CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:
- Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
- System exception names to interface to system exceptions without having compatibility issues.
- Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
- Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
- Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
- A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
The following sections provide details about the CMSIS-Core (Cortex-M):
- Using CMSIS in Embedded Applications describes the project setup and shows a simple program example.
- Using TrustZone® for Armv8-M describes how to use the security extensions available in the Armv8-M architecture.
- CMSIS-Core Device Templates describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
- MISRA-C Deviations describes the violations to the MISRA standard.
- Reference describe the features and functions of the Device Header File <device.h> in detail.
- Data Structures describe the data structures of the Device Header File <device.h> in detail.
CMSIS-Core (Cortex-M) in ARM::CMSIS Pack
Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:
|CMSIS\Core\Include||CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)|
|Device||Arm reference implementations of Cortex-M devices|
|Device\_Template_Vendor||CMSIS-Core Device Templates for extension by silicon vendors|
The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:
- Cortex-M0 Devices Generic User Guide (Armv6-M architecture)
- Cortex-M0+ Devices Generic User Guide (Armv6-M architecture)
- Cortex-M3 Devices Generic User Guide (Armv7-M architecture)
- Cortex-M4 Devices Generic User Guide (ARMv7-M architecture)
- Cortex-M7 Devices Generic User Guide (Armv7-M architecture)
The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:
- Cortex-M23 Technical Reference Manual (Armv8-M baseline architecture)
- Cortex-M33 Technical Reference Manual (Armv8-M mainline architecture)
Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.
The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.
The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:
- Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
- Arm: Arm Compiler 6.9
- Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
- GNU: GNU Tools for Arm Embedded 6.3.1 20170620
- IAR: IAR ANSI C/C++ Compiler for Arm 126.96.36.19983