Description

Macros

#define UARTDRV_STATUS_RXEN   (1 << 0)
 The receiver is enabled.
 
#define UARTDRV_STATUS_TXEN   (1 << 1)
 The transmitter is enabled.
 
#define UARTDRV_STATUS_RXBLOCK   (1 << 3)
 The receiver is blocked; incoming frames will be discarded.
 
#define UARTDRV_STATUS_TXTRI   (1 << 4)
 The transmitter is tristated.
 
#define UARTDRV_STATUS_TXC   (1 << 5)
 A transmit operation is complete. No more data is available in the transmit buffer and shift register.
 
#define UARTDRV_STATUS_TXBL   (1 << 6)
 The transmit buffer is empty.
 
#define UARTDRV_STATUS_RXDATAV   (1 << 7)
 Data is available in the receive buffer.
 
#define UARTDRV_STATUS_RXFULL   (1 << 8)
 The receive buffer is full.
 
#define UARTDRV_STATUS_TXIDLE   (1 << 13)
 The transmitter is idle.
 
#define UARTDRV_STATUS_RXIDLE   (1 << 12)
 The Receiver is idle.
 

Macro Definition Documentation

◆ UARTDRV_STATUS_RXEN

#define UARTDRV_STATUS_RXEN   (1 << 0)

The receiver is enabled.

◆ UARTDRV_STATUS_TXEN

#define UARTDRV_STATUS_TXEN   (1 << 1)

The transmitter is enabled.

◆ UARTDRV_STATUS_RXBLOCK

#define UARTDRV_STATUS_RXBLOCK   (1 << 3)

The receiver is blocked; incoming frames will be discarded.

◆ UARTDRV_STATUS_TXTRI

#define UARTDRV_STATUS_TXTRI   (1 << 4)

The transmitter is tristated.

◆ UARTDRV_STATUS_TXC

#define UARTDRV_STATUS_TXC   (1 << 5)

A transmit operation is complete. No more data is available in the transmit buffer and shift register.

◆ UARTDRV_STATUS_TXBL

#define UARTDRV_STATUS_TXBL   (1 << 6)

The transmit buffer is empty.

◆ UARTDRV_STATUS_RXDATAV

#define UARTDRV_STATUS_RXDATAV   (1 << 7)

Data is available in the receive buffer.

◆ UARTDRV_STATUS_RXFULL

#define UARTDRV_STATUS_RXFULL   (1 << 8)

The receive buffer is full.

◆ UARTDRV_STATUS_TXIDLE

#define UARTDRV_STATUS_TXIDLE   (1 << 13)

The transmitter is idle.

◆ UARTDRV_STATUS_RXIDLE

#define UARTDRV_STATUS_RXIDLE   (1 << 12)

The Receiver is idle.