SMU Bit FieldsDevices > SMU

Macros

#define _SMU_IEN_MASK   0x00000001UL
 
#define _SMU_IEN_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IEN_PPUPRIV_MASK   0x1UL
 
#define _SMU_IEN_PPUPRIV_SHIFT   0
 
#define _SMU_IEN_RESETVALUE   0x00000000UL
 
#define _SMU_IF_MASK   0x00000001UL
 
#define _SMU_IF_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IF_PPUPRIV_MASK   0x1UL
 
#define _SMU_IF_PPUPRIV_SHIFT   0
 
#define _SMU_IF_RESETVALUE   0x00000000UL
 
#define _SMU_IFC_MASK   0x00000001UL
 
#define _SMU_IFC_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IFC_PPUPRIV_MASK   0x1UL
 
#define _SMU_IFC_PPUPRIV_SHIFT   0
 
#define _SMU_IFC_RESETVALUE   0x00000000UL
 
#define _SMU_IFS_MASK   0x00000001UL
 
#define _SMU_IFS_PPUPRIV_DEFAULT   0x00000000UL
 
#define _SMU_IFS_PPUPRIV_MASK   0x1UL
 
#define _SMU_IFS_PPUPRIV_SHIFT   0
 
#define _SMU_IFS_RESETVALUE   0x00000000UL
 
#define _SMU_PPUCTRL_ENABLE_DEFAULT   0x00000000UL
 
#define _SMU_PPUCTRL_ENABLE_MASK   0x1UL
 
#define _SMU_PPUCTRL_ENABLE_SHIFT   0
 
#define _SMU_PPUCTRL_MASK   0x00000001UL
 
#define _SMU_PPUCTRL_RESETVALUE   0x00000000UL
 
#define _SMU_PPUFS_MASK   0x0000007FUL
 
#define _SMU_PPUFS_PERIPHID_ACMP0   0x00000000UL
 
#define _SMU_PPUFS_PERIPHID_ACMP1   0x00000001UL
 
#define _SMU_PPUFS_PERIPHID_ACMP2   0x00000002UL
 
#define _SMU_PPUFS_PERIPHID_ACMP3   0x00000003UL
 
#define _SMU_PPUFS_PERIPHID_ADC0   0x00000004UL
 
#define _SMU_PPUFS_PERIPHID_ADC1   0x00000005UL
 
#define _SMU_PPUFS_PERIPHID_CAN0   0x00000006UL
 
#define _SMU_PPUFS_PERIPHID_CAN1   0x00000007UL
 
#define _SMU_PPUFS_PERIPHID_CMU   0x00000008UL
 
#define _SMU_PPUFS_PERIPHID_CRYOTIMER   0x00000009UL
 
#define _SMU_PPUFS_PERIPHID_CRYPTO0   0x0000000AUL
 
#define _SMU_PPUFS_PERIPHID_CSEN   0x0000000BUL
 
#define _SMU_PPUFS_PERIPHID_DEFAULT   0x00000000UL
 
#define _SMU_PPUFS_PERIPHID_EBI   0x0000000EUL
 
#define _SMU_PPUFS_PERIPHID_EMU   0x0000000FUL
 
#define _SMU_PPUFS_PERIPHID_ETH   0x00000010UL
 
#define _SMU_PPUFS_PERIPHID_FPUEH   0x00000011UL
 
#define _SMU_PPUFS_PERIPHID_GPCRC   0x00000012UL
 
#define _SMU_PPUFS_PERIPHID_GPIO   0x00000013UL
 
#define _SMU_PPUFS_PERIPHID_I2C0   0x00000014UL
 
#define _SMU_PPUFS_PERIPHID_I2C1   0x00000015UL
 
#define _SMU_PPUFS_PERIPHID_I2C2   0x00000016UL
 
#define _SMU_PPUFS_PERIPHID_IDAC0   0x00000017UL
 
#define _SMU_PPUFS_PERIPHID_LCD   0x00000019UL
 
#define _SMU_PPUFS_PERIPHID_LDMA   0x0000001AUL
 
#define _SMU_PPUFS_PERIPHID_LESENSE   0x0000001BUL
 
#define _SMU_PPUFS_PERIPHID_LETIMER0   0x0000001CUL
 
#define _SMU_PPUFS_PERIPHID_LETIMER1   0x0000001DUL
 
#define _SMU_PPUFS_PERIPHID_LEUART0   0x0000001EUL
 
#define _SMU_PPUFS_PERIPHID_LEUART1   0x0000001FUL
 
#define _SMU_PPUFS_PERIPHID_MASK   0x7FUL
 
#define _SMU_PPUFS_PERIPHID_MSC   0x00000018UL
 
#define _SMU_PPUFS_PERIPHID_PCNT0   0x00000020UL
 
#define _SMU_PPUFS_PERIPHID_PCNT1   0x00000021UL
 
#define _SMU_PPUFS_PERIPHID_PCNT2   0x00000022UL
 
#define _SMU_PPUFS_PERIPHID_PRS   0x0000000DUL
 
#define _SMU_PPUFS_PERIPHID_QSPI0   0x00000023UL
 
#define _SMU_PPUFS_PERIPHID_RMU   0x00000024UL
 
#define _SMU_PPUFS_PERIPHID_RTC   0x00000025UL
 
#define _SMU_PPUFS_PERIPHID_RTCC   0x00000026UL
 
#define _SMU_PPUFS_PERIPHID_SDIO   0x00000027UL
 
#define _SMU_PPUFS_PERIPHID_SHIFT   0
 
#define _SMU_PPUFS_PERIPHID_SMU   0x00000028UL
 
#define _SMU_PPUFS_PERIPHID_TIMER0   0x00000029UL
 
#define _SMU_PPUFS_PERIPHID_TIMER1   0x0000002AUL
 
#define _SMU_PPUFS_PERIPHID_TIMER2   0x0000002BUL
 
#define _SMU_PPUFS_PERIPHID_TIMER3   0x0000002CUL
 
#define _SMU_PPUFS_PERIPHID_TIMER4   0x0000002DUL
 
#define _SMU_PPUFS_PERIPHID_TIMER5   0x0000002EUL
 
#define _SMU_PPUFS_PERIPHID_TIMER6   0x0000002FUL
 
#define _SMU_PPUFS_PERIPHID_TRNG0   0x00000030UL
 
#define _SMU_PPUFS_PERIPHID_UART0   0x00000031UL
 
#define _SMU_PPUFS_PERIPHID_UART1   0x00000032UL
 
#define _SMU_PPUFS_PERIPHID_USART0   0x00000033UL
 
#define _SMU_PPUFS_PERIPHID_USART1   0x00000034UL
 
#define _SMU_PPUFS_PERIPHID_USART2   0x00000035UL
 
#define _SMU_PPUFS_PERIPHID_USART3   0x00000036UL
 
#define _SMU_PPUFS_PERIPHID_USART4   0x00000037UL
 
#define _SMU_PPUFS_PERIPHID_USART5   0x00000038UL
 
#define _SMU_PPUFS_PERIPHID_USB   0x00000039UL
 
#define _SMU_PPUFS_PERIPHID_VDAC0   0x0000000CUL
 
#define _SMU_PPUFS_PERIPHID_WDOG0   0x0000003AUL
 
#define _SMU_PPUFS_PERIPHID_WDOG1   0x0000003BUL
 
#define _SMU_PPUFS_PERIPHID_WTIMER0   0x0000003CUL
 
#define _SMU_PPUFS_PERIPHID_WTIMER1   0x0000003DUL
 
#define _SMU_PPUFS_PERIPHID_WTIMER2   0x0000003EUL
 
#define _SMU_PPUFS_PERIPHID_WTIMER3   0x0000003FUL
 
#define _SMU_PPUFS_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP0_MASK   0x1UL
 
#define _SMU_PPUPATD0_ACMP0_SHIFT   0
 
#define _SMU_PPUPATD0_ACMP1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP1_MASK   0x2UL
 
#define _SMU_PPUPATD0_ACMP1_SHIFT   1
 
#define _SMU_PPUPATD0_ACMP2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP2_MASK   0x4UL
 
#define _SMU_PPUPATD0_ACMP2_SHIFT   2
 
#define _SMU_PPUPATD0_ACMP3_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ACMP3_MASK   0x8UL
 
#define _SMU_PPUPATD0_ACMP3_SHIFT   3
 
#define _SMU_PPUPATD0_ADC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ADC0_MASK   0x10UL
 
#define _SMU_PPUPATD0_ADC0_SHIFT   4
 
#define _SMU_PPUPATD0_ADC1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ADC1_MASK   0x20UL
 
#define _SMU_PPUPATD0_ADC1_SHIFT   5
 
#define _SMU_PPUPATD0_CAN0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CAN0_MASK   0x40UL
 
#define _SMU_PPUPATD0_CAN0_SHIFT   6
 
#define _SMU_PPUPATD0_CAN1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CAN1_MASK   0x80UL
 
#define _SMU_PPUPATD0_CAN1_SHIFT   7
 
#define _SMU_PPUPATD0_CMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CMU_MASK   0x100UL
 
#define _SMU_PPUPATD0_CMU_SHIFT   8
 
#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CRYOTIMER_MASK   0x200UL
 
#define _SMU_PPUPATD0_CRYOTIMER_SHIFT   9
 
#define _SMU_PPUPATD0_CRYPTO0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CRYPTO0_MASK   0x400UL
 
#define _SMU_PPUPATD0_CRYPTO0_SHIFT   10
 
#define _SMU_PPUPATD0_CSEN_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_CSEN_MASK   0x800UL
 
#define _SMU_PPUPATD0_CSEN_SHIFT   11
 
#define _SMU_PPUPATD0_EBI_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_EBI_MASK   0x4000UL
 
#define _SMU_PPUPATD0_EBI_SHIFT   14
 
#define _SMU_PPUPATD0_EMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_EMU_MASK   0x8000UL
 
#define _SMU_PPUPATD0_EMU_SHIFT   15
 
#define _SMU_PPUPATD0_ETH_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_ETH_MASK   0x10000UL
 
#define _SMU_PPUPATD0_ETH_SHIFT   16
 
#define _SMU_PPUPATD0_FPUEH_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_FPUEH_MASK   0x20000UL
 
#define _SMU_PPUPATD0_FPUEH_SHIFT   17
 
#define _SMU_PPUPATD0_GPCRC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_GPCRC_MASK   0x40000UL
 
#define _SMU_PPUPATD0_GPCRC_SHIFT   18
 
#define _SMU_PPUPATD0_GPIO_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_GPIO_MASK   0x80000UL
 
#define _SMU_PPUPATD0_GPIO_SHIFT   19
 
#define _SMU_PPUPATD0_I2C0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_I2C0_MASK   0x100000UL
 
#define _SMU_PPUPATD0_I2C0_SHIFT   20
 
#define _SMU_PPUPATD0_I2C1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_I2C1_MASK   0x200000UL
 
#define _SMU_PPUPATD0_I2C1_SHIFT   21
 
#define _SMU_PPUPATD0_I2C2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_I2C2_MASK   0x400000UL
 
#define _SMU_PPUPATD0_I2C2_SHIFT   22
 
#define _SMU_PPUPATD0_IDAC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_IDAC0_MASK   0x800000UL
 
#define _SMU_PPUPATD0_IDAC0_SHIFT   23
 
#define _SMU_PPUPATD0_LCD_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LCD_MASK   0x2000000UL
 
#define _SMU_PPUPATD0_LCD_SHIFT   25
 
#define _SMU_PPUPATD0_LDMA_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LDMA_MASK   0x4000000UL
 
#define _SMU_PPUPATD0_LDMA_SHIFT   26
 
#define _SMU_PPUPATD0_LESENSE_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LESENSE_MASK   0x8000000UL
 
#define _SMU_PPUPATD0_LESENSE_SHIFT   27
 
#define _SMU_PPUPATD0_LETIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LETIMER0_MASK   0x10000000UL
 
#define _SMU_PPUPATD0_LETIMER0_SHIFT   28
 
#define _SMU_PPUPATD0_LETIMER1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LETIMER1_MASK   0x20000000UL
 
#define _SMU_PPUPATD0_LETIMER1_SHIFT   29
 
#define _SMU_PPUPATD0_LEUART0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LEUART0_MASK   0x40000000UL
 
#define _SMU_PPUPATD0_LEUART0_SHIFT   30
 
#define _SMU_PPUPATD0_LEUART1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_LEUART1_MASK   0x80000000UL
 
#define _SMU_PPUPATD0_LEUART1_SHIFT   31
 
#define _SMU_PPUPATD0_MASK   0xFFFFFFFFUL
 
#define _SMU_PPUPATD0_MSC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_MSC_MASK   0x1000000UL
 
#define _SMU_PPUPATD0_MSC_SHIFT   24
 
#define _SMU_PPUPATD0_PRS_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_PRS_MASK   0x2000UL
 
#define _SMU_PPUPATD0_PRS_SHIFT   13
 
#define _SMU_PPUPATD0_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD0_VDAC0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD0_VDAC0_MASK   0x1000UL
 
#define _SMU_PPUPATD0_VDAC0_SHIFT   12
 
#define _SMU_PPUPATD1_MASK   0xFFFFFFFFUL
 
#define _SMU_PPUPATD1_PCNT0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_PCNT0_MASK   0x1UL
 
#define _SMU_PPUPATD1_PCNT0_SHIFT   0
 
#define _SMU_PPUPATD1_PCNT1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_PCNT1_MASK   0x2UL
 
#define _SMU_PPUPATD1_PCNT1_SHIFT   1
 
#define _SMU_PPUPATD1_PCNT2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_PCNT2_MASK   0x4UL
 
#define _SMU_PPUPATD1_PCNT2_SHIFT   2
 
#define _SMU_PPUPATD1_QSPI0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_QSPI0_MASK   0x8UL
 
#define _SMU_PPUPATD1_QSPI0_SHIFT   3
 
#define _SMU_PPUPATD1_RESETVALUE   0x00000000UL
 
#define _SMU_PPUPATD1_RMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_RMU_MASK   0x10UL
 
#define _SMU_PPUPATD1_RMU_SHIFT   4
 
#define _SMU_PPUPATD1_RTC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_RTC_MASK   0x20UL
 
#define _SMU_PPUPATD1_RTC_SHIFT   5
 
#define _SMU_PPUPATD1_RTCC_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_RTCC_MASK   0x40UL
 
#define _SMU_PPUPATD1_RTCC_SHIFT   6
 
#define _SMU_PPUPATD1_SDIO_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_SDIO_MASK   0x80UL
 
#define _SMU_PPUPATD1_SDIO_SHIFT   7
 
#define _SMU_PPUPATD1_SMU_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_SMU_MASK   0x100UL
 
#define _SMU_PPUPATD1_SMU_SHIFT   8
 
#define _SMU_PPUPATD1_TIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER0_MASK   0x200UL
 
#define _SMU_PPUPATD1_TIMER0_SHIFT   9
 
#define _SMU_PPUPATD1_TIMER1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER1_MASK   0x400UL
 
#define _SMU_PPUPATD1_TIMER1_SHIFT   10
 
#define _SMU_PPUPATD1_TIMER2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER2_MASK   0x800UL
 
#define _SMU_PPUPATD1_TIMER2_SHIFT   11
 
#define _SMU_PPUPATD1_TIMER3_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER3_MASK   0x1000UL
 
#define _SMU_PPUPATD1_TIMER3_SHIFT   12
 
#define _SMU_PPUPATD1_TIMER4_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER4_MASK   0x2000UL
 
#define _SMU_PPUPATD1_TIMER4_SHIFT   13
 
#define _SMU_PPUPATD1_TIMER5_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER5_MASK   0x4000UL
 
#define _SMU_PPUPATD1_TIMER5_SHIFT   14
 
#define _SMU_PPUPATD1_TIMER6_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TIMER6_MASK   0x8000UL
 
#define _SMU_PPUPATD1_TIMER6_SHIFT   15
 
#define _SMU_PPUPATD1_TRNG0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_TRNG0_MASK   0x10000UL
 
#define _SMU_PPUPATD1_TRNG0_SHIFT   16
 
#define _SMU_PPUPATD1_UART0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_UART0_MASK   0x20000UL
 
#define _SMU_PPUPATD1_UART0_SHIFT   17
 
#define _SMU_PPUPATD1_UART1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_UART1_MASK   0x40000UL
 
#define _SMU_PPUPATD1_UART1_SHIFT   18
 
#define _SMU_PPUPATD1_USART0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART0_MASK   0x80000UL
 
#define _SMU_PPUPATD1_USART0_SHIFT   19
 
#define _SMU_PPUPATD1_USART1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART1_MASK   0x100000UL
 
#define _SMU_PPUPATD1_USART1_SHIFT   20
 
#define _SMU_PPUPATD1_USART2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART2_MASK   0x200000UL
 
#define _SMU_PPUPATD1_USART2_SHIFT   21
 
#define _SMU_PPUPATD1_USART3_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART3_MASK   0x400000UL
 
#define _SMU_PPUPATD1_USART3_SHIFT   22
 
#define _SMU_PPUPATD1_USART4_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART4_MASK   0x800000UL
 
#define _SMU_PPUPATD1_USART4_SHIFT   23
 
#define _SMU_PPUPATD1_USART5_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USART5_MASK   0x1000000UL
 
#define _SMU_PPUPATD1_USART5_SHIFT   24
 
#define _SMU_PPUPATD1_USB_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_USB_MASK   0x2000000UL
 
#define _SMU_PPUPATD1_USB_SHIFT   25
 
#define _SMU_PPUPATD1_WDOG0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WDOG0_MASK   0x4000000UL
 
#define _SMU_PPUPATD1_WDOG0_SHIFT   26
 
#define _SMU_PPUPATD1_WDOG1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WDOG1_MASK   0x8000000UL
 
#define _SMU_PPUPATD1_WDOG1_SHIFT   27
 
#define _SMU_PPUPATD1_WTIMER0_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WTIMER0_MASK   0x10000000UL
 
#define _SMU_PPUPATD1_WTIMER0_SHIFT   28
 
#define _SMU_PPUPATD1_WTIMER1_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WTIMER1_MASK   0x20000000UL
 
#define _SMU_PPUPATD1_WTIMER1_SHIFT   29
 
#define _SMU_PPUPATD1_WTIMER2_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WTIMER2_MASK   0x40000000UL
 
#define _SMU_PPUPATD1_WTIMER2_SHIFT   30
 
#define _SMU_PPUPATD1_WTIMER3_DEFAULT   0x00000000UL
 
#define _SMU_PPUPATD1_WTIMER3_MASK   0x80000000UL
 
#define _SMU_PPUPATD1_WTIMER3_SHIFT   31
 
#define _SMU_PPUPATD2_MASK   0x00000000UL
 
#define _SMU_PPUPATD2_RESETVALUE   0x00000000UL
 
#define SMU_IEN_PPUPRIV   (0x1UL << 0)
 
#define SMU_IEN_PPUPRIV_DEFAULT   (_SMU_IEN_PPUPRIV_DEFAULT << 0)
 
#define SMU_IF_PPUPRIV   (0x1UL << 0)
 
#define SMU_IF_PPUPRIV_DEFAULT   (_SMU_IF_PPUPRIV_DEFAULT << 0)
 
#define SMU_IFC_PPUPRIV   (0x1UL << 0)
 
#define SMU_IFC_PPUPRIV_DEFAULT   (_SMU_IFC_PPUPRIV_DEFAULT << 0)
 
#define SMU_IFS_PPUPRIV   (0x1UL << 0)
 
#define SMU_IFS_PPUPRIV_DEFAULT   (_SMU_IFS_PPUPRIV_DEFAULT << 0)
 
#define SMU_PPUCTRL_ENABLE   (0x1UL << 0)
 
#define SMU_PPUCTRL_ENABLE_DEFAULT   (_SMU_PPUCTRL_ENABLE_DEFAULT << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP0   (_SMU_PPUFS_PERIPHID_ACMP0 << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP1   (_SMU_PPUFS_PERIPHID_ACMP1 << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP2   (_SMU_PPUFS_PERIPHID_ACMP2 << 0)
 
#define SMU_PPUFS_PERIPHID_ACMP3   (_SMU_PPUFS_PERIPHID_ACMP3 << 0)
 
#define SMU_PPUFS_PERIPHID_ADC0   (_SMU_PPUFS_PERIPHID_ADC0 << 0)
 
#define SMU_PPUFS_PERIPHID_ADC1   (_SMU_PPUFS_PERIPHID_ADC1 << 0)
 
#define SMU_PPUFS_PERIPHID_CAN0   (_SMU_PPUFS_PERIPHID_CAN0 << 0)
 
#define SMU_PPUFS_PERIPHID_CAN1   (_SMU_PPUFS_PERIPHID_CAN1 << 0)
 
#define SMU_PPUFS_PERIPHID_CMU   (_SMU_PPUFS_PERIPHID_CMU << 0)
 
#define SMU_PPUFS_PERIPHID_CRYOTIMER   (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0)
 
#define SMU_PPUFS_PERIPHID_CRYPTO0   (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0)
 
#define SMU_PPUFS_PERIPHID_CSEN   (_SMU_PPUFS_PERIPHID_CSEN << 0)
 
#define SMU_PPUFS_PERIPHID_DEFAULT   (_SMU_PPUFS_PERIPHID_DEFAULT << 0)
 
#define SMU_PPUFS_PERIPHID_EBI   (_SMU_PPUFS_PERIPHID_EBI << 0)
 
#define SMU_PPUFS_PERIPHID_EMU   (_SMU_PPUFS_PERIPHID_EMU << 0)
 
#define SMU_PPUFS_PERIPHID_ETH   (_SMU_PPUFS_PERIPHID_ETH << 0)
 
#define SMU_PPUFS_PERIPHID_FPUEH   (_SMU_PPUFS_PERIPHID_FPUEH << 0)
 
#define SMU_PPUFS_PERIPHID_GPCRC   (_SMU_PPUFS_PERIPHID_GPCRC << 0)
 
#define SMU_PPUFS_PERIPHID_GPIO   (_SMU_PPUFS_PERIPHID_GPIO << 0)
 
#define SMU_PPUFS_PERIPHID_I2C0   (_SMU_PPUFS_PERIPHID_I2C0 << 0)
 
#define SMU_PPUFS_PERIPHID_I2C1   (_SMU_PPUFS_PERIPHID_I2C1 << 0)
 
#define SMU_PPUFS_PERIPHID_I2C2   (_SMU_PPUFS_PERIPHID_I2C2 << 0)
 
#define SMU_PPUFS_PERIPHID_IDAC0   (_SMU_PPUFS_PERIPHID_IDAC0 << 0)
 
#define SMU_PPUFS_PERIPHID_LCD   (_SMU_PPUFS_PERIPHID_LCD << 0)
 
#define SMU_PPUFS_PERIPHID_LDMA   (_SMU_PPUFS_PERIPHID_LDMA << 0)
 
#define SMU_PPUFS_PERIPHID_LESENSE   (_SMU_PPUFS_PERIPHID_LESENSE << 0)
 
#define SMU_PPUFS_PERIPHID_LETIMER0   (_SMU_PPUFS_PERIPHID_LETIMER0 << 0)
 
#define SMU_PPUFS_PERIPHID_LETIMER1   (_SMU_PPUFS_PERIPHID_LETIMER1 << 0)
 
#define SMU_PPUFS_PERIPHID_LEUART0   (_SMU_PPUFS_PERIPHID_LEUART0 << 0)
 
#define SMU_PPUFS_PERIPHID_LEUART1   (_SMU_PPUFS_PERIPHID_LEUART1 << 0)
 
#define SMU_PPUFS_PERIPHID_MSC   (_SMU_PPUFS_PERIPHID_MSC << 0)
 
#define SMU_PPUFS_PERIPHID_PCNT0   (_SMU_PPUFS_PERIPHID_PCNT0 << 0)
 
#define SMU_PPUFS_PERIPHID_PCNT1   (_SMU_PPUFS_PERIPHID_PCNT1 << 0)
 
#define SMU_PPUFS_PERIPHID_PCNT2   (_SMU_PPUFS_PERIPHID_PCNT2 << 0)
 
#define SMU_PPUFS_PERIPHID_PRS   (_SMU_PPUFS_PERIPHID_PRS << 0)
 
#define SMU_PPUFS_PERIPHID_QSPI0   (_SMU_PPUFS_PERIPHID_QSPI0 << 0)
 
#define SMU_PPUFS_PERIPHID_RMU   (_SMU_PPUFS_PERIPHID_RMU << 0)
 
#define SMU_PPUFS_PERIPHID_RTC   (_SMU_PPUFS_PERIPHID_RTC << 0)
 
#define SMU_PPUFS_PERIPHID_RTCC   (_SMU_PPUFS_PERIPHID_RTCC << 0)
 
#define SMU_PPUFS_PERIPHID_SDIO   (_SMU_PPUFS_PERIPHID_SDIO << 0)
 
#define SMU_PPUFS_PERIPHID_SMU   (_SMU_PPUFS_PERIPHID_SMU << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER0   (_SMU_PPUFS_PERIPHID_TIMER0 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER1   (_SMU_PPUFS_PERIPHID_TIMER1 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER2   (_SMU_PPUFS_PERIPHID_TIMER2 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER3   (_SMU_PPUFS_PERIPHID_TIMER3 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER4   (_SMU_PPUFS_PERIPHID_TIMER4 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER5   (_SMU_PPUFS_PERIPHID_TIMER5 << 0)
 
#define SMU_PPUFS_PERIPHID_TIMER6   (_SMU_PPUFS_PERIPHID_TIMER6 << 0)
 
#define SMU_PPUFS_PERIPHID_TRNG0   (_SMU_PPUFS_PERIPHID_TRNG0 << 0)
 
#define SMU_PPUFS_PERIPHID_UART0   (_SMU_PPUFS_PERIPHID_UART0 << 0)
 
#define SMU_PPUFS_PERIPHID_UART1   (_SMU_PPUFS_PERIPHID_UART1 << 0)
 
#define SMU_PPUFS_PERIPHID_USART0   (_SMU_PPUFS_PERIPHID_USART0 << 0)
 
#define SMU_PPUFS_PERIPHID_USART1   (_SMU_PPUFS_PERIPHID_USART1 << 0)
 
#define SMU_PPUFS_PERIPHID_USART2   (_SMU_PPUFS_PERIPHID_USART2 << 0)
 
#define SMU_PPUFS_PERIPHID_USART3   (_SMU_PPUFS_PERIPHID_USART3 << 0)
 
#define SMU_PPUFS_PERIPHID_USART4   (_SMU_PPUFS_PERIPHID_USART4 << 0)
 
#define SMU_PPUFS_PERIPHID_USART5   (_SMU_PPUFS_PERIPHID_USART5 << 0)
 
#define SMU_PPUFS_PERIPHID_USB   (_SMU_PPUFS_PERIPHID_USB << 0)
 
#define SMU_PPUFS_PERIPHID_VDAC0   (_SMU_PPUFS_PERIPHID_VDAC0 << 0)
 
#define SMU_PPUFS_PERIPHID_WDOG0   (_SMU_PPUFS_PERIPHID_WDOG0 << 0)
 
#define SMU_PPUFS_PERIPHID_WDOG1   (_SMU_PPUFS_PERIPHID_WDOG1 << 0)
 
#define SMU_PPUFS_PERIPHID_WTIMER0   (_SMU_PPUFS_PERIPHID_WTIMER0 << 0)
 
#define SMU_PPUFS_PERIPHID_WTIMER1   (_SMU_PPUFS_PERIPHID_WTIMER1 << 0)
 
#define SMU_PPUFS_PERIPHID_WTIMER2   (_SMU_PPUFS_PERIPHID_WTIMER2 << 0)
 
#define SMU_PPUFS_PERIPHID_WTIMER3   (_SMU_PPUFS_PERIPHID_WTIMER3 << 0)
 
#define SMU_PPUPATD0_ACMP0   (0x1UL << 0)
 
#define SMU_PPUPATD0_ACMP0_DEFAULT   (_SMU_PPUPATD0_ACMP0_DEFAULT << 0)
 
#define SMU_PPUPATD0_ACMP1   (0x1UL << 1)
 
#define SMU_PPUPATD0_ACMP1_DEFAULT   (_SMU_PPUPATD0_ACMP1_DEFAULT << 1)
 
#define SMU_PPUPATD0_ACMP2   (0x1UL << 2)
 
#define SMU_PPUPATD0_ACMP2_DEFAULT   (_SMU_PPUPATD0_ACMP2_DEFAULT << 2)
 
#define SMU_PPUPATD0_ACMP3   (0x1UL << 3)
 
#define SMU_PPUPATD0_ACMP3_DEFAULT   (_SMU_PPUPATD0_ACMP3_DEFAULT << 3)
 
#define SMU_PPUPATD0_ADC0   (0x1UL << 4)
 
#define SMU_PPUPATD0_ADC0_DEFAULT   (_SMU_PPUPATD0_ADC0_DEFAULT << 4)
 
#define SMU_PPUPATD0_ADC1   (0x1UL << 5)
 
#define SMU_PPUPATD0_ADC1_DEFAULT   (_SMU_PPUPATD0_ADC1_DEFAULT << 5)
 
#define SMU_PPUPATD0_CAN0   (0x1UL << 6)
 
#define SMU_PPUPATD0_CAN0_DEFAULT   (_SMU_PPUPATD0_CAN0_DEFAULT << 6)
 
#define SMU_PPUPATD0_CAN1   (0x1UL << 7)
 
#define SMU_PPUPATD0_CAN1_DEFAULT   (_SMU_PPUPATD0_CAN1_DEFAULT << 7)
 
#define SMU_PPUPATD0_CMU   (0x1UL << 8)
 
#define SMU_PPUPATD0_CMU_DEFAULT   (_SMU_PPUPATD0_CMU_DEFAULT << 8)
 
#define SMU_PPUPATD0_CRYOTIMER   (0x1UL << 9)
 
#define SMU_PPUPATD0_CRYOTIMER_DEFAULT   (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9)
 
#define SMU_PPUPATD0_CRYPTO0   (0x1UL << 10)
 
#define SMU_PPUPATD0_CRYPTO0_DEFAULT   (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10)
 
#define SMU_PPUPATD0_CSEN   (0x1UL << 11)
 
#define SMU_PPUPATD0_CSEN_DEFAULT   (_SMU_PPUPATD0_CSEN_DEFAULT << 11)
 
#define SMU_PPUPATD0_EBI   (0x1UL << 14)
 
#define SMU_PPUPATD0_EBI_DEFAULT   (_SMU_PPUPATD0_EBI_DEFAULT << 14)
 
#define SMU_PPUPATD0_EMU   (0x1UL << 15)
 
#define SMU_PPUPATD0_EMU_DEFAULT   (_SMU_PPUPATD0_EMU_DEFAULT << 15)
 
#define SMU_PPUPATD0_ETH   (0x1UL << 16)
 
#define SMU_PPUPATD0_ETH_DEFAULT   (_SMU_PPUPATD0_ETH_DEFAULT << 16)
 
#define SMU_PPUPATD0_FPUEH   (0x1UL << 17)
 
#define SMU_PPUPATD0_FPUEH_DEFAULT   (_SMU_PPUPATD0_FPUEH_DEFAULT << 17)
 
#define SMU_PPUPATD0_GPCRC   (0x1UL << 18)
 
#define SMU_PPUPATD0_GPCRC_DEFAULT   (_SMU_PPUPATD0_GPCRC_DEFAULT << 18)
 
#define SMU_PPUPATD0_GPIO   (0x1UL << 19)
 
#define SMU_PPUPATD0_GPIO_DEFAULT   (_SMU_PPUPATD0_GPIO_DEFAULT << 19)
 
#define SMU_PPUPATD0_I2C0   (0x1UL << 20)
 
#define SMU_PPUPATD0_I2C0_DEFAULT   (_SMU_PPUPATD0_I2C0_DEFAULT << 20)
 
#define SMU_PPUPATD0_I2C1   (0x1UL << 21)
 
#define SMU_PPUPATD0_I2C1_DEFAULT   (_SMU_PPUPATD0_I2C1_DEFAULT << 21)
 
#define SMU_PPUPATD0_I2C2   (0x1UL << 22)
 
#define SMU_PPUPATD0_I2C2_DEFAULT   (_SMU_PPUPATD0_I2C2_DEFAULT << 22)
 
#define SMU_PPUPATD0_IDAC0   (0x1UL << 23)
 
#define SMU_PPUPATD0_IDAC0_DEFAULT   (_SMU_PPUPATD0_IDAC0_DEFAULT << 23)
 
#define SMU_PPUPATD0_LCD   (0x1UL << 25)
 
#define SMU_PPUPATD0_LCD_DEFAULT   (_SMU_PPUPATD0_LCD_DEFAULT << 25)
 
#define SMU_PPUPATD0_LDMA   (0x1UL << 26)
 
#define SMU_PPUPATD0_LDMA_DEFAULT   (_SMU_PPUPATD0_LDMA_DEFAULT << 26)
 
#define SMU_PPUPATD0_LESENSE   (0x1UL << 27)
 
#define SMU_PPUPATD0_LESENSE_DEFAULT   (_SMU_PPUPATD0_LESENSE_DEFAULT << 27)
 
#define SMU_PPUPATD0_LETIMER0   (0x1UL << 28)
 
#define SMU_PPUPATD0_LETIMER0_DEFAULT   (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28)
 
#define SMU_PPUPATD0_LETIMER1   (0x1UL << 29)
 
#define SMU_PPUPATD0_LETIMER1_DEFAULT   (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29)
 
#define SMU_PPUPATD0_LEUART0   (0x1UL << 30)
 
#define SMU_PPUPATD0_LEUART0_DEFAULT   (_SMU_PPUPATD0_LEUART0_DEFAULT << 30)
 
#define SMU_PPUPATD0_LEUART1   (0x1UL << 31)
 
#define SMU_PPUPATD0_LEUART1_DEFAULT   (_SMU_PPUPATD0_LEUART1_DEFAULT << 31)
 
#define SMU_PPUPATD0_MSC   (0x1UL << 24)
 
#define SMU_PPUPATD0_MSC_DEFAULT   (_SMU_PPUPATD0_MSC_DEFAULT << 24)
 
#define SMU_PPUPATD0_PRS   (0x1UL << 13)
 
#define SMU_PPUPATD0_PRS_DEFAULT   (_SMU_PPUPATD0_PRS_DEFAULT << 13)
 
#define SMU_PPUPATD0_VDAC0   (0x1UL << 12)
 
#define SMU_PPUPATD0_VDAC0_DEFAULT   (_SMU_PPUPATD0_VDAC0_DEFAULT << 12)
 
#define SMU_PPUPATD1_PCNT0   (0x1UL << 0)
 
#define SMU_PPUPATD1_PCNT0_DEFAULT   (_SMU_PPUPATD1_PCNT0_DEFAULT << 0)
 
#define SMU_PPUPATD1_PCNT1   (0x1UL << 1)
 
#define SMU_PPUPATD1_PCNT1_DEFAULT   (_SMU_PPUPATD1_PCNT1_DEFAULT << 1)
 
#define SMU_PPUPATD1_PCNT2   (0x1UL << 2)
 
#define SMU_PPUPATD1_PCNT2_DEFAULT   (_SMU_PPUPATD1_PCNT2_DEFAULT << 2)
 
#define SMU_PPUPATD1_QSPI0   (0x1UL << 3)
 
#define SMU_PPUPATD1_QSPI0_DEFAULT   (_SMU_PPUPATD1_QSPI0_DEFAULT << 3)
 
#define SMU_PPUPATD1_RMU   (0x1UL << 4)
 
#define SMU_PPUPATD1_RMU_DEFAULT   (_SMU_PPUPATD1_RMU_DEFAULT << 4)
 
#define SMU_PPUPATD1_RTC   (0x1UL << 5)
 
#define SMU_PPUPATD1_RTC_DEFAULT   (_SMU_PPUPATD1_RTC_DEFAULT << 5)
 
#define SMU_PPUPATD1_RTCC   (0x1UL << 6)
 
#define SMU_PPUPATD1_RTCC_DEFAULT   (_SMU_PPUPATD1_RTCC_DEFAULT << 6)
 
#define SMU_PPUPATD1_SDIO   (0x1UL << 7)
 
#define SMU_PPUPATD1_SDIO_DEFAULT   (_SMU_PPUPATD1_SDIO_DEFAULT << 7)
 
#define SMU_PPUPATD1_SMU   (0x1UL << 8)
 
#define SMU_PPUPATD1_SMU_DEFAULT   (_SMU_PPUPATD1_SMU_DEFAULT << 8)
 
#define SMU_PPUPATD1_TIMER0   (0x1UL << 9)
 
#define SMU_PPUPATD1_TIMER0_DEFAULT   (_SMU_PPUPATD1_TIMER0_DEFAULT << 9)
 
#define SMU_PPUPATD1_TIMER1   (0x1UL << 10)
 
#define SMU_PPUPATD1_TIMER1_DEFAULT   (_SMU_PPUPATD1_TIMER1_DEFAULT << 10)
 
#define SMU_PPUPATD1_TIMER2   (0x1UL << 11)
 
#define SMU_PPUPATD1_TIMER2_DEFAULT   (_SMU_PPUPATD1_TIMER2_DEFAULT << 11)
 
#define SMU_PPUPATD1_TIMER3   (0x1UL << 12)
 
#define SMU_PPUPATD1_TIMER3_DEFAULT   (_SMU_PPUPATD1_TIMER3_DEFAULT << 12)
 
#define SMU_PPUPATD1_TIMER4   (0x1UL << 13)
 
#define SMU_PPUPATD1_TIMER4_DEFAULT   (_SMU_PPUPATD1_TIMER4_DEFAULT << 13)
 
#define SMU_PPUPATD1_TIMER5   (0x1UL << 14)
 
#define SMU_PPUPATD1_TIMER5_DEFAULT   (_SMU_PPUPATD1_TIMER5_DEFAULT << 14)
 
#define SMU_PPUPATD1_TIMER6   (0x1UL << 15)
 
#define SMU_PPUPATD1_TIMER6_DEFAULT   (_SMU_PPUPATD1_TIMER6_DEFAULT << 15)
 
#define SMU_PPUPATD1_TRNG0   (0x1UL << 16)
 
#define SMU_PPUPATD1_TRNG0_DEFAULT   (_SMU_PPUPATD1_TRNG0_DEFAULT << 16)
 
#define SMU_PPUPATD1_UART0   (0x1UL << 17)
 
#define SMU_PPUPATD1_UART0_DEFAULT   (_SMU_PPUPATD1_UART0_DEFAULT << 17)
 
#define SMU_PPUPATD1_UART1   (0x1UL << 18)
 
#define SMU_PPUPATD1_UART1_DEFAULT   (_SMU_PPUPATD1_UART1_DEFAULT << 18)
 
#define SMU_PPUPATD1_USART0   (0x1UL << 19)
 
#define SMU_PPUPATD1_USART0_DEFAULT   (_SMU_PPUPATD1_USART0_DEFAULT << 19)
 
#define SMU_PPUPATD1_USART1   (0x1UL << 20)
 
#define SMU_PPUPATD1_USART1_DEFAULT   (_SMU_PPUPATD1_USART1_DEFAULT << 20)
 
#define SMU_PPUPATD1_USART2   (0x1UL << 21)
 
#define SMU_PPUPATD1_USART2_DEFAULT   (_SMU_PPUPATD1_USART2_DEFAULT << 21)
 
#define SMU_PPUPATD1_USART3   (0x1UL << 22)
 
#define SMU_PPUPATD1_USART3_DEFAULT   (_SMU_PPUPATD1_USART3_DEFAULT << 22)
 
#define SMU_PPUPATD1_USART4   (0x1UL << 23)
 
#define SMU_PPUPATD1_USART4_DEFAULT   (_SMU_PPUPATD1_USART4_DEFAULT << 23)
 
#define SMU_PPUPATD1_USART5   (0x1UL << 24)
 
#define SMU_PPUPATD1_USART5_DEFAULT   (_SMU_PPUPATD1_USART5_DEFAULT << 24)
 
#define SMU_PPUPATD1_USB   (0x1UL << 25)
 
#define SMU_PPUPATD1_USB_DEFAULT   (_SMU_PPUPATD1_USB_DEFAULT << 25)
 
#define SMU_PPUPATD1_WDOG0   (0x1UL << 26)
 
#define SMU_PPUPATD1_WDOG0_DEFAULT   (_SMU_PPUPATD1_WDOG0_DEFAULT << 26)
 
#define SMU_PPUPATD1_WDOG1   (0x1UL << 27)
 
#define SMU_PPUPATD1_WDOG1_DEFAULT   (_SMU_PPUPATD1_WDOG1_DEFAULT << 27)
 
#define SMU_PPUPATD1_WTIMER0   (0x1UL << 28)
 
#define SMU_PPUPATD1_WTIMER0_DEFAULT   (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28)
 
#define SMU_PPUPATD1_WTIMER1   (0x1UL << 29)
 
#define SMU_PPUPATD1_WTIMER1_DEFAULT   (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29)
 
#define SMU_PPUPATD1_WTIMER2   (0x1UL << 30)
 
#define SMU_PPUPATD1_WTIMER2_DEFAULT   (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30)
 
#define SMU_PPUPATD1_WTIMER3   (0x1UL << 31)
 
#define SMU_PPUPATD1_WTIMER3_DEFAULT   (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31)
 

Macro Definition Documentation

#define _SMU_IEN_MASK   0x00000001UL

Mask for SMU_IEN

Definition at line 102 of file efm32gg11b_smu.h.

#define _SMU_IEN_PPUPRIV_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_IEN

Definition at line 106 of file efm32gg11b_smu.h.

#define _SMU_IEN_PPUPRIV_MASK   0x1UL

Bit mask for SMU_PPUPRIV

Definition at line 105 of file efm32gg11b_smu.h.

#define _SMU_IEN_PPUPRIV_SHIFT   0

Shift value for SMU_PPUPRIV

Definition at line 104 of file efm32gg11b_smu.h.

#define _SMU_IEN_RESETVALUE   0x00000000UL

Default value for SMU_IEN

Definition at line 101 of file efm32gg11b_smu.h.

#define _SMU_IF_MASK   0x00000001UL

Mask for SMU_IF

Definition at line 75 of file efm32gg11b_smu.h.

#define _SMU_IF_PPUPRIV_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_IF

Definition at line 79 of file efm32gg11b_smu.h.

#define _SMU_IF_PPUPRIV_MASK   0x1UL

Bit mask for SMU_PPUPRIV

Definition at line 78 of file efm32gg11b_smu.h.

#define _SMU_IF_PPUPRIV_SHIFT   0

Shift value for SMU_PPUPRIV

Definition at line 77 of file efm32gg11b_smu.h.

#define _SMU_IF_RESETVALUE   0x00000000UL

Default value for SMU_IF

Definition at line 74 of file efm32gg11b_smu.h.

#define _SMU_IFC_MASK   0x00000001UL

Mask for SMU_IFC

Definition at line 93 of file efm32gg11b_smu.h.

#define _SMU_IFC_PPUPRIV_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_IFC

Definition at line 97 of file efm32gg11b_smu.h.

#define _SMU_IFC_PPUPRIV_MASK   0x1UL

Bit mask for SMU_PPUPRIV

Definition at line 96 of file efm32gg11b_smu.h.

#define _SMU_IFC_PPUPRIV_SHIFT   0

Shift value for SMU_PPUPRIV

Definition at line 95 of file efm32gg11b_smu.h.

#define _SMU_IFC_RESETVALUE   0x00000000UL

Default value for SMU_IFC

Definition at line 92 of file efm32gg11b_smu.h.

#define _SMU_IFS_MASK   0x00000001UL

Mask for SMU_IFS

Definition at line 84 of file efm32gg11b_smu.h.

#define _SMU_IFS_PPUPRIV_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_IFS

Definition at line 88 of file efm32gg11b_smu.h.

#define _SMU_IFS_PPUPRIV_MASK   0x1UL

Bit mask for SMU_PPUPRIV

Definition at line 87 of file efm32gg11b_smu.h.

#define _SMU_IFS_PPUPRIV_SHIFT   0

Shift value for SMU_PPUPRIV

Definition at line 86 of file efm32gg11b_smu.h.

#define _SMU_IFS_RESETVALUE   0x00000000UL

Default value for SMU_IFS

Definition at line 83 of file efm32gg11b_smu.h.

#define _SMU_PPUCTRL_ENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUCTRL

Definition at line 115 of file efm32gg11b_smu.h.

#define _SMU_PPUCTRL_ENABLE_MASK   0x1UL

Bit mask for SMU_ENABLE

Definition at line 114 of file efm32gg11b_smu.h.

#define _SMU_PPUCTRL_ENABLE_SHIFT   0

Shift value for SMU_ENABLE

Definition at line 113 of file efm32gg11b_smu.h.

Referenced by SMU_EnablePPU().

#define _SMU_PPUCTRL_MASK   0x00000001UL

Mask for SMU_PPUCTRL

Definition at line 111 of file efm32gg11b_smu.h.

#define _SMU_PPUCTRL_RESETVALUE   0x00000000UL

Default value for SMU_PPUCTRL

Definition at line 110 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_MASK   0x0000007FUL

Mask for SMU_PPUFS

Definition at line 452 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ACMP0   0x00000000UL

Mode ACMP0 for SMU_PPUFS

Definition at line 456 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ACMP1   0x00000001UL

Mode ACMP1 for SMU_PPUFS

Definition at line 457 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ACMP2   0x00000002UL

Mode ACMP2 for SMU_PPUFS

Definition at line 458 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ACMP3   0x00000003UL

Mode ACMP3 for SMU_PPUFS

Definition at line 459 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ADC0   0x00000004UL

Mode ADC0 for SMU_PPUFS

Definition at line 460 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ADC1   0x00000005UL

Mode ADC1 for SMU_PPUFS

Definition at line 461 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CAN0   0x00000006UL

Mode CAN0 for SMU_PPUFS

Definition at line 462 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CAN1   0x00000007UL

Mode CAN1 for SMU_PPUFS

Definition at line 463 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CMU   0x00000008UL

Mode CMU for SMU_PPUFS

Definition at line 464 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CRYOTIMER   0x00000009UL

Mode CRYOTIMER for SMU_PPUFS

Definition at line 465 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CRYPTO0   0x0000000AUL

Mode CRYPTO0 for SMU_PPUFS

Definition at line 466 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_CSEN   0x0000000BUL

Mode CSEN for SMU_PPUFS

Definition at line 467 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUFS

Definition at line 455 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_EBI   0x0000000EUL

Mode EBI for SMU_PPUFS

Definition at line 470 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_EMU   0x0000000FUL

Mode EMU for SMU_PPUFS

Definition at line 471 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_ETH   0x00000010UL

Mode ETH for SMU_PPUFS

Definition at line 472 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_FPUEH   0x00000011UL

Mode FPUEH for SMU_PPUFS

Definition at line 473 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_GPCRC   0x00000012UL

Mode GPCRC for SMU_PPUFS

Definition at line 474 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_GPIO   0x00000013UL

Mode GPIO for SMU_PPUFS

Definition at line 475 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_I2C0   0x00000014UL

Mode I2C0 for SMU_PPUFS

Definition at line 476 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_I2C1   0x00000015UL

Mode I2C1 for SMU_PPUFS

Definition at line 477 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_I2C2   0x00000016UL

Mode I2C2 for SMU_PPUFS

Definition at line 478 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_IDAC0   0x00000017UL

Mode IDAC0 for SMU_PPUFS

Definition at line 479 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LCD   0x00000019UL

Mode LCD for SMU_PPUFS

Definition at line 481 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LDMA   0x0000001AUL

Mode LDMA for SMU_PPUFS

Definition at line 482 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LESENSE   0x0000001BUL

Mode LESENSE for SMU_PPUFS

Definition at line 483 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LETIMER0   0x0000001CUL

Mode LETIMER0 for SMU_PPUFS

Definition at line 484 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LETIMER1   0x0000001DUL

Mode LETIMER1 for SMU_PPUFS

Definition at line 485 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LEUART0   0x0000001EUL

Mode LEUART0 for SMU_PPUFS

Definition at line 486 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_LEUART1   0x0000001FUL

Mode LEUART1 for SMU_PPUFS

Definition at line 487 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_MASK   0x7FUL

Bit mask for SMU_PERIPHID

Definition at line 454 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_MSC   0x00000018UL

Mode MSC for SMU_PPUFS

Definition at line 480 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_PCNT0   0x00000020UL

Mode PCNT0 for SMU_PPUFS

Definition at line 488 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_PCNT1   0x00000021UL

Mode PCNT1 for SMU_PPUFS

Definition at line 489 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_PCNT2   0x00000022UL

Mode PCNT2 for SMU_PPUFS

Definition at line 490 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_PRS   0x0000000DUL

Mode PRS for SMU_PPUFS

Definition at line 469 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_QSPI0   0x00000023UL

Mode QSPI0 for SMU_PPUFS

Definition at line 491 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_RMU   0x00000024UL

Mode RMU for SMU_PPUFS

Definition at line 492 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_RTC   0x00000025UL

Mode RTC for SMU_PPUFS

Definition at line 493 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_RTCC   0x00000026UL

Mode RTCC for SMU_PPUFS

Definition at line 494 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_SDIO   0x00000027UL

Mode SDIO for SMU_PPUFS

Definition at line 495 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_SHIFT   0

Shift value for SMU_PERIPHID

Definition at line 453 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_SMU   0x00000028UL

Mode SMU for SMU_PPUFS

Definition at line 496 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER0   0x00000029UL

Mode TIMER0 for SMU_PPUFS

Definition at line 497 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER1   0x0000002AUL

Mode TIMER1 for SMU_PPUFS

Definition at line 498 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER2   0x0000002BUL

Mode TIMER2 for SMU_PPUFS

Definition at line 499 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER3   0x0000002CUL

Mode TIMER3 for SMU_PPUFS

Definition at line 500 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER4   0x0000002DUL

Mode TIMER4 for SMU_PPUFS

Definition at line 501 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER5   0x0000002EUL

Mode TIMER5 for SMU_PPUFS

Definition at line 502 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TIMER6   0x0000002FUL

Mode TIMER6 for SMU_PPUFS

Definition at line 503 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_TRNG0   0x00000030UL

Mode TRNG0 for SMU_PPUFS

Definition at line 504 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_UART0   0x00000031UL

Mode UART0 for SMU_PPUFS

Definition at line 505 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_UART1   0x00000032UL

Mode UART1 for SMU_PPUFS

Definition at line 506 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART0   0x00000033UL

Mode USART0 for SMU_PPUFS

Definition at line 507 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART1   0x00000034UL

Mode USART1 for SMU_PPUFS

Definition at line 508 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART2   0x00000035UL

Mode USART2 for SMU_PPUFS

Definition at line 509 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART3   0x00000036UL

Mode USART3 for SMU_PPUFS

Definition at line 510 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART4   0x00000037UL

Mode USART4 for SMU_PPUFS

Definition at line 511 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USART5   0x00000038UL

Mode USART5 for SMU_PPUFS

Definition at line 512 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_USB   0x00000039UL

Mode USB for SMU_PPUFS

Definition at line 513 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_VDAC0   0x0000000CUL

Mode VDAC0 for SMU_PPUFS

Definition at line 468 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WDOG0   0x0000003AUL

Mode WDOG0 for SMU_PPUFS

Definition at line 514 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WDOG1   0x0000003BUL

Mode WDOG1 for SMU_PPUFS

Definition at line 515 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WTIMER0   0x0000003CUL

Mode WTIMER0 for SMU_PPUFS

Definition at line 516 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WTIMER1   0x0000003DUL

Mode WTIMER1 for SMU_PPUFS

Definition at line 517 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WTIMER2   0x0000003EUL

Mode WTIMER2 for SMU_PPUFS

Definition at line 518 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_PERIPHID_WTIMER3   0x0000003FUL

Mode WTIMER3 for SMU_PPUFS

Definition at line 519 of file efm32gg11b_smu.h.

#define _SMU_PPUFS_RESETVALUE   0x00000000UL

Default value for SMU_PPUFS

Definition at line 451 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 124 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP0_MASK   0x1UL

Bit mask for SMU_ACMP0

Definition at line 123 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP0_SHIFT   0

Shift value for SMU_ACMP0

Definition at line 122 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 129 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP1_MASK   0x2UL

Bit mask for SMU_ACMP1

Definition at line 128 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP1_SHIFT   1

Shift value for SMU_ACMP1

Definition at line 127 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 134 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP2_MASK   0x4UL

Bit mask for SMU_ACMP2

Definition at line 133 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP2_SHIFT   2

Shift value for SMU_ACMP2

Definition at line 132 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP3_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 139 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP3_MASK   0x8UL

Bit mask for SMU_ACMP3

Definition at line 138 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ACMP3_SHIFT   3

Shift value for SMU_ACMP3

Definition at line 137 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 144 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC0_MASK   0x10UL

Bit mask for SMU_ADC0

Definition at line 143 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC0_SHIFT   4

Shift value for SMU_ADC0

Definition at line 142 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 149 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC1_MASK   0x20UL

Bit mask for SMU_ADC1

Definition at line 148 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ADC1_SHIFT   5

Shift value for SMU_ADC1

Definition at line 147 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 154 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN0_MASK   0x40UL

Bit mask for SMU_CAN0

Definition at line 153 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN0_SHIFT   6

Shift value for SMU_CAN0

Definition at line 152 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 159 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN1_MASK   0x80UL

Bit mask for SMU_CAN1

Definition at line 158 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CAN1_SHIFT   7

Shift value for SMU_CAN1

Definition at line 157 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CMU_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 164 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CMU_MASK   0x100UL

Bit mask for SMU_CMU

Definition at line 163 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CMU_SHIFT   8

Shift value for SMU_CMU

Definition at line 162 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYOTIMER_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 169 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYOTIMER_MASK   0x200UL

Bit mask for SMU_CRYOTIMER

Definition at line 168 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYOTIMER_SHIFT   9

Shift value for SMU_CRYOTIMER

Definition at line 167 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYPTO0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 174 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYPTO0_MASK   0x400UL

Bit mask for SMU_CRYPTO0

Definition at line 173 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CRYPTO0_SHIFT   10

Shift value for SMU_CRYPTO0

Definition at line 172 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CSEN_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 179 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CSEN_MASK   0x800UL

Bit mask for SMU_CSEN

Definition at line 178 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_CSEN_SHIFT   11

Shift value for SMU_CSEN

Definition at line 177 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EBI_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 194 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EBI_MASK   0x4000UL

Bit mask for SMU_EBI

Definition at line 193 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EBI_SHIFT   14

Shift value for SMU_EBI

Definition at line 192 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EMU_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 199 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EMU_MASK   0x8000UL

Bit mask for SMU_EMU

Definition at line 198 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_EMU_SHIFT   15

Shift value for SMU_EMU

Definition at line 197 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ETH_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 204 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ETH_MASK   0x10000UL

Bit mask for SMU_ETH

Definition at line 203 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_ETH_SHIFT   16

Shift value for SMU_ETH

Definition at line 202 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_FPUEH_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 209 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_FPUEH_MASK   0x20000UL

Bit mask for SMU_FPUEH

Definition at line 208 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_FPUEH_SHIFT   17

Shift value for SMU_FPUEH

Definition at line 207 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPCRC_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 214 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPCRC_MASK   0x40000UL

Bit mask for SMU_GPCRC

Definition at line 213 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPCRC_SHIFT   18

Shift value for SMU_GPCRC

Definition at line 212 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPIO_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 219 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPIO_MASK   0x80000UL

Bit mask for SMU_GPIO

Definition at line 218 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_GPIO_SHIFT   19

Shift value for SMU_GPIO

Definition at line 217 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 224 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C0_MASK   0x100000UL

Bit mask for SMU_I2C0

Definition at line 223 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C0_SHIFT   20

Shift value for SMU_I2C0

Definition at line 222 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 229 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C1_MASK   0x200000UL

Bit mask for SMU_I2C1

Definition at line 228 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C1_SHIFT   21

Shift value for SMU_I2C1

Definition at line 227 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 234 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C2_MASK   0x400000UL

Bit mask for SMU_I2C2

Definition at line 233 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_I2C2_SHIFT   22

Shift value for SMU_I2C2

Definition at line 232 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_IDAC0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 239 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_IDAC0_MASK   0x800000UL

Bit mask for SMU_IDAC0

Definition at line 238 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_IDAC0_SHIFT   23

Shift value for SMU_IDAC0

Definition at line 237 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LCD_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 249 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LCD_MASK   0x2000000UL

Bit mask for SMU_LCD

Definition at line 248 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LCD_SHIFT   25

Shift value for SMU_LCD

Definition at line 247 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LDMA_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 254 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LDMA_MASK   0x4000000UL

Bit mask for SMU_LDMA

Definition at line 253 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LDMA_SHIFT   26

Shift value for SMU_LDMA

Definition at line 252 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LESENSE_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 259 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LESENSE_MASK   0x8000000UL

Bit mask for SMU_LESENSE

Definition at line 258 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LESENSE_SHIFT   27

Shift value for SMU_LESENSE

Definition at line 257 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 264 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER0_MASK   0x10000000UL

Bit mask for SMU_LETIMER0

Definition at line 263 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER0_SHIFT   28

Shift value for SMU_LETIMER0

Definition at line 262 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 269 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER1_MASK   0x20000000UL

Bit mask for SMU_LETIMER1

Definition at line 268 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LETIMER1_SHIFT   29

Shift value for SMU_LETIMER1

Definition at line 267 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 274 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART0_MASK   0x40000000UL

Bit mask for SMU_LEUART0

Definition at line 273 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART0_SHIFT   30

Shift value for SMU_LEUART0

Definition at line 272 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 279 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART1_MASK   0x80000000UL

Bit mask for SMU_LEUART1

Definition at line 278 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_LEUART1_SHIFT   31

Shift value for SMU_LEUART1

Definition at line 277 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_MASK   0xFFFFFFFFUL

Mask for SMU_PPUPATD0

Definition at line 120 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_MSC_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 244 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_MSC_MASK   0x1000000UL

Bit mask for SMU_MSC

Definition at line 243 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_MSC_SHIFT   24

Shift value for SMU_MSC

Definition at line 242 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_PRS_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 189 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_PRS_MASK   0x2000UL

Bit mask for SMU_PRS

Definition at line 188 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_PRS_SHIFT   13

Shift value for SMU_PRS

Definition at line 187 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_RESETVALUE   0x00000000UL

Default value for SMU_PPUPATD0

Definition at line 119 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_VDAC0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD0

Definition at line 184 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_VDAC0_MASK   0x1000UL

Bit mask for SMU_VDAC0

Definition at line 183 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD0_VDAC0_SHIFT   12

Shift value for SMU_VDAC0

Definition at line 182 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_MASK   0xFFFFFFFFUL

Mask for SMU_PPUPATD1

Definition at line 284 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 288 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT0_MASK   0x1UL

Bit mask for SMU_PCNT0

Definition at line 287 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT0_SHIFT   0

Shift value for SMU_PCNT0

Definition at line 286 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 293 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT1_MASK   0x2UL

Bit mask for SMU_PCNT1

Definition at line 292 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT1_SHIFT   1

Shift value for SMU_PCNT1

Definition at line 291 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 298 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT2_MASK   0x4UL

Bit mask for SMU_PCNT2

Definition at line 297 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_PCNT2_SHIFT   2

Shift value for SMU_PCNT2

Definition at line 296 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_QSPI0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 303 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_QSPI0_MASK   0x8UL

Bit mask for SMU_QSPI0

Definition at line 302 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_QSPI0_SHIFT   3

Shift value for SMU_QSPI0

Definition at line 301 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RESETVALUE   0x00000000UL

Default value for SMU_PPUPATD1

Definition at line 283 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RMU_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 308 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RMU_MASK   0x10UL

Bit mask for SMU_RMU

Definition at line 307 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RMU_SHIFT   4

Shift value for SMU_RMU

Definition at line 306 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTC_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 313 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTC_MASK   0x20UL

Bit mask for SMU_RTC

Definition at line 312 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTC_SHIFT   5

Shift value for SMU_RTC

Definition at line 311 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTCC_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 318 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTCC_MASK   0x40UL

Bit mask for SMU_RTCC

Definition at line 317 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_RTCC_SHIFT   6

Shift value for SMU_RTCC

Definition at line 316 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SDIO_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 323 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SDIO_MASK   0x80UL

Bit mask for SMU_SDIO

Definition at line 322 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SDIO_SHIFT   7

Shift value for SMU_SDIO

Definition at line 321 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SMU_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 328 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SMU_MASK   0x100UL

Bit mask for SMU_SMU

Definition at line 327 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_SMU_SHIFT   8

Shift value for SMU_SMU

Definition at line 326 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 333 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER0_MASK   0x200UL

Bit mask for SMU_TIMER0

Definition at line 332 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER0_SHIFT   9

Shift value for SMU_TIMER0

Definition at line 331 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 338 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER1_MASK   0x400UL

Bit mask for SMU_TIMER1

Definition at line 337 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER1_SHIFT   10

Shift value for SMU_TIMER1

Definition at line 336 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 343 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER2_MASK   0x800UL

Bit mask for SMU_TIMER2

Definition at line 342 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER2_SHIFT   11

Shift value for SMU_TIMER2

Definition at line 341 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER3_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 348 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER3_MASK   0x1000UL

Bit mask for SMU_TIMER3

Definition at line 347 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER3_SHIFT   12

Shift value for SMU_TIMER3

Definition at line 346 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER4_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 353 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER4_MASK   0x2000UL

Bit mask for SMU_TIMER4

Definition at line 352 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER4_SHIFT   13

Shift value for SMU_TIMER4

Definition at line 351 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER5_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 358 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER5_MASK   0x4000UL

Bit mask for SMU_TIMER5

Definition at line 357 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER5_SHIFT   14

Shift value for SMU_TIMER5

Definition at line 356 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER6_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 363 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER6_MASK   0x8000UL

Bit mask for SMU_TIMER6

Definition at line 362 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TIMER6_SHIFT   15

Shift value for SMU_TIMER6

Definition at line 361 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TRNG0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 368 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TRNG0_MASK   0x10000UL

Bit mask for SMU_TRNG0

Definition at line 367 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_TRNG0_SHIFT   16

Shift value for SMU_TRNG0

Definition at line 366 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 373 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART0_MASK   0x20000UL

Bit mask for SMU_UART0

Definition at line 372 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART0_SHIFT   17

Shift value for SMU_UART0

Definition at line 371 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 378 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART1_MASK   0x40000UL

Bit mask for SMU_UART1

Definition at line 377 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_UART1_SHIFT   18

Shift value for SMU_UART1

Definition at line 376 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 383 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART0_MASK   0x80000UL

Bit mask for SMU_USART0

Definition at line 382 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART0_SHIFT   19

Shift value for SMU_USART0

Definition at line 381 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 388 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART1_MASK   0x100000UL

Bit mask for SMU_USART1

Definition at line 387 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART1_SHIFT   20

Shift value for SMU_USART1

Definition at line 386 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 393 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART2_MASK   0x200000UL

Bit mask for SMU_USART2

Definition at line 392 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART2_SHIFT   21

Shift value for SMU_USART2

Definition at line 391 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART3_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 398 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART3_MASK   0x400000UL

Bit mask for SMU_USART3

Definition at line 397 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART3_SHIFT   22

Shift value for SMU_USART3

Definition at line 396 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART4_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 403 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART4_MASK   0x800000UL

Bit mask for SMU_USART4

Definition at line 402 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART4_SHIFT   23

Shift value for SMU_USART4

Definition at line 401 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART5_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 408 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART5_MASK   0x1000000UL

Bit mask for SMU_USART5

Definition at line 407 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USART5_SHIFT   24

Shift value for SMU_USART5

Definition at line 406 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USB_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 413 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USB_MASK   0x2000000UL

Bit mask for SMU_USB

Definition at line 412 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_USB_SHIFT   25

Shift value for SMU_USB

Definition at line 411 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 418 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG0_MASK   0x4000000UL

Bit mask for SMU_WDOG0

Definition at line 417 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG0_SHIFT   26

Shift value for SMU_WDOG0

Definition at line 416 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 423 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG1_MASK   0x8000000UL

Bit mask for SMU_WDOG1

Definition at line 422 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WDOG1_SHIFT   27

Shift value for SMU_WDOG1

Definition at line 421 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER0_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 428 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER0_MASK   0x10000000UL

Bit mask for SMU_WTIMER0

Definition at line 427 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER0_SHIFT   28

Shift value for SMU_WTIMER0

Definition at line 426 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER1_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 433 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER1_MASK   0x20000000UL

Bit mask for SMU_WTIMER1

Definition at line 432 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER1_SHIFT   29

Shift value for SMU_WTIMER1

Definition at line 431 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER2_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 438 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER2_MASK   0x40000000UL

Bit mask for SMU_WTIMER2

Definition at line 437 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER2_SHIFT   30

Shift value for SMU_WTIMER2

Definition at line 436 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER3_DEFAULT   0x00000000UL

Mode DEFAULT for SMU_PPUPATD1

Definition at line 443 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER3_MASK   0x80000000UL

Bit mask for SMU_WTIMER3

Definition at line 442 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD1_WTIMER3_SHIFT   31

Shift value for SMU_WTIMER3

Definition at line 441 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD2_MASK   0x00000000UL

Mask for SMU_PPUPATD2

Definition at line 448 of file efm32gg11b_smu.h.

#define _SMU_PPUPATD2_RESETVALUE   0x00000000UL

Default value for SMU_PPUPATD2

Definition at line 447 of file efm32gg11b_smu.h.

#define SMU_IEN_PPUPRIV   (0x1UL << 0)

PPUPRIV Interrupt Enable

Definition at line 103 of file efm32gg11b_smu.h.

#define SMU_IEN_PPUPRIV_DEFAULT   (_SMU_IEN_PPUPRIV_DEFAULT << 0)

Shifted mode DEFAULT for SMU_IEN

Definition at line 107 of file efm32gg11b_smu.h.

#define SMU_IF_PPUPRIV   (0x1UL << 0)

PPU Privilege Interrupt Flag

Definition at line 76 of file efm32gg11b_smu.h.

#define SMU_IF_PPUPRIV_DEFAULT   (_SMU_IF_PPUPRIV_DEFAULT << 0)

Shifted mode DEFAULT for SMU_IF

Definition at line 80 of file efm32gg11b_smu.h.

#define SMU_IFC_PPUPRIV   (0x1UL << 0)

Clear PPUPRIV Interrupt Flag

Definition at line 94 of file efm32gg11b_smu.h.

#define SMU_IFC_PPUPRIV_DEFAULT   (_SMU_IFC_PPUPRIV_DEFAULT << 0)

Shifted mode DEFAULT for SMU_IFC

Definition at line 98 of file efm32gg11b_smu.h.

#define SMU_IFS_PPUPRIV   (0x1UL << 0)

Set PPUPRIV Interrupt Flag

Definition at line 85 of file efm32gg11b_smu.h.

#define SMU_IFS_PPUPRIV_DEFAULT   (_SMU_IFS_PPUPRIV_DEFAULT << 0)

Shifted mode DEFAULT for SMU_IFS

Definition at line 89 of file efm32gg11b_smu.h.

#define SMU_PPUCTRL_ENABLE_DEFAULT   (_SMU_PPUCTRL_ENABLE_DEFAULT << 0)

Shifted mode DEFAULT for SMU_PPUCTRL

Definition at line 116 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ACMP0   (_SMU_PPUFS_PERIPHID_ACMP0 << 0)

Shifted mode ACMP0 for SMU_PPUFS

Definition at line 521 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ACMP1   (_SMU_PPUFS_PERIPHID_ACMP1 << 0)

Shifted mode ACMP1 for SMU_PPUFS

Definition at line 522 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ACMP2   (_SMU_PPUFS_PERIPHID_ACMP2 << 0)

Shifted mode ACMP2 for SMU_PPUFS

Definition at line 523 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ACMP3   (_SMU_PPUFS_PERIPHID_ACMP3 << 0)

Shifted mode ACMP3 for SMU_PPUFS

Definition at line 524 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ADC0   (_SMU_PPUFS_PERIPHID_ADC0 << 0)

Shifted mode ADC0 for SMU_PPUFS

Definition at line 525 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ADC1   (_SMU_PPUFS_PERIPHID_ADC1 << 0)

Shifted mode ADC1 for SMU_PPUFS

Definition at line 526 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CAN0   (_SMU_PPUFS_PERIPHID_CAN0 << 0)

Shifted mode CAN0 for SMU_PPUFS

Definition at line 527 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CAN1   (_SMU_PPUFS_PERIPHID_CAN1 << 0)

Shifted mode CAN1 for SMU_PPUFS

Definition at line 528 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CMU   (_SMU_PPUFS_PERIPHID_CMU << 0)

Shifted mode CMU for SMU_PPUFS

Definition at line 529 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CRYOTIMER   (_SMU_PPUFS_PERIPHID_CRYOTIMER << 0)

Shifted mode CRYOTIMER for SMU_PPUFS

Definition at line 530 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CRYPTO0   (_SMU_PPUFS_PERIPHID_CRYPTO0 << 0)

Shifted mode CRYPTO0 for SMU_PPUFS

Definition at line 531 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_CSEN   (_SMU_PPUFS_PERIPHID_CSEN << 0)

Shifted mode CSEN for SMU_PPUFS

Definition at line 532 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_DEFAULT   (_SMU_PPUFS_PERIPHID_DEFAULT << 0)

Shifted mode DEFAULT for SMU_PPUFS

Definition at line 520 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_EBI   (_SMU_PPUFS_PERIPHID_EBI << 0)

Shifted mode EBI for SMU_PPUFS

Definition at line 535 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_EMU   (_SMU_PPUFS_PERIPHID_EMU << 0)

Shifted mode EMU for SMU_PPUFS

Definition at line 536 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_ETH   (_SMU_PPUFS_PERIPHID_ETH << 0)

Shifted mode ETH for SMU_PPUFS

Definition at line 537 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_FPUEH   (_SMU_PPUFS_PERIPHID_FPUEH << 0)

Shifted mode FPUEH for SMU_PPUFS

Definition at line 538 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_GPCRC   (_SMU_PPUFS_PERIPHID_GPCRC << 0)

Shifted mode GPCRC for SMU_PPUFS

Definition at line 539 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_GPIO   (_SMU_PPUFS_PERIPHID_GPIO << 0)

Shifted mode GPIO for SMU_PPUFS

Definition at line 540 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_I2C0   (_SMU_PPUFS_PERIPHID_I2C0 << 0)

Shifted mode I2C0 for SMU_PPUFS

Definition at line 541 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_I2C1   (_SMU_PPUFS_PERIPHID_I2C1 << 0)

Shifted mode I2C1 for SMU_PPUFS

Definition at line 542 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_I2C2   (_SMU_PPUFS_PERIPHID_I2C2 << 0)

Shifted mode I2C2 for SMU_PPUFS

Definition at line 543 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_IDAC0   (_SMU_PPUFS_PERIPHID_IDAC0 << 0)

Shifted mode IDAC0 for SMU_PPUFS

Definition at line 544 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LCD   (_SMU_PPUFS_PERIPHID_LCD << 0)

Shifted mode LCD for SMU_PPUFS

Definition at line 546 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LDMA   (_SMU_PPUFS_PERIPHID_LDMA << 0)

Shifted mode LDMA for SMU_PPUFS

Definition at line 547 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LESENSE   (_SMU_PPUFS_PERIPHID_LESENSE << 0)

Shifted mode LESENSE for SMU_PPUFS

Definition at line 548 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LETIMER0   (_SMU_PPUFS_PERIPHID_LETIMER0 << 0)

Shifted mode LETIMER0 for SMU_PPUFS

Definition at line 549 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LETIMER1   (_SMU_PPUFS_PERIPHID_LETIMER1 << 0)

Shifted mode LETIMER1 for SMU_PPUFS

Definition at line 550 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LEUART0   (_SMU_PPUFS_PERIPHID_LEUART0 << 0)

Shifted mode LEUART0 for SMU_PPUFS

Definition at line 551 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_LEUART1   (_SMU_PPUFS_PERIPHID_LEUART1 << 0)

Shifted mode LEUART1 for SMU_PPUFS

Definition at line 552 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_MSC   (_SMU_PPUFS_PERIPHID_MSC << 0)

Shifted mode MSC for SMU_PPUFS

Definition at line 545 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_PCNT0   (_SMU_PPUFS_PERIPHID_PCNT0 << 0)

Shifted mode PCNT0 for SMU_PPUFS

Definition at line 553 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_PCNT1   (_SMU_PPUFS_PERIPHID_PCNT1 << 0)

Shifted mode PCNT1 for SMU_PPUFS

Definition at line 554 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_PCNT2   (_SMU_PPUFS_PERIPHID_PCNT2 << 0)

Shifted mode PCNT2 for SMU_PPUFS

Definition at line 555 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_PRS   (_SMU_PPUFS_PERIPHID_PRS << 0)

Shifted mode PRS for SMU_PPUFS

Definition at line 534 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_QSPI0   (_SMU_PPUFS_PERIPHID_QSPI0 << 0)

Shifted mode QSPI0 for SMU_PPUFS

Definition at line 556 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_RMU   (_SMU_PPUFS_PERIPHID_RMU << 0)

Shifted mode RMU for SMU_PPUFS

Definition at line 557 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_RTC   (_SMU_PPUFS_PERIPHID_RTC << 0)

Shifted mode RTC for SMU_PPUFS

Definition at line 558 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_RTCC   (_SMU_PPUFS_PERIPHID_RTCC << 0)

Shifted mode RTCC for SMU_PPUFS

Definition at line 559 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_SDIO   (_SMU_PPUFS_PERIPHID_SDIO << 0)

Shifted mode SDIO for SMU_PPUFS

Definition at line 560 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_SMU   (_SMU_PPUFS_PERIPHID_SMU << 0)

Shifted mode SMU for SMU_PPUFS

Definition at line 561 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER0   (_SMU_PPUFS_PERIPHID_TIMER0 << 0)

Shifted mode TIMER0 for SMU_PPUFS

Definition at line 562 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER1   (_SMU_PPUFS_PERIPHID_TIMER1 << 0)

Shifted mode TIMER1 for SMU_PPUFS

Definition at line 563 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER2   (_SMU_PPUFS_PERIPHID_TIMER2 << 0)

Shifted mode TIMER2 for SMU_PPUFS

Definition at line 564 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER3   (_SMU_PPUFS_PERIPHID_TIMER3 << 0)

Shifted mode TIMER3 for SMU_PPUFS

Definition at line 565 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER4   (_SMU_PPUFS_PERIPHID_TIMER4 << 0)

Shifted mode TIMER4 for SMU_PPUFS

Definition at line 566 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER5   (_SMU_PPUFS_PERIPHID_TIMER5 << 0)

Shifted mode TIMER5 for SMU_PPUFS

Definition at line 567 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TIMER6   (_SMU_PPUFS_PERIPHID_TIMER6 << 0)

Shifted mode TIMER6 for SMU_PPUFS

Definition at line 568 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_TRNG0   (_SMU_PPUFS_PERIPHID_TRNG0 << 0)

Shifted mode TRNG0 for SMU_PPUFS

Definition at line 569 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_UART0   (_SMU_PPUFS_PERIPHID_UART0 << 0)

Shifted mode UART0 for SMU_PPUFS

Definition at line 570 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_UART1   (_SMU_PPUFS_PERIPHID_UART1 << 0)

Shifted mode UART1 for SMU_PPUFS

Definition at line 571 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART0   (_SMU_PPUFS_PERIPHID_USART0 << 0)

Shifted mode USART0 for SMU_PPUFS

Definition at line 572 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART1   (_SMU_PPUFS_PERIPHID_USART1 << 0)

Shifted mode USART1 for SMU_PPUFS

Definition at line 573 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART2   (_SMU_PPUFS_PERIPHID_USART2 << 0)

Shifted mode USART2 for SMU_PPUFS

Definition at line 574 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART3   (_SMU_PPUFS_PERIPHID_USART3 << 0)

Shifted mode USART3 for SMU_PPUFS

Definition at line 575 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART4   (_SMU_PPUFS_PERIPHID_USART4 << 0)

Shifted mode USART4 for SMU_PPUFS

Definition at line 576 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USART5   (_SMU_PPUFS_PERIPHID_USART5 << 0)

Shifted mode USART5 for SMU_PPUFS

Definition at line 577 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_USB   (_SMU_PPUFS_PERIPHID_USB << 0)

Shifted mode USB for SMU_PPUFS

Definition at line 578 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_VDAC0   (_SMU_PPUFS_PERIPHID_VDAC0 << 0)

Shifted mode VDAC0 for SMU_PPUFS

Definition at line 533 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WDOG0   (_SMU_PPUFS_PERIPHID_WDOG0 << 0)

Shifted mode WDOG0 for SMU_PPUFS

Definition at line 579 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WDOG1   (_SMU_PPUFS_PERIPHID_WDOG1 << 0)

Shifted mode WDOG1 for SMU_PPUFS

Definition at line 580 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WTIMER0   (_SMU_PPUFS_PERIPHID_WTIMER0 << 0)

Shifted mode WTIMER0 for SMU_PPUFS

Definition at line 581 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WTIMER1   (_SMU_PPUFS_PERIPHID_WTIMER1 << 0)

Shifted mode WTIMER1 for SMU_PPUFS

Definition at line 582 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WTIMER2   (_SMU_PPUFS_PERIPHID_WTIMER2 << 0)

Shifted mode WTIMER2 for SMU_PPUFS

Definition at line 583 of file efm32gg11b_smu.h.

#define SMU_PPUFS_PERIPHID_WTIMER3   (_SMU_PPUFS_PERIPHID_WTIMER3 << 0)

Shifted mode WTIMER3 for SMU_PPUFS

Definition at line 584 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP0   (0x1UL << 0)

Analog Comparator 0 access control bit

Definition at line 121 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP0_DEFAULT   (_SMU_PPUPATD0_ACMP0_DEFAULT << 0)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 125 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP1   (0x1UL << 1)

Analog Comparator 1 access control bit

Definition at line 126 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP1_DEFAULT   (_SMU_PPUPATD0_ACMP1_DEFAULT << 1)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 130 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP2   (0x1UL << 2)

Analog Comparator 1 access control bit

Definition at line 131 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP2_DEFAULT   (_SMU_PPUPATD0_ACMP2_DEFAULT << 2)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 135 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP3   (0x1UL << 3)

Analog Comparator 3 access control bit

Definition at line 136 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ACMP3_DEFAULT   (_SMU_PPUPATD0_ACMP3_DEFAULT << 3)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 140 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ADC0   (0x1UL << 4)

Analog to Digital Converter 0 access control bit

Definition at line 141 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ADC0_DEFAULT   (_SMU_PPUPATD0_ADC0_DEFAULT << 4)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 145 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ADC1   (0x1UL << 5)

Analog to Digital Converter 0 access control bit

Definition at line 146 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ADC1_DEFAULT   (_SMU_PPUPATD0_ADC1_DEFAULT << 5)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 150 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CAN0   (0x1UL << 6)

CAN 0 access control bit

Definition at line 151 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CAN0_DEFAULT   (_SMU_PPUPATD0_CAN0_DEFAULT << 6)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 155 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CAN1   (0x1UL << 7)

CAN 1 access control bit

Definition at line 156 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CAN1_DEFAULT   (_SMU_PPUPATD0_CAN1_DEFAULT << 7)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 160 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CMU   (0x1UL << 8)

Clock Management Unit access control bit

Definition at line 161 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CMU_DEFAULT   (_SMU_PPUPATD0_CMU_DEFAULT << 8)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 165 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CRYOTIMER   (0x1UL << 9)

CRYOTIMER access control bit

Definition at line 166 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CRYOTIMER_DEFAULT   (_SMU_PPUPATD0_CRYOTIMER_DEFAULT << 9)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 170 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CRYPTO0   (0x1UL << 10)

Advanced Encryption Standard Accelerator access control bit

Definition at line 171 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CRYPTO0_DEFAULT   (_SMU_PPUPATD0_CRYPTO0_DEFAULT << 10)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 175 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CSEN   (0x1UL << 11)

Capacitive touch sense module access control bit

Definition at line 176 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_CSEN_DEFAULT   (_SMU_PPUPATD0_CSEN_DEFAULT << 11)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 180 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_EBI   (0x1UL << 14)

External Bus Interface access control bit

Definition at line 191 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_EBI_DEFAULT   (_SMU_PPUPATD0_EBI_DEFAULT << 14)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 195 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_EMU   (0x1UL << 15)

Energy Management Unit access control bit

Definition at line 196 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_EMU_DEFAULT   (_SMU_PPUPATD0_EMU_DEFAULT << 15)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 200 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ETH   (0x1UL << 16)

Ethernet Controller access control bit

Definition at line 201 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_ETH_DEFAULT   (_SMU_PPUPATD0_ETH_DEFAULT << 16)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 205 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_FPUEH   (0x1UL << 17)

FPU Exception Handler access control bit

Definition at line 206 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_FPUEH_DEFAULT   (_SMU_PPUPATD0_FPUEH_DEFAULT << 17)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 210 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_GPCRC   (0x1UL << 18)

General Purpose CRC access control bit

Definition at line 211 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_GPCRC_DEFAULT   (_SMU_PPUPATD0_GPCRC_DEFAULT << 18)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 215 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_GPIO   (0x1UL << 19)

General purpose Input/Output access control bit

Definition at line 216 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_GPIO_DEFAULT   (_SMU_PPUPATD0_GPIO_DEFAULT << 19)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 220 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C0   (0x1UL << 20)

I2C 0 access control bit

Definition at line 221 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C0_DEFAULT   (_SMU_PPUPATD0_I2C0_DEFAULT << 20)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 225 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C1   (0x1UL << 21)

I2C 1 access control bit

Definition at line 226 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C1_DEFAULT   (_SMU_PPUPATD0_I2C1_DEFAULT << 21)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 230 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C2   (0x1UL << 22)

I2C 2 access control bit

Definition at line 231 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_I2C2_DEFAULT   (_SMU_PPUPATD0_I2C2_DEFAULT << 22)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 235 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_IDAC0   (0x1UL << 23)

Current Digital to Analog Converter 0 access control bit

Definition at line 236 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_IDAC0_DEFAULT   (_SMU_PPUPATD0_IDAC0_DEFAULT << 23)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 240 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LCD   (0x1UL << 25)

Liquid Crystal Display Controller access control bit

Definition at line 246 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LCD_DEFAULT   (_SMU_PPUPATD0_LCD_DEFAULT << 25)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 250 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LDMA   (0x1UL << 26)

Linked Direct Memory Access Controller access control bit

Definition at line 251 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LDMA_DEFAULT   (_SMU_PPUPATD0_LDMA_DEFAULT << 26)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 255 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LESENSE   (0x1UL << 27)

Low Energy Sensor Interface access control bit

Definition at line 256 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LESENSE_DEFAULT   (_SMU_PPUPATD0_LESENSE_DEFAULT << 27)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 260 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LETIMER0   (0x1UL << 28)

Low Energy Timer 0 access control bit

Definition at line 261 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LETIMER0_DEFAULT   (_SMU_PPUPATD0_LETIMER0_DEFAULT << 28)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 265 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LETIMER1   (0x1UL << 29)

Low Energy Timer 1 access control bit

Definition at line 266 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LETIMER1_DEFAULT   (_SMU_PPUPATD0_LETIMER1_DEFAULT << 29)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 270 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LEUART0   (0x1UL << 30)

Low Energy UART 0 access control bit

Definition at line 271 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LEUART0_DEFAULT   (_SMU_PPUPATD0_LEUART0_DEFAULT << 30)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 275 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LEUART1   (0x1UL << 31)

Low Energy UART 1 access control bit

Definition at line 276 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_LEUART1_DEFAULT   (_SMU_PPUPATD0_LEUART1_DEFAULT << 31)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 280 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_MSC   (0x1UL << 24)

Memory System Controller access control bit

Definition at line 241 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_MSC_DEFAULT   (_SMU_PPUPATD0_MSC_DEFAULT << 24)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 245 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_PRS   (0x1UL << 13)

Peripheral Reflex System access control bit

Definition at line 186 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_PRS_DEFAULT   (_SMU_PPUPATD0_PRS_DEFAULT << 13)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 190 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_VDAC0   (0x1UL << 12)

Digital to Analog Converter 0 access control bit

Definition at line 181 of file efm32gg11b_smu.h.

#define SMU_PPUPATD0_VDAC0_DEFAULT   (_SMU_PPUPATD0_VDAC0_DEFAULT << 12)

Shifted mode DEFAULT for SMU_PPUPATD0

Definition at line 185 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT0   (0x1UL << 0)

Pulse Counter 0 access control bit

Definition at line 285 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT0_DEFAULT   (_SMU_PPUPATD1_PCNT0_DEFAULT << 0)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 289 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT1   (0x1UL << 1)

Pulse Counter 1 access control bit

Definition at line 290 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT1_DEFAULT   (_SMU_PPUPATD1_PCNT1_DEFAULT << 1)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 294 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT2   (0x1UL << 2)

Pulse Counter 2 access control bit

Definition at line 295 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_PCNT2_DEFAULT   (_SMU_PPUPATD1_PCNT2_DEFAULT << 2)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 299 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_QSPI0   (0x1UL << 3)

Quad-SPI access control bit

Definition at line 300 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_QSPI0_DEFAULT   (_SMU_PPUPATD1_QSPI0_DEFAULT << 3)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 304 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RMU   (0x1UL << 4)

Reset Management Unit access control bit

Definition at line 305 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RMU_DEFAULT   (_SMU_PPUPATD1_RMU_DEFAULT << 4)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 309 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RTC   (0x1UL << 5)

Real-Time Counter access control bit

Definition at line 310 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RTC_DEFAULT   (_SMU_PPUPATD1_RTC_DEFAULT << 5)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 314 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RTCC   (0x1UL << 6)

Real-Time Counter and Calendar access control bit

Definition at line 315 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_RTCC_DEFAULT   (_SMU_PPUPATD1_RTCC_DEFAULT << 6)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 319 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_SDIO   (0x1UL << 7)

SDIO Controller access control bit

Definition at line 320 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_SDIO_DEFAULT   (_SMU_PPUPATD1_SDIO_DEFAULT << 7)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 324 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_SMU   (0x1UL << 8)

Security Management Unit access control bit

Definition at line 325 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_SMU_DEFAULT   (_SMU_PPUPATD1_SMU_DEFAULT << 8)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 329 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER0   (0x1UL << 9)

Timer 0 access control bit

Definition at line 330 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER0_DEFAULT   (_SMU_PPUPATD1_TIMER0_DEFAULT << 9)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 334 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER1   (0x1UL << 10)

Timer 1 access control bit

Definition at line 335 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER1_DEFAULT   (_SMU_PPUPATD1_TIMER1_DEFAULT << 10)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 339 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER2   (0x1UL << 11)

Timer 2 access control bit

Definition at line 340 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER2_DEFAULT   (_SMU_PPUPATD1_TIMER2_DEFAULT << 11)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 344 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER3   (0x1UL << 12)

Timer 3 access control bit

Definition at line 345 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER3_DEFAULT   (_SMU_PPUPATD1_TIMER3_DEFAULT << 12)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 349 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER4   (0x1UL << 13)

Timer 4 access control bit

Definition at line 350 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER4_DEFAULT   (_SMU_PPUPATD1_TIMER4_DEFAULT << 13)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 354 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER5   (0x1UL << 14)

Timer 5 access control bit

Definition at line 355 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER5_DEFAULT   (_SMU_PPUPATD1_TIMER5_DEFAULT << 14)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 359 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER6   (0x1UL << 15)

Timer 6 access control bit

Definition at line 360 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TIMER6_DEFAULT   (_SMU_PPUPATD1_TIMER6_DEFAULT << 15)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 364 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TRNG0   (0x1UL << 16)

True Random Number Generator 0 access control bit

Definition at line 365 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_TRNG0_DEFAULT   (_SMU_PPUPATD1_TRNG0_DEFAULT << 16)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 369 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_UART0   (0x1UL << 17)

Universal Asynchronous Receiver/Transmitter 0 access control bit

Definition at line 370 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_UART0_DEFAULT   (_SMU_PPUPATD1_UART0_DEFAULT << 17)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 374 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_UART1   (0x1UL << 18)

Universal Asynchronous Receiver/Transmitter 1 access control bit

Definition at line 375 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_UART1_DEFAULT   (_SMU_PPUPATD1_UART1_DEFAULT << 18)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 379 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART0   (0x1UL << 19)

Universal Synchronous/Asynchronous Receiver/Transmitter 0 access control bit

Definition at line 380 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART0_DEFAULT   (_SMU_PPUPATD1_USART0_DEFAULT << 19)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 384 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART1   (0x1UL << 20)

Universal Synchronous/Asynchronous Receiver/Transmitter 1 access control bit

Definition at line 385 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART1_DEFAULT   (_SMU_PPUPATD1_USART1_DEFAULT << 20)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 389 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART2   (0x1UL << 21)

Universal Synchronous/Asynchronous Receiver/Transmitter 2 access control bit

Definition at line 390 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART2_DEFAULT   (_SMU_PPUPATD1_USART2_DEFAULT << 21)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 394 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART3   (0x1UL << 22)

Universal Synchronous/Asynchronous Receiver/Transmitter 3 access control bit

Definition at line 395 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART3_DEFAULT   (_SMU_PPUPATD1_USART3_DEFAULT << 22)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 399 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART4   (0x1UL << 23)

Universal Synchronous/Asynchronous Receiver/Transmitter 4 access control bit

Definition at line 400 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART4_DEFAULT   (_SMU_PPUPATD1_USART4_DEFAULT << 23)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 404 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART5   (0x1UL << 24)

Universal Synchronous/Asynchronous Receiver/Transmitter 5 access control bit

Definition at line 405 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USART5_DEFAULT   (_SMU_PPUPATD1_USART5_DEFAULT << 24)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 409 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USB   (0x1UL << 25)

Universal Serial Bus Interface access control bit

Definition at line 410 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_USB_DEFAULT   (_SMU_PPUPATD1_USB_DEFAULT << 25)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 414 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WDOG0   (0x1UL << 26)

Watchdog access control bit

Definition at line 415 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WDOG0_DEFAULT   (_SMU_PPUPATD1_WDOG0_DEFAULT << 26)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 419 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WDOG1   (0x1UL << 27)

Watchdog access control bit

Definition at line 420 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WDOG1_DEFAULT   (_SMU_PPUPATD1_WDOG1_DEFAULT << 27)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 424 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER0   (0x1UL << 28)

Wide Timer 0 access control bit

Definition at line 425 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER0_DEFAULT   (_SMU_PPUPATD1_WTIMER0_DEFAULT << 28)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 429 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER1   (0x1UL << 29)

Wide Timer 0 access control bit

Definition at line 430 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER1_DEFAULT   (_SMU_PPUPATD1_WTIMER1_DEFAULT << 29)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 434 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER2   (0x1UL << 30)

Wide Timer 2 access control bit

Definition at line 435 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER2_DEFAULT   (_SMU_PPUPATD1_WTIMER2_DEFAULT << 30)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 439 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER3   (0x1UL << 31)

Wide Timer 3 access control bit

Definition at line 440 of file efm32gg11b_smu.h.

#define SMU_PPUPATD1_WTIMER3_DEFAULT   (_SMU_PPUPATD1_WTIMER3_DEFAULT << 31)

Shifted mode DEFAULT for SMU_PPUPATD1

Definition at line 444 of file efm32gg11b_smu.h.