EFR32BG21A020F1024IM32 Peripheral ParametersDevices > EFR32BG21A020F1024IM32

Detailed Description

Device peripheral parameter values.

Macros

#define ACMP(n)
 
#define ACMP0_DAC_INPUT   0x0UL /**> None */
 
#define ACMP0_EXT_OVR_IF   0x0UL /**> None */
 
#define ACMP1_DAC_INPUT   0x0UL /**> None */
 
#define ACMP1_EXT_OVR_IF   0x0UL /**> None */
 
#define ACMP_DAC_INPUT(n)
 
#define ACMP_EXT_OVR_IF(n)
 
#define ACMP_NUM(ref)
 
#define AGC_AMPLITUDE_WIDTH   0x14UL /**> New Param */
 
#define AGC_POWER_WIDTH   0xCUL /**> New Param */
 
#define AMUXCP0_AMUXCPNUM   0x0UL /**> AMUXCPNUM */
 
#define BUFC_LOG2NUMOFBUFS   0x2UL /**> New Param */
 
#define BUFC_LOG2NUMOFINPUTS   0x1UL /**> New Param */
 
#define BUFC_NUMOFBUFS   0x4UL /**> New Param */
 
#define BUFC_NUMOFINPUTS   0x1UL /**> New Param */
 
#define BURTC_CNTWIDTH   0x20UL /**> None */
 
#define BURTC_PRECNT_WIDTH   0xFUL /**> */
 
#define DMEM_ADDR_OVERRIDE_BITS   0x8UL /**> Override bits for remapping */
 
#define DMEM_BANK0_SIZE   0x4000UL /**> Bank0 Size */
 
#define DMEM_BANK1_SIZE   0x4000UL /**> Bank1 Size */
 
#define DMEM_BANK2_SIZE   0x4000UL /**> Bank2 Size */
 
#define DMEM_BANK3_SIZE   0x4000UL /**> Bank3 Size */
 
#define DMEM_BANK4_SIZE   0x4000UL /**> Bank4 Size */
 
#define DMEM_BANK5_SIZE   0x4000UL /**> Bank5 Size */
 
#define DMEM_BANK6_SIZE   0x0UL /**> Bank6 Size */
 
#define DMEM_BANK7_SIZE   0x0UL /**> Bank7 Size */
 
#define DMEM_NUM_BANK   0x6UL /**> Number of Banks */
 
#define DMEM_RAM_BWE_WIDTH   0x27UL /**> Bitwise write enable */
 
#define DMEM_RAM_DATA_WIDTH   0x27UL /**> Data width */
 
#define DMEM_RAM_DIV_PRESENT   0x0UL /**> Bank0 division present */
 
#define DMEM_RAM_ECC_EN   0x1UL /**> RAM_ECC_EN_PRESENT */
 
#define DMEM_RAM_ECCADDR_WIDTH   0x20UL /**> ECC Address width */
 
#define DMEM_RAMADDRBITS   0x11UL /**> Total address bits */
 
#define DMEM_RAMADDRMINBITS   0xEUL /**> address bits for one bank */
 
#define FRC_DEMOD_FILT_WIDTH   0x13UL /**> New Param */
 
#define FRC_FCD_NUM   0x4UL /**> None */
 
#define FRC_INTELEMENTS   0x10UL /**> None */
 
#define FRC_RAMADDR_WIDTH   0x10UL /**> None */
 
#define GPIO_MODE_WIDTH   0x4UL /**> Mode Width */
 
#define GPIO_NUM_EM4_WU   0xCUL /**> New Param */
 
#define GPIO_NUM_EVEN_PA   0x4UL /**> Num of even pins port A */
 
#define GPIO_NUM_EVEN_PB   0x1UL /**> Num of even pins port B */
 
#define GPIO_NUM_EVEN_PC   0x3UL /**> Num of even pins port C */
 
#define GPIO_NUM_EVEN_PD   0x3UL /**> Num of even pins port D */
 
#define GPIO_NUM_EXT_INT   0x8UL /**> New Param */
 
#define GPIO_NUM_EXT_INT_L   0x8UL /**> New Param */
 
#define GPIO_NUM_EXT_INT_U   0x0UL /**> New Param */
 
#define GPIO_NUM_EXT_INT_U_ZERO   0x0UL /**> New Param */
 
#define GPIO_NUM_ODD_PA   0x3UL /**> Num of odd pins port A */
 
#define GPIO_NUM_ODD_PB   0x1UL /**> Num of odd pins port B */
 
#define GPIO_NUM_ODD_PC   0x3UL /**> Num of odd pins port C */
 
#define GPIO_NUM_ODD_PD   0x2UL /**> Num of odd pins port D */
 
#define GPIO_PINSEL_WIDTH   0x4UL /**> Route config pin select width */
 
#define GPIO_PORT_A_WIDTH   0x7UL /**> Port A Width */
 
#define GPIO_PORT_A_WIDTH_ZERO   0x0UL /**> Port A Width is Zero */
 
#define GPIO_PORT_A_WL   0x7UL /**> New Param */
 
#define GPIO_PORT_A_WU   0x0UL /**> New Param */
 
#define GPIO_PORT_A_WU_ZERO   0x1UL /**> New Param */
 
#define GPIO_PORT_B_WIDTH   0x2UL /**> Port B Width */
 
#define GPIO_PORT_B_WIDTH_ZERO   0x0UL /**> Port B Width is Zero */
 
#define GPIO_PORT_B_WL   0x2UL /**> New Param */
 
#define GPIO_PORT_B_WU   0x0UL /**> New Param */
 
#define GPIO_PORT_B_WU_ZERO   0x1UL /**> New Param */
 
#define GPIO_PORT_C_WIDTH   0x6UL /**> Port C Width */
 
#define GPIO_PORT_C_WIDTH_ZERO   0x0UL /**> Port C Width is Zero */
 
#define GPIO_PORT_C_WL   0x6UL /**> New Param */
 
#define GPIO_PORT_C_WU   0x0UL /**> New Param */
 
#define GPIO_PORT_C_WU_ZERO   0x1UL /**> New Param */
 
#define GPIO_PORT_D_WIDTH   0x5UL /**> Port D Width */
 
#define GPIO_PORT_D_WIDTH_ZERO   0x0UL /**> Port D Width is Zero */
 
#define GPIO_PORT_D_WL   0x5UL /**> New Param */
 
#define GPIO_PORT_D_WU   0x0UL /**> New Param */
 
#define GPIO_PORT_D_WU_ZERO   0x1UL /**> New Param */
 
#define GPIO_PORTSEL_WIDTH   0x2UL /**> Route config port select width */
 
#define GPIO_SLEWRATE_WIDTH   0x3UL /**> Slew Rate Width Param */
 
#define HFRCO(n)
 
#define HFRCO_NUM(ref)
 
#define I2C(n)
 
#define I2C0_DELAY   0x7D0UL /**> Delay cell selection */
 
#define I2C0_DELAY_CHAIN_NUM   0x2UL /**> Number of delay chain */
 
#define I2C1_DELAY   0x7D0UL /**> Delay cell selection */
 
#define I2C1_DELAY_CHAIN_NUM   0x2UL /**> Number of delay chain */
 
#define I2C_DELAY(n)
 
#define I2C_DELAY_CHAIN_NUM(n)
 
#define I2C_NUM(ref)
 
#define IADC0_CONFIGNUM   0x2UL /**> CONFIG */
 
#define IADC0_ENTRIES   0x10UL /**> ENTRIES */
 
#define IADC0_FULLRANGEUNIPOLAR   0x0UL /**> FULLRANGEUNIPOLAR */
 
#define IADC0_SCANBYTES   0x1UL /**> SCANBYTES */
 
#define ICACHE0_ADDR_BITS   0x12UL /**> Address bits */
 
#define ICACHE0_AHB_LITE   0x0UL /**> AHB Lite */
 
#define ICACHE0_DEFAULT_OFF   0x0UL /**> Default off */
 
#define ICACHE0_FLASH_SIZE   0x100000UL /**> Flash size */
 
#define ICACHE0_FLASH_START   0x0UL /**> Flash start */
 
#define ICACHE0_LOOPCACHE_MEM_ADDR_BITS   0x3UL /**> Loopcache Memory Address bits */
 
#define ICACHE0_LOOPCACHE_STICKINESS_BITS   0x4UL /**> Loopcache Stickiness bits */
 
#define ICACHE0_PARITY_BITS   0x1UL /**> Use Parity */
 
#define ICACHE0_PC_BITS   0x20UL /**> Performance Counter bits */
 
#define ICACHE0_PIPE_STAGE   0x1UL /**> Pipeline Stage */
 
#define ICACHE0_RAM_ADDR_BITS   0x0UL /**> RAM Address bits */
 
#define ICACHE0_RAM_DATA_BITS   0x0UL /**> RAM Data bits */
 
#define ICACHE0_SET_BITS   0x5UL /**> Set bits */
 
#define ICACHE0_USE_HREADY_GATING   0x1UL /**> Use HREADY gating */
 
#define ICACHE0_USE_IDLE_GATING   0x1UL /**> Use IDLE gating */
 
#define ICACHE0_USE_LOOPCACHE   0x1UL /**> Use Loopcache */
 
#define ICACHE0_WAY_BITS   0x1UL /**> Way bits */
 
#define ICACHE0_WORDS_PER_BLOCK   0x0UL /**> Words Per Block */
 
#define ICACHE0_WPB_BITS   0x1UL /**> Words Per Block bits */
 
#define ICACHE0_WPL_BITS   0x3UL /**> Words Per Line bits */
 
#define LDMA_CH_BITS   0x5UL /**> New Param */
 
#define LDMA_CH_NUM   0x8UL /**> New Param */
 
#define LDMA_FIFO_BITS   0x5UL /**> New Param */
 
#define LDMA_FIFO_DEPTH   0x10UL /**> New Param */
 
#define LDMAXBAR_CH_BITS   0x5UL /**> None */
 
#define LDMAXBAR_CH_NUM   0x8UL /**> None */
 
#define LDMAXBAR_SIGSEL_W   0x4UL /**> New Param */
 
#define LDMAXBAR_SOURCESEL_W   0x6UL /**> New Param */
 
#define LETIMER0_CNT_WIDTH   0x18UL /**> Count Width */
 
#define LFXO_CTUNE   0x1UL /**> CTUNE Present */
 
#define LFXO_NO_CTUNE   0x0UL /**> CTUNE Not Present */
 
#define MODEM_ADDR_WIDTH   0xBUL /**> New Param */
 
#define MODEM_AMPLITUDE_WIDTH   0x14UL /**> New Param */
 
#define MODEM_ANT_NUM   0x2UL /**> Antenna Number */
 
#define MODEM_DEC0_SIZE   0xFUL /**> New Param */
 
#define MODEM_DEMOD_RAM_WIDTH   0xAUL /**> New Param */
 
#define MODEM_DEMOD_WIDTH   0x8UL /**> New Param */
 
#define MODEM_IN_SIZE   0x8UL /**> New Param */
 
#define MODEM_INTERNAL_SIZE   0x13UL /**> New Param */
 
#define MODEM_LEADING_BITS_SIZE   0x4UL /**> New Param */
 
#define MODEM_PHASE_SIZE   0x8UL /**> New Param */
 
#define MODEM_POWER_WIDTH   0xCUL /**> New Param */
 
#define MODEM_RAM_SIZE   0x100UL /**> New Param */
 
#define MODEM_REMOVE_DEMOD_FILTER   0x0UL /**> New Param */
 
#define MODEM_SYMBOL_WIDTH   0x4UL /**> New Param */
 
#define MSC_FDIO_WIDTH   0x40UL /**> None */
 
#define MSC_FLASH_BLOCK_INFO_PCOUNT   0x8UL /**> None */
 
#define MSC_FLASHADDRBITS   0x14UL /**> None */
 
#define MSC_FLASHBLOCKADDRBITS   0x14UL /**> None */
 
#define MSC_INFO_PSIZE_BITS   0xDUL /**> None */
 
#define MSC_INFOADDRBITS   0x10UL /**> None */
 
#define MSC_INFOBLOCKADDRBITS   0x10UL /**> None */
 
#define MSC_MAIN_PSIZE_BITS   0xDUL /**> None */
 
#define MSC_REDUNDANCY   0x2UL /**> None */
 
#define MSC_YADDRBITS   0x6UL /**> None */
 
#define PER_REG_BLOCK_CLR_OFFSET   0x2000UL
 
#define PER_REG_BLOCK_SET_OFFSET   0x1000UL
 
#define PER_REG_BLOCK_TGL_OFFSET   0x3000UL
 
#define PROTIMER_CC_NUM   0x8UL /**> None */
 
#define PROTIMER_PRS_NUM   0xBUL /**> */
 
#define PRS_ASYNC_CH_NUM   0xCUL /**> None */
 
#define PRS_PRSSEL_WIDTH   0x4UL /**> New Param */
 
#define PRS_SPRSSEL_WIDTH   0x2UL /**> New Param */
 
#define PRS_SYNC_CH_NUM   0x4UL /**> None */
 
#define RAC_DPI_CHAN_COUNT   0x6UL /**> */
 
#define RAC_PRESC_BITS   0x7UL /**> None */
 
#define RAC_WAIT_BITS   0xAUL /**> None */
 
#define RDMEM_FRC_BANK0_SIZE   0x1000UL /**> FRC_RAM_BANK0_SIZE */
 
#define RDMEM_FRC_BANK1_SIZE   0x0UL /**> FRC_RAM_BANK1_SIZE */
 
#define RDMEM_FRC_BANK2_SIZE   0x0UL /**> FRC_RAM_BANK2_SIZE */
 
#define RDMEM_FRC_BANK3_SIZE   0x0UL /**> FRC_RAM_BANK3_SIZE */
 
#define RDMEM_FRC_BANK4_SIZE   0x0UL /**> FRC_RAM_BANK4_SIZE */
 
#define RDMEM_FRC_BANK5_SIZE   0x0UL /**> FRC_RAM_BANK5_SIZE */
 
#define RDMEM_FRC_BANK6_SIZE   0x0UL /**> FRC_RAM_BANK6_SIZE */
 
#define RDMEM_FRC_BANK7_SIZE   0x0UL /**> FRC_RAM_BANK7_SIZE */
 
#define RDMEM_FRC_NUM_BANK   0x1UL /**> FRC_NUM_BANK */
 
#define RDMEM_FRC_RAM_BWE_WIDTH   0x27UL /**> FRCRAM BWE width */
 
#define RDMEM_FRC_RAM_DATA_WIDTH   0x27UL /**> FRC_RAM_DATA_WIDTH */
 
#define RDMEM_FRC_RAM_ECC_EN   0x1UL /**> FRC RAM ECCEN */
 
#define RDMEM_FRC_RAMADDRBITS   0xCUL /**> FRC RAM ADDRBITS */
 
#define RDMEM_FRC_RAMADDRMINBITS   0xCUL /**> FRC RAM address bits for one bank */
 
#define RDMEM_FRC_RAMECCADDR_WIDTH   0x20UL /**> FRC RAM ECC Address width */
 
#define RDMEM_SEQ_BANK0_SIZE   0x2000UL /**> SEQ_RAM_BANK0_SIZE */
 
#define RDMEM_SEQ_BANK1_SIZE   0x0UL /**> SEQ_RAM_BANK1_SIZE */
 
#define RDMEM_SEQ_BANK2_SIZE   0x0UL /**> SEQ_RAM_BANK2_SIZE */
 
#define RDMEM_SEQ_BANK3_SIZE   0x0UL /**> SEQ_RAM_BANK3_SIZE */
 
#define RDMEM_SEQ_BANK4_SIZE   0x0UL /**> SEQ_RAM_BANK4_SIZE */
 
#define RDMEM_SEQ_BANK5_SIZE   0x0UL /**> SEQ_RAM_BANK5_SIZE */
 
#define RDMEM_SEQ_BANK6_SIZE   0x0UL /**> SEQ_RAM_BANK6_SIZE */
 
#define RDMEM_SEQ_BANK7_SIZE   0x0UL /**> SEQ_RAM_BANK7_SIZE */
 
#define RDMEM_SEQ_NUM_BANK   0x1UL /**> SEQ_NUM_BANK */
 
#define RDMEM_SEQ_RAM_BWE_WIDTH   0x27UL /**> SEQRAM BWE width */
 
#define RDMEM_SEQ_RAM_DATA_WIDTH   0x27UL /**> SEQ_RAM_DATA_WIDTH */
 
#define RDMEM_SEQ_RAM_ECC_EN   0x1UL /**> SEQ RAM ECCEN */
 
#define RDMEM_SEQ_RAMADDRBITS   0xDUL /**> SEQ RAM ADDRBITS */
 
#define RDMEM_SEQ_RAMADDRMINBITS   0xDUL /**> SEQ RAM address bits for one bank */
 
#define RDMEM_SEQ_RAMECCADDR_WIDTH   0x20UL /**> SEQ RAM ECC Address width */
 
#define RTCC_CC_NUM   0x3UL /**> None */
 
#define SYNTH_CHPDACBITS   0x8UL /**> */
 
#define SYNTH_DACDEMBITS   0x3UL /**> */
 
#define SYNTH_MMDDENOMBITS   0x9UL /**> */
 
#define SYNTH_MOD_OUT_WIDTH   0x11UL /**> */
 
#define SYNTH_MODEM_AFCADJ_WIDTH   0x13UL /**> */
 
#define SYNTH_ZERO_IF_RECEIVER   0x0UL /**> */
 
#define SYSCFG_CHIP_FAMILY   0x30UL /**> CHIP Family */
 
#define SYSCFG_CHIP_REV_MAJOR   0x1UL /**> Major revision */
 
#define SYSCFG_CHIP_REV_MINOR   0x0UL /**> Minor revision */
 
#define SYSCFG_DEMODRAM_INST_COUNT   0x1UL /**> */
 
#define SYSCFG_FRCRAM_INST_COUNT   0x1UL /**> */
 
#define SYSCFG_RAM0_INST_COUNT   0x6UL /**> None */
 
#define SYSCFG_SEQRAM_INST_COUNT   0x1UL /**> None */
 
#define SYSCFG_SWINT_NUM   0x4UL /**> Software interupts */
 
#define TIMER(n)
 
#define TIMER0_CC_NUM   0x3UL /**> Number of Compare/Capture Channels */
 
#define TIMER0_CNTWIDTH   0x20UL /**> Counter Width */
 
#define TIMER0_DTI   0x1UL /**> Dead-time insertion enabled */
 
#define TIMER0_DTI_CC_NUM   0x3UL /**> Number of DTI Channels */
 
#define TIMER0_NO_DTI   0x0UL /**> */
 
#define TIMER1_CC_NUM   0x3UL /**> Number of Compare/Capture Channels */
 
#define TIMER1_CNTWIDTH   0x10UL /**> Counter Width */
 
#define TIMER1_DTI   0x1UL /**> Dead-time insertion enabled */
 
#define TIMER1_DTI_CC_NUM   0x3UL /**> Number of DTI Channels */
 
#define TIMER1_NO_DTI   0x0UL /**> */
 
#define TIMER2_CC_NUM   0x3UL /**> Number of Compare/Capture Channels */
 
#define TIMER2_CNTWIDTH   0x10UL /**> Counter Width */
 
#define TIMER2_DTI   0x1UL /**> Dead-time insertion enabled */
 
#define TIMER2_DTI_CC_NUM   0x3UL /**> Number of DTI Channels */
 
#define TIMER2_NO_DTI   0x0UL /**> */
 
#define TIMER3_CC_NUM   0x3UL /**> Number of Compare/Capture Channels */
 
#define TIMER3_CNTWIDTH   0x10UL /**> Counter Width */
 
#define TIMER3_DTI   0x1UL /**> Dead-time insertion enabled */
 
#define TIMER3_DTI_CC_NUM   0x3UL /**> Number of DTI Channels */
 
#define TIMER3_NO_DTI   0x0UL /**> */
 
#define TIMER_CC_NUM(n)
 
#define TIMER_CNTWIDTH(n)
 
#define TIMER_DTI(n)
 
#define TIMER_DTI_CC_NUM(n)
 
#define TIMER_NO_DTI(n)
 
#define TIMER_NUM(ref)
 
#define USART(n)
 
#define USART0_AUTOTX_REG   0x1UL /**> None */
 
#define USART0_AUTOTX_REG_B   0x0UL /**> None */
 
#define USART0_AUTOTX_TRIGGER   0x1UL /**> None */
 
#define USART0_AUTOTX_TRIGGER_B   0x0UL /**> New Param */
 
#define USART0_CLK_PRS   0x1UL /**> None */
 
#define USART0_CLK_PRS_B   0x0UL /**> New Param */
 
#define USART0_FLOW_CONTROL   0x1UL /**> None */
 
#define USART0_FLOW_CONTROL_B   0x0UL /**> New Param */
 
#define USART0_I2S   0x1UL /**> None */
 
#define USART0_I2S_B   0x0UL /**> New Param */
 
#define USART0_IRDA_AVAILABLE   0x1UL /**> None */
 
#define USART0_IRDA_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART0_MVDIS_FUNC   0x1UL /**> None */
 
#define USART0_MVDIS_FUNC_B   0x0UL /**> New Param */
 
#define USART0_RX_PRS   0x1UL /**> None */
 
#define USART0_RX_PRS_B   0x0UL /**> New Param */
 
#define USART0_SC_AVAILABLE   0x1UL /**> None */
 
#define USART0_SC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART0_SYNC_AVAILABLE   0x1UL /**> None */
 
#define USART0_SYNC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART0_SYNC_LATE_SAMPLE   0x1UL /**> None */
 
#define USART0_SYNC_LATE_SAMPLE_B   0x0UL /**> New Param */
 
#define USART0_TIMER   0x1UL /**> New Param */
 
#define USART0_TIMER_B   0x0UL /**> New Param */
 
#define USART1_AUTOTX_REG   0x1UL /**> None */
 
#define USART1_AUTOTX_REG_B   0x0UL /**> None */
 
#define USART1_AUTOTX_TRIGGER   0x1UL /**> None */
 
#define USART1_AUTOTX_TRIGGER_B   0x0UL /**> New Param */
 
#define USART1_CLK_PRS   0x1UL /**> None */
 
#define USART1_CLK_PRS_B   0x0UL /**> New Param */
 
#define USART1_FLOW_CONTROL   0x1UL /**> None */
 
#define USART1_FLOW_CONTROL_B   0x0UL /**> New Param */
 
#define USART1_I2S   0x1UL /**> None */
 
#define USART1_I2S_B   0x0UL /**> New Param */
 
#define USART1_IRDA_AVAILABLE   0x1UL /**> None */
 
#define USART1_IRDA_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART1_MVDIS_FUNC   0x1UL /**> None */
 
#define USART1_MVDIS_FUNC_B   0x0UL /**> New Param */
 
#define USART1_RX_PRS   0x1UL /**> None */
 
#define USART1_RX_PRS_B   0x0UL /**> New Param */
 
#define USART1_SC_AVAILABLE   0x1UL /**> None */
 
#define USART1_SC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART1_SYNC_AVAILABLE   0x1UL /**> None */
 
#define USART1_SYNC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART1_SYNC_LATE_SAMPLE   0x1UL /**> None */
 
#define USART1_SYNC_LATE_SAMPLE_B   0x0UL /**> New Param */
 
#define USART1_TIMER   0x1UL /**> New Param */
 
#define USART1_TIMER_B   0x0UL /**> New Param */
 
#define USART2_AUTOTX_REG   0x1UL /**> None */
 
#define USART2_AUTOTX_REG_B   0x0UL /**> None */
 
#define USART2_AUTOTX_TRIGGER   0x1UL /**> None */
 
#define USART2_AUTOTX_TRIGGER_B   0x0UL /**> New Param */
 
#define USART2_CLK_PRS   0x1UL /**> None */
 
#define USART2_CLK_PRS_B   0x0UL /**> New Param */
 
#define USART2_FLOW_CONTROL   0x1UL /**> None */
 
#define USART2_FLOW_CONTROL_B   0x0UL /**> New Param */
 
#define USART2_I2S   0x1UL /**> None */
 
#define USART2_I2S_B   0x0UL /**> New Param */
 
#define USART2_IRDA_AVAILABLE   0x1UL /**> None */
 
#define USART2_IRDA_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART2_MVDIS_FUNC   0x1UL /**> None */
 
#define USART2_MVDIS_FUNC_B   0x0UL /**> New Param */
 
#define USART2_RX_PRS   0x1UL /**> None */
 
#define USART2_RX_PRS_B   0x0UL /**> New Param */
 
#define USART2_SC_AVAILABLE   0x1UL /**> None */
 
#define USART2_SC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART2_SYNC_AVAILABLE   0x1UL /**> None */
 
#define USART2_SYNC_AVAILABLE_B   0x0UL /**> New Param */
 
#define USART2_SYNC_LATE_SAMPLE   0x1UL /**> None */
 
#define USART2_SYNC_LATE_SAMPLE_B   0x0UL /**> New Param */
 
#define USART2_TIMER   0x1UL /**> New Param */
 
#define USART2_TIMER_B   0x0UL /**> New Param */
 
#define USART_AUTOTX_REG(n)
 
#define USART_AUTOTX_REG_B(n)
 
#define USART_AUTOTX_TRIGGER(n)
 
#define USART_AUTOTX_TRIGGER_B(n)
 
#define USART_CLK_PRS(n)
 
#define USART_CLK_PRS_B(n)
 
#define USART_FLOW_CONTROL(n)
 
#define USART_FLOW_CONTROL_B(n)
 
#define USART_I2S(n)
 
#define USART_I2S_B(n)
 
#define USART_IRDA_AVAILABLE(n)
 
#define USART_IRDA_AVAILABLE_B(n)
 
#define USART_MVDIS_FUNC(n)
 
#define USART_MVDIS_FUNC_B(n)
 
#define USART_NUM(ref)
 
#define USART_RX_PRS(n)
 
#define USART_RX_PRS_B(n)
 
#define USART_SC_AVAILABLE(n)
 
#define USART_SC_AVAILABLE_B(n)
 
#define USART_SYNC_AVAILABLE(n)
 
#define USART_SYNC_AVAILABLE_B(n)
 
#define USART_SYNC_LATE_SAMPLE(n)
 
#define USART_SYNC_LATE_SAMPLE_B(n)
 
#define USART_TIMER(n)
 
#define USART_TIMER_B(n)
 
#define WDOG(n)
 
#define WDOG0_PCNUM   0x2UL /**> None */
 
#define WDOG1_PCNUM   0x2UL /**> None */
 
#define WDOG_NUM(ref)
 
#define WDOG_PCNUM(n)
 

Macro Definition Documentation

#define ACMP (   n)
Value:
(((n) == 0) ? ACMP0 \
: ((n) == 1) ? ACMP1 \
: 0x0UL)
#define ACMP1
Definition: efr32bg21a020f1024im32.h:643
#define ACMP0
Definition: efr32bg21a020f1024im32.h:641

Definition at line 1016 of file efr32bg21a020f1024im32.h.

#define ACMP_DAC_INPUT (   n)
Value:
(((n) == 0) ? ACMP0_DAC_INPUT \
: ((n) == 1) ? ACMP1_DAC_INPUT \
: 0x0UL)

Definition at line 1022 of file efr32bg21a020f1024im32.h.

#define ACMP_EXT_OVR_IF (   n)
Value:
(((n) == 0) ? ACMP0_EXT_OVR_IF \
: ((n) == 1) ? ACMP1_EXT_OVR_IF \
: 0x0UL)

Definition at line 1025 of file efr32bg21a020f1024im32.h.

#define ACMP_NUM (   ref)
Value:
(((ref) == ACMP0) ? 0 \
: ((ref) == ACMP1) ? 1 \
: -1)
#define ACMP1
Definition: efr32bg21a020f1024im32.h:643
#define ACMP0
Definition: efr32bg21a020f1024im32.h:641

Definition at line 1019 of file efr32bg21a020f1024im32.h.

#define HFRCO (   n)
Value:
(((n) == 0) ? HFRCO0 \
: ((n) == 1) ? HFRCOEM23 \
: 0x0UL)
#define HFRCO0
Definition: efr32bg21a020f1024im32.h:579
#define HFRCOEM23
Definition: efr32bg21a020f1024im32.h:647

Definition at line 1030 of file efr32bg21a020f1024im32.h.

#define HFRCO_NUM (   ref)
Value:
(((ref) == HFRCO0) ? 0 \
: ((ref) == HFRCOEM23) ? 1 \
: -1)
#define HFRCO0
Definition: efr32bg21a020f1024im32.h:579
#define HFRCOEM23
Definition: efr32bg21a020f1024im32.h:647

Definition at line 1033 of file efr32bg21a020f1024im32.h.

#define I2C (   n)
Value:
(((n) == 0) ? I2C0 \
: ((n) == 1) ? I2C1 \
: 0x0UL)
#define I2C1
Definition: efr32bg21a020f1024im32.h:619
#define I2C0
Definition: efr32bg21a020f1024im32.h:645

Definition at line 1038 of file efr32bg21a020f1024im32.h.

#define I2C_DELAY (   n)
Value:
(((n) == 0) ? I2C0_DELAY \
: ((n) == 1) ? I2C1_DELAY \
: 0x0UL)

Definition at line 1044 of file efr32bg21a020f1024im32.h.

#define I2C_DELAY_CHAIN_NUM (   n)
Value:
(((n) == 0) ? I2C0_DELAY_CHAIN_NUM \
: ((n) == 1) ? I2C1_DELAY_CHAIN_NUM \
: 0x0UL)

Definition at line 1047 of file efr32bg21a020f1024im32.h.

#define I2C_NUM (   ref)
Value:
(((ref) == I2C0) ? 0 \
: ((ref) == I2C1) ? 1 \
: -1)
#define I2C1
Definition: efr32bg21a020f1024im32.h:619
#define I2C0
Definition: efr32bg21a020f1024im32.h:645

Definition at line 1041 of file efr32bg21a020f1024im32.h.

#define PER_REG_BLOCK_CLR_OFFSET   0x2000UL

Offset to CLEAR register block

Definition at line 730 of file efr32bg21a020f1024im32.h.

Referenced by BUS_RegBitWrite(), and BUS_RegMaskedClear().

#define PER_REG_BLOCK_SET_OFFSET   0x1000UL

Offset to SET register block

Definition at line 729 of file efr32bg21a020f1024im32.h.

Referenced by BUS_RegBitWrite(), and BUS_RegMaskedSet().

#define PER_REG_BLOCK_TGL_OFFSET   0x3000UL

Offset to TOGGLE register block

Definition at line 731 of file efr32bg21a020f1024im32.h.

#define TIMER (   n)
Value:
(((n) == 0) ? TIMER0 \
: ((n) == 1) ? TIMER1 \
: ((n) == 2) ? TIMER2 \
: ((n) == 3) ? TIMER3 \
: 0x0UL)
#define TIMER2
Definition: efr32bg21a020f1024im32.h:607
#define TIMER0
Definition: efr32bg21a020f1024im32.h:603
#define TIMER3
Definition: efr32bg21a020f1024im32.h:609
#define TIMER1
Definition: efr32bg21a020f1024im32.h:605

Definition at line 1052 of file efr32bg21a020f1024im32.h.

#define TIMER_CC_NUM (   n)
Value:
(((n) == 0) ? TIMER0_CC_NUM \
: ((n) == 1) ? TIMER1_CC_NUM \
: ((n) == 2) ? TIMER2_CC_NUM \
: ((n) == 3) ? TIMER3_CC_NUM \
: 0x0UL)

Definition at line 1062 of file efr32bg21a020f1024im32.h.

#define TIMER_CNTWIDTH (   n)
Value:
(((n) == 0) ? TIMER0_CNTWIDTH \
: ((n) == 1) ? TIMER1_CNTWIDTH \
: ((n) == 2) ? TIMER2_CNTWIDTH \
: ((n) == 3) ? TIMER3_CNTWIDTH \
: 0x0UL)

Definition at line 1067 of file efr32bg21a020f1024im32.h.

#define TIMER_DTI (   n)
Value:
(((n) == 0) ? TIMER0_DTI \
: ((n) == 1) ? TIMER1_DTI \
: ((n) == 2) ? TIMER2_DTI \
: ((n) == 3) ? TIMER3_DTI \
: 0x0UL)

Definition at line 1072 of file efr32bg21a020f1024im32.h.

#define TIMER_DTI_CC_NUM (   n)
Value:
(((n) == 0) ? TIMER0_DTI_CC_NUM \
: ((n) == 1) ? TIMER1_DTI_CC_NUM \
: ((n) == 2) ? TIMER2_DTI_CC_NUM \
: ((n) == 3) ? TIMER3_DTI_CC_NUM \
: 0x0UL)

Definition at line 1077 of file efr32bg21a020f1024im32.h.

#define TIMER_NO_DTI (   n)
Value:
(((n) == 0) ? TIMER0_NO_DTI \
: ((n) == 1) ? TIMER1_NO_DTI \
: ((n) == 2) ? TIMER2_NO_DTI \
: ((n) == 3) ? TIMER3_NO_DTI \
: 0x0UL)

Definition at line 1082 of file efr32bg21a020f1024im32.h.

#define TIMER_NUM (   ref)
Value:
(((ref) == TIMER0) ? 0 \
: ((ref) == TIMER1) ? 1 \
: ((ref) == TIMER2) ? 2 \
: ((ref) == TIMER3) ? 3 \
: -1)
#define TIMER2
Definition: efr32bg21a020f1024im32.h:607
#define TIMER0
Definition: efr32bg21a020f1024im32.h:603
#define TIMER3
Definition: efr32bg21a020f1024im32.h:609
#define TIMER1
Definition: efr32bg21a020f1024im32.h:605

Definition at line 1057 of file efr32bg21a020f1024im32.h.

#define USART (   n)
Value:
(((n) == 0) ? USART0 \
: ((n) == 1) ? USART1 \
: ((n) == 2) ? USART2 \
: 0x0UL)
#define USART1
Definition: efr32bg21a020f1024im32.h:613
#define USART0
Definition: efr32bg21a020f1024im32.h:611
#define USART2
Definition: efr32bg21a020f1024im32.h:615

Definition at line 1089 of file efr32bg21a020f1024im32.h.

#define USART_AUTOTX_REG (   n)
Value:
(((n) == 0) ? USART0_AUTOTX_REG \
: ((n) == 1) ? USART1_AUTOTX_REG \
: ((n) == 2) ? USART2_AUTOTX_REG \
: 0x0UL)

Definition at line 1097 of file efr32bg21a020f1024im32.h.

#define USART_AUTOTX_REG_B (   n)
Value:
(((n) == 0) ? USART0_AUTOTX_REG_B \
: ((n) == 1) ? USART1_AUTOTX_REG_B \
: ((n) == 2) ? USART2_AUTOTX_REG_B \
: 0x0UL)

Definition at line 1101 of file efr32bg21a020f1024im32.h.

#define USART_AUTOTX_TRIGGER (   n)
Value:
(((n) == 0) ? USART0_AUTOTX_TRIGGER \
: ((n) == 1) ? USART1_AUTOTX_TRIGGER \
: ((n) == 2) ? USART2_AUTOTX_TRIGGER \
: 0x0UL)

Definition at line 1105 of file efr32bg21a020f1024im32.h.

#define USART_AUTOTX_TRIGGER_B (   n)
Value:
(((n) == 0) ? USART0_AUTOTX_TRIGGER_B \
: ((n) == 1) ? USART1_AUTOTX_TRIGGER_B \
: ((n) == 2) ? USART2_AUTOTX_TRIGGER_B \
: 0x0UL)

Definition at line 1109 of file efr32bg21a020f1024im32.h.

#define USART_CLK_PRS (   n)
Value:
(((n) == 0) ? USART0_CLK_PRS \
: ((n) == 1) ? USART1_CLK_PRS \
: ((n) == 2) ? USART2_CLK_PRS \
: 0x0UL)

Definition at line 1113 of file efr32bg21a020f1024im32.h.

#define USART_CLK_PRS_B (   n)
Value:
(((n) == 0) ? USART0_CLK_PRS_B \
: ((n) == 1) ? USART1_CLK_PRS_B \
: ((n) == 2) ? USART2_CLK_PRS_B \
: 0x0UL)

Definition at line 1117 of file efr32bg21a020f1024im32.h.

#define USART_FLOW_CONTROL (   n)
Value:
(((n) == 0) ? USART0_FLOW_CONTROL \
: ((n) == 1) ? USART1_FLOW_CONTROL \
: ((n) == 2) ? USART2_FLOW_CONTROL \
: 0x0UL)

Definition at line 1121 of file efr32bg21a020f1024im32.h.

#define USART_FLOW_CONTROL_B (   n)
Value:
(((n) == 0) ? USART0_FLOW_CONTROL_B \
: ((n) == 1) ? USART1_FLOW_CONTROL_B \
: ((n) == 2) ? USART2_FLOW_CONTROL_B \
: 0x0UL)

Definition at line 1125 of file efr32bg21a020f1024im32.h.

#define USART_I2S (   n)
Value:
(((n) == 0) ? USART0_I2S \
: ((n) == 1) ? USART1_I2S \
: ((n) == 2) ? USART2_I2S \
: 0x0UL)

Definition at line 1129 of file efr32bg21a020f1024im32.h.

#define USART_I2S_B (   n)
Value:
(((n) == 0) ? USART0_I2S_B \
: ((n) == 1) ? USART1_I2S_B \
: ((n) == 2) ? USART2_I2S_B \
: 0x0UL)

Definition at line 1133 of file efr32bg21a020f1024im32.h.

#define USART_IRDA_AVAILABLE (   n)
Value:
(((n) == 0) ? USART0_IRDA_AVAILABLE \
: ((n) == 1) ? USART1_IRDA_AVAILABLE \
: ((n) == 2) ? USART2_IRDA_AVAILABLE \
: 0x0UL)

Definition at line 1137 of file efr32bg21a020f1024im32.h.

#define USART_IRDA_AVAILABLE_B (   n)
Value:
(((n) == 0) ? USART0_IRDA_AVAILABLE_B \
: ((n) == 1) ? USART1_IRDA_AVAILABLE_B \
: ((n) == 2) ? USART2_IRDA_AVAILABLE_B \
: 0x0UL)

Definition at line 1141 of file efr32bg21a020f1024im32.h.

#define USART_MVDIS_FUNC (   n)
Value:
(((n) == 0) ? USART0_MVDIS_FUNC \
: ((n) == 1) ? USART1_MVDIS_FUNC \
: ((n) == 2) ? USART2_MVDIS_FUNC \
: 0x0UL)

Definition at line 1145 of file efr32bg21a020f1024im32.h.

#define USART_MVDIS_FUNC_B (   n)
Value:
(((n) == 0) ? USART0_MVDIS_FUNC_B \
: ((n) == 1) ? USART1_MVDIS_FUNC_B \
: ((n) == 2) ? USART2_MVDIS_FUNC_B \
: 0x0UL)

Definition at line 1149 of file efr32bg21a020f1024im32.h.

#define USART_NUM (   ref)
Value:
(((ref) == USART0) ? 0 \
: ((ref) == USART1) ? 1 \
: ((ref) == USART2) ? 2 \
: -1)
#define USART1
Definition: efr32bg21a020f1024im32.h:613
#define USART0
Definition: efr32bg21a020f1024im32.h:611
#define USART2
Definition: efr32bg21a020f1024im32.h:615

Definition at line 1093 of file efr32bg21a020f1024im32.h.

#define USART_RX_PRS (   n)
Value:
(((n) == 0) ? USART0_RX_PRS \
: ((n) == 1) ? USART1_RX_PRS \
: ((n) == 2) ? USART2_RX_PRS \
: 0x0UL)

Definition at line 1153 of file efr32bg21a020f1024im32.h.

#define USART_RX_PRS_B (   n)
Value:
(((n) == 0) ? USART0_RX_PRS_B \
: ((n) == 1) ? USART1_RX_PRS_B \
: ((n) == 2) ? USART2_RX_PRS_B \
: 0x0UL)

Definition at line 1157 of file efr32bg21a020f1024im32.h.

#define USART_SC_AVAILABLE (   n)
Value:
(((n) == 0) ? USART0_SC_AVAILABLE \
: ((n) == 1) ? USART1_SC_AVAILABLE \
: ((n) == 2) ? USART2_SC_AVAILABLE \
: 0x0UL)

Definition at line 1161 of file efr32bg21a020f1024im32.h.

#define USART_SC_AVAILABLE_B (   n)
Value:
(((n) == 0) ? USART0_SC_AVAILABLE_B \
: ((n) == 1) ? USART1_SC_AVAILABLE_B \
: ((n) == 2) ? USART2_SC_AVAILABLE_B \
: 0x0UL)

Definition at line 1165 of file efr32bg21a020f1024im32.h.

#define USART_SYNC_AVAILABLE (   n)
Value:
(((n) == 0) ? USART0_SYNC_AVAILABLE \
: ((n) == 1) ? USART1_SYNC_AVAILABLE \
: ((n) == 2) ? USART2_SYNC_AVAILABLE \
: 0x0UL)

Definition at line 1169 of file efr32bg21a020f1024im32.h.

#define USART_SYNC_AVAILABLE_B (   n)
Value:
(((n) == 0) ? USART0_SYNC_AVAILABLE_B \
: ((n) == 1) ? USART1_SYNC_AVAILABLE_B \
: ((n) == 2) ? USART2_SYNC_AVAILABLE_B \
: 0x0UL)

Definition at line 1173 of file efr32bg21a020f1024im32.h.

#define USART_SYNC_LATE_SAMPLE (   n)
Value:
(((n) == 0) ? USART0_SYNC_LATE_SAMPLE \
: ((n) == 1) ? USART1_SYNC_LATE_SAMPLE \
: ((n) == 2) ? USART2_SYNC_LATE_SAMPLE \
: 0x0UL)

Definition at line 1177 of file efr32bg21a020f1024im32.h.

#define USART_SYNC_LATE_SAMPLE_B (   n)
Value:
(((n) == 0) ? USART0_SYNC_LATE_SAMPLE_B \
: ((n) == 1) ? USART1_SYNC_LATE_SAMPLE_B \
: ((n) == 2) ? USART2_SYNC_LATE_SAMPLE_B \
: 0x0UL)

Definition at line 1181 of file efr32bg21a020f1024im32.h.

#define USART_TIMER (   n)
Value:
(((n) == 0) ? USART0_TIMER \
: ((n) == 1) ? USART1_TIMER \
: ((n) == 2) ? USART2_TIMER \
: 0x0UL)

Definition at line 1185 of file efr32bg21a020f1024im32.h.

#define USART_TIMER_B (   n)
Value:
(((n) == 0) ? USART0_TIMER_B \
: ((n) == 1) ? USART1_TIMER_B \
: ((n) == 2) ? USART2_TIMER_B \
: 0x0UL)

Definition at line 1189 of file efr32bg21a020f1024im32.h.

#define WDOG (   n)
Value:
(((n) == 0) ? WDOG0 \
: ((n) == 1) ? WDOG1 \
: 0x0UL)
#define WDOG0
Definition: efr32bg21a020f1024im32.h:649
#define WDOG1
Definition: efr32bg21a020f1024im32.h:651

Definition at line 1195 of file efr32bg21a020f1024im32.h.

#define WDOG_NUM (   ref)
Value:
(((ref) == WDOG0) ? 0 \
: ((ref) == WDOG1) ? 1 \
: -1)
#define WDOG0
Definition: efr32bg21a020f1024im32.h:649
#define WDOG1
Definition: efr32bg21a020f1024im32.h:651

Definition at line 1198 of file efr32bg21a020f1024im32.h.

#define WDOG_PCNUM (   n)
Value:
(((n) == 0) ? WDOG0_PCNUM \
: ((n) == 1) ? WDOG1_PCNUM \
: 0x0UL)

Definition at line 1201 of file efr32bg21a020f1024im32.h.