LDMA_TypeDef Struct ReferenceDevices > LDMA

LDMA Register Declaration

Definition at line 49 of file efm32gg11b_ldma.h.

#include <efm32gg11b_ldma.h>

Data Fields

LDMA_CH_TypeDef CH [24U]
 
__IM uint32_t CHBUSY
 
__IOM uint32_t CHDONE
 
__IOM uint32_t CHEN
 
__IOM uint32_t CTRL
 
__IOM uint32_t DBGHALT
 
__IOM uint32_t IEN
 
__IM uint32_t IF
 
__IOM uint32_t IFC
 
__IOM uint32_t IFS
 
__IOM uint32_t LINKLOAD
 
__IOM uint32_t REQCLEAR
 
__IOM uint32_t REQDIS
 
__IM uint32_t REQPEND
 
uint32_t RESERVED0 [5U]
 
uint32_t RESERVED1 [7U]
 
uint32_t RESERVED2 [4U]
 
__IM uint32_t STATUS
 
__IOM uint32_t SWREQ
 
__IOM uint32_t SYNC
 

Field Documentation

LDMA_CH_TypeDef LDMA_TypeDef::CH[24U]

DMA Channel Registers

Definition at line 70 of file efm32gg11b_ldma.h.

__IM uint32_t LDMA_TypeDef::CHBUSY

DMA Channel Busy Register

Definition at line 55 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CHDONE

DMA Channel Linking Done Register (Single-Cycle RMW)

Definition at line 56 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CHEN

DMA Channel Enable Register (Single-Cycle RMW)

Definition at line 54 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::CTRL

DMA Control Register

Definition at line 50 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::DBGHALT

DMA Channel Debug Halt Register

Definition at line 57 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IEN

Interrupt Enable Register

Definition at line 67 of file efm32gg11b_ldma.h.

__IM uint32_t LDMA_TypeDef::IF

Interrupt Flag Register

Definition at line 64 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 66 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 65 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::LINKLOAD

DMA Channel Link Load Register

Definition at line 61 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::REQCLEAR

DMA Channel Request Clear Register

Definition at line 62 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::REQDIS

DMA Channel Request Disable Register

Definition at line 59 of file efm32gg11b_ldma.h.

__IM uint32_t LDMA_TypeDef::REQPEND

DMA Channel Requests Pending Register

Definition at line 60 of file efm32gg11b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED0[5U]

Reserved for future use

Definition at line 53 of file efm32gg11b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED1[7U]

Reserved for future use

Definition at line 63 of file efm32gg11b_ldma.h.

uint32_t LDMA_TypeDef::RESERVED2[4U]

Reserved registers

Definition at line 69 of file efm32gg11b_ldma.h.

__IM uint32_t LDMA_TypeDef::STATUS

DMA Status Register

Definition at line 51 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::SWREQ

DMA Channel Software Transfer Request Register

Definition at line 58 of file efm32gg11b_ldma.h.

__IOM uint32_t LDMA_TypeDef::SYNC

DMA Synchronization Trigger Register (Single-Cycle RMW)

Definition at line 52 of file efm32gg11b_ldma.h.


The documentation for this struct was generated from the following file:
  • C:/repos/embsw_super_h1/platform/Device/SiliconLabs/EFM32GG11B/Include/efm32gg11b_ldma.h