This file contains the type definitions for efr32xg1x chip-specific aspects of RAIL.
License#
Copyright 2020 Silicon Laboratories Inc. www.silabs.com
SPDX-License-Identifier: Zlib
The licensor of this software is Silicon Laboratories Inc.
This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software.
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required.
Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
This notice may not be removed or altered from any source distribution.
Modules#
Macros#
SLI_LIBRARY_BUILD.
The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.
This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.
Time it takes to take care of protocol switching.
Indicates the number of RF Paths supported.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.
Backwards compatibility define.
Backwards compatibility define.
Backwards compatibility define.
Backwards compatibility define.
Backwards compatibility define.
Backwards compatibility define.
The number of PA's on this chip.
The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.
Default PRS channel to use when configuring sleep.
Default RTCC channel to use when configuring sleep.
Default timer synchronization configuration.
The minimum value for a consistent RAIL transition.
The maximum value for a consistent RAIL transition.
Macro Definition Documentation#
__RAIL_CHIP_SPECIFIC_H_#
#define __RAIL_CHIP_SPECIFIC_H_
SLI_LIBRARY_BUILD.
Include guard
44 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_ENUM#
#define RAIL_ENUMValue:
(name)
The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.
Instead, uint8_t typedefs are used in compiled code for all enumerations. For documentation purposes, this is converted to an actual enumeration since it's much easier to read in Doxygen.
55 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_ENUM_GENERIC#
#define RAIL_ENUM_GENERICValue:
(name, type)
This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.
See RAIL_ENUM() for more information.
59 of file chip/efr32/efr32xg1x/rail_chip_specific.hTRANSITION_TIME_US#
#define TRANSITION_TIME_USValue:
430
Time it takes to take care of protocol switching.
191 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_RF_PATHS#
#define RAIL_RF_PATHSValue:
1
Indicates the number of RF Paths supported.
209 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_LP_MAXValue:
(7U)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.
241 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_HP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_HP_MAXValue:
(252U)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.
246 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAXValue:
(248U)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.
251 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_LP_MINValue:
(1U)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.
256 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_HP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_HP_MINValue:
(0U)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.
261 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MINValue:
(0U)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.
266 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_LP_MAX#
#define RAIL_TX_POWER_LEVEL_LP_MAXValue:
RAIL_TX_POWER_LEVEL_2P4_LP_MAX
Backwards compatibility define.
269 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_HP_MAX#
#define RAIL_TX_POWER_LEVEL_HP_MAXValue:
RAIL_TX_POWER_LEVEL_2P4_HP_MAX
Backwards compatibility define.
271 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MAXValue:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
Backwards compatibility define.
273 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_LP_MIN#
#define RAIL_TX_POWER_LEVEL_LP_MINValue:
RAIL_TX_POWER_LEVEL_2P4_LP_MIN
Backwards compatibility define.
275 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_HP_MIN#
#define RAIL_TX_POWER_LEVEL_HP_MINValue:
RAIL_TX_POWER_LEVEL_2P4_HP_MIN
Backwards compatibility define.
277 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MINValue:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
Backwards compatibility define.
279 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_NUM_PA#
#define RAIL_NUM_PAValue:
(3U)
The number of PA's on this chip.
(Including Virtual PAs)
284 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL#
#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNELValue:
(55U)
The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.
310 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT#
#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULTValue:
(7U)
Default PRS channel to use when configuring sleep.
325 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT#
#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULTValue:
(0U)
Default RTCC channel to use when configuring sleep.
332 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_TIMER_SYNC_DEFAULT#
#define RAIL_TIMER_SYNC_DEFAULTValue:
Default timer synchronization configuration.
336 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_MINIMUM_TRANSITION_US#
#define RAIL_MINIMUM_TRANSITION_USValue:
(100U)
The minimum value for a consistent RAIL transition.
Note
Transitions may need to be slower than this when using longer RAIL_TxPowerConfig_t::rampTime values
356 of file chip/efr32/efr32xg1x/rail_chip_specific.hRAIL_MAXIMUM_TRANSITION_US#
#define RAIL_MAXIMUM_TRANSITION_USValue:
(1000000U)
The maximum value for a consistent RAIL transition.
(_SILICON_LABS_32B_SERIES_1_CONFIG == 1)
365 of file chip/efr32/efr32xg1x/rail_chip_specific.h