AN1515: SiWG917 M4 Sleep Application Note#

The SiWG917 System-on-Chip (SoC) integrates an ARM Cortex-M4 core along with Network Wireless Processor (NWP) subsystem. To maximize energy efficiency, the M4 core supports a range of power-saving sleep modes coordinated by the Power Manager.

When the M4 CPU and peripherals are idle, the Power Manager automatically transitions the SoC into an appropriate Power Save Sleep mode. During these periods, clocks are gated and selected RAM banks can be retained.

This mechanism allows applications to reduce active current draw by a significant amount when idle, while retaining context for rapid wake-up through configured wake-up sources.

Note: This document focuses exclusively on M4 sleep management, and NWP sleep modes are referenced only where necessary for power-measurement context.

Key Points#

• Explains M4 sleep modes and Power Manager integration.

• Details RAM, wake-up, peripheral, and clock configurations.

• Guides porting from bare-metal to FreeRTOS with M4 sleep support.

• Covers debug methods — Universal Asynchronous Receiver/Transmitter (UART), General-Purpose Input/Output (GPIO), and transition callbacks.

• Provides power data references and sample applications.