WF200 Registers

This section presents the registers exposed by WF200 to the host. The section focuses on the registers involved in the WF200 FMAC driver. Those registers can be accessed both using SPI or SDIO.

SPI

In SPI, the MSB is used to define the following data as read or write (1: read, 0: write). The next three bits are the actual register address, and all other bits define the length of the following transmission. Each command word is 16 bits long.

Bit number1514 downto 1211 downto 0
FunctionR/WAddressLength

Each command for this operational mode is formatted as described below.

SPI Access to WF200 Registers

For each command, there can be data in or data out, and data can be any multiple of 16 bit blocks.

SDIO

In SDIO, these registers are defined for command 53 (::wf200_host_sdio_transfer_cmd53). The addresses below are used as the first 6 bits of SDIO command address field.

1. Address Map

NameSPI AddressSDIO AddressDescription
Config0x000x00Configuration register
Control0x010x04Control register
Input /Output_channel0x020x08Input/output queue port
Ahb port0x030x0CDirect AHB port access
Address0x040x10AHB: Full 32-bit address SRAM: Memory address offset (0=first SRAM address)
Sram_data_port0x050x14Direct Shared RAM APB port access
General purpose0x060x18General purpose registers: extended indirect mode to configure various parameters for SYXO, RFBIAS, CLKMULT, EMUOSC, HDREG…
Frame_output_channel0x07N/ASPI Only: Used to read data in current output queue without giving length in SPI command. When the Host sends this read command, HIF provides 16-bit length information (in bytes) before sending data.

2. CONFIG Register

NameSize (bits)SPI addressSDIO address
CONFIG320x000x00
BitResetRead/WriteDescription
31-240x1RDevice identification information
23-20Unused
190x0R/WSPI: Unused SDIO: Disable CRC check on data. 0: Normal CRC check behaviour. 1: Disable CRC check on data transfers (CRC result assumed always correct).
180x0R/WSPI: Dout_posedge_enable (1=enable, 0=disable) SDIO: Dout_posedge_enable (1=enable, 0=disable) This in intended to be used with 50MHz SDIO clock speed.
17:160x0R/WIrq_enable 10 = wlan_rdy enable 01 = data-irq enable 00 = both irq’s disabled 11 = both irq’s enabled
150x0R/WSPI: 0 (normal functional mode) SDIO: Disable DAT1 interrupt mechanism 0: Normal DAT1 interrupt behaviour. 1: Disable DAT1 interrupts. Interrupt to host are still available on WIRQ pin.
140x1R/WCpu_reset (1 = cpu reset, 0 = cpu non_reset)
130x0R/WDirect_pre_fetch apb (1 = channel busy, 0 = channel non-busy)
120x1R/WCpu_clk_disable (1 = disable clk, 0 = enable clk)
110x0R/WDirect_pre_fetch_ahb (1 = channel busy, 0 = channel non-busy)
100x1R/WDirect_access_mode apb/ahb (0 = queue mode, 1 = direct access mode)
9:80x0 SPI 0x2 SDIOR/W RMode0 (“00”) : 4 bytes are sent : B1,B0,B3,B2 Mode1 (“01”) : 4 bytes are sent : B3,B2,B1,B0. This only make sense if the HOST works in 32-bit mode (SW-controlled) Mode2 (“10”) : 4 bytes are sent : B0,B1,B2,B3 Note : In SPI the config register access will always be in word_mode 0, regardless of the real value of word mode
70x0 0x0R/W RSPI : CSN-framing disable (1= spi_cs is not checked , 0=spi_cs is checked) SDIO: Err 7 (1 = host misses CRC error, 0 = no error)
60x0RErr 6 (1 = host tries to send data with no hif input queue entry programmed, 0 = no error)
50x0RErr 5 (1 = host tries to send data larger than hif input buffer, 0 = no error)
40x0RErr 4 (1 = host tries to send data when hif buffers overrun, 0 = no error)
30x0RErr 3 (1 = host tries to read data with no hif output queue entry programmed, 0 = no error)
20x0RErr 2 (1 = host tries to read data less than output message length, 0 = no error)
10x0RErr 1 (1 = host tries to read data when hif buffers underrun, 0 = no error)
00x0 0x0R RSPI: Err 0 (1 = CSN Framing error ,0=no error) SDIO:Err 0 (1= Buffer number mismatch, 0= no error)

3. CONTROL Register

NameSize (bits)SPI AddressSDIO Address
CONTROL160x010x4
BitResetRead/WriteDescription
15:140x0RFrame type information: 11 = Wi-Fi data packet 10 = Wi-Fi management packet 01 = any other indication 00 = any confirmation
130x0RWlan_rdy (1= wlan is ready, 0 = wlan not ready)
120x0R/WWlan_wup (1= init wake up , 0 = do not init wakeup)
11:00x0RNext output Queue item length

4. Card Common Control Register (SDIO specific)

NameSize (Bytes)Address
CCCR2560x00000
OffsetResetRead/WriteDescription
0x000x11R/OCCCR/SDIO Revision
0x010x0R/OSD Specification Revision
0x020x0R/WI/O Function Enable
0x030x0R/OI/O Function Ready
0x040x0R/WInterrupt Enable (7 functions and 1 master)
0x050x0R/OInterrupt Pending for each function
0x060x0W/OI/O Function Abort
0x070x0R/W*Bus Interface Control
0x080x1FR/W*Card Capability
0x09-0x0B0x1000R/OCommon CIS Pointer
0x0C0x0R/W*Bus Suspend
0x0D0x0R/W*Function Select
0x0E0x0R/OFunction Execution Flags
0x0F0x0R/OFunction Ready Flags
0x10-0x110x0R/WFunction0 Block Size
0x120x0R/W*Power Control
0x13-0xEFunused – Reserved for Future Use
0xF0-0xFFunused – Reserved for Vendors

R/W*: There are also R/O bits

5. Function Basic Registers (FBR) of Function1 (SDIO specific)

Register NameSize (Bytes)Address
FBR2560x00100
OffsetResetRead/WriteDescription
0x000x0R/OFunction1 Standard SDIO Function Interface Code
0x010x0R/OFunction1 Standard SDIO Function Interface Code
0x020x0R/W*Power Selection
0x03-0x08unused - RFU
0x0B-0x090x2000R/OPointer to Function1 Card Information Pointer (CIS)
0x0C-0x0E0x0R/OPointer to Function1 Code Storage Area (CSA)
0x0F0x0R/OData Access Window to CSA
0x10-0x110x0R/WFunction1 Block Size
0x12-0xFFunused - RFU

R/W*: There are also R/O bits