Enable Watchdog when initialization completed.

Counter keeps running during debug halt.

Select WDOG clear source: False: Write to the clear bit will clear the WDOG counter True: Rising edge on the PRS Source 0 will clear the WDOG counter.

Counter keeps running when in EM2.

Counter keeps running when in EM3.

Block EMU from entering EM4.

Block SW from disabling LFRCO/LFXO oscillators.

Block SW from modifying the configuration (a reset is needed to reconfigure).

Clock source to use for Watchdog.

Watchdog timeout period.

Select warning time as % of the Watchdog timeout.

Select illegal window time as % of the Watchdog timeout.

Disable Watchdog reset output if true.