RFF PLL initialization structure.

When using this structure you need to modify the X, Y and N factor and the desired host target frequency to match the components placed on the board (namely the RFFPLL reference clock). X, Y, N values for a 39MHz HFXO:

• Formula for host clock output: frequency = (freq HFXO * dividerN / 2) / dividerY

• Formula for radio clock output: freq = (freq HFXO * dividerN / 2) / (dividerX / 2)