TFT Initialization structure.

Public Attributes#

External memory bank for driving display.

Color source for masking and alpha blending.

Trigger for updating frame buffer pointer.

bool

Drive DCLK from negative clock edge of internal clock.

Masking and alpha blending mode.

TFT Direct Drive mode.

TFT Polarity for Chip Select (CS) Line.

TFT Polarity for Data Clock (DCLK) Line.

TFT Polarity for Data Enable (DATAEN) Line.

TFT Polarity for Horizontal Sync (HSYNC) Line.

TFT Polarity for Vertical Sync (VSYNC) Line.

int

Horizontal size in pixels.

int

Horizontal Front Porch Size.

int

Horizontal Back Porch Size.

int

Horizontal Synchronization Pulse Width.

int

Vertical size in pixels.

int

Vertical Front Porch Size.

int

Vertical Back Porch Size.

int

Vertical Synchronization Pulse Width.

uint32_t

TFT Frame Buffer address, offset to EBI bank base address.

int

TFT DCLK period in internal cycles.

int

Starting position of External Direct Drive relative to DCLK inactive edge.

int

Number of cycles RGB data is driven before active edge of DCLK.

int

Number of cycles RGB data is held after active edge of DCLK.

Public Attribute Documentation#

bank#

EBI_TFTBank_TypeDef EBI_TFTInit_TypeDef::bank

External memory bank for driving display.


width#

EBI_TFTWidth_TypeDef EBI_TFTInit_TypeDef::width

Width.


colSrc#

EBI_TFTColorSrc_TypeDef EBI_TFTInit_TypeDef::colSrc

Color source for masking and alpha blending.


interleave#

EBI_TFTInterleave_TypeDef EBI_TFTInit_TypeDef::interleave

Bus Interleave mode.


fbTrigger#

EBI_TFTFrameBufTrigger_TypeDef EBI_TFTInit_TypeDef::fbTrigger

Trigger for updating frame buffer pointer.


shiftDClk#

bool EBI_TFTInit_TypeDef::shiftDClk

Drive DCLK from negative clock edge of internal clock.


maskBlend#

EBI_TFTMaskBlend_TypeDef EBI_TFTInit_TypeDef::maskBlend

Masking and alpha blending mode.


driveMode#

EBI_TFTDDMode_TypeDef EBI_TFTInit_TypeDef::driveMode

TFT Direct Drive mode.


csPolarity#

EBI_Polarity_TypeDef EBI_TFTInit_TypeDef::csPolarity

TFT Polarity for Chip Select (CS) Line.


dclkPolarity#

EBI_Polarity_TypeDef EBI_TFTInit_TypeDef::dclkPolarity

TFT Polarity for Data Clock (DCLK) Line.


dataenPolarity#

EBI_Polarity_TypeDef EBI_TFTInit_TypeDef::dataenPolarity

TFT Polarity for Data Enable (DATAEN) Line.


hsyncPolarity#

EBI_Polarity_TypeDef EBI_TFTInit_TypeDef::hsyncPolarity

TFT Polarity for Horizontal Sync (HSYNC) Line.


vsyncPolarity#

EBI_Polarity_TypeDef EBI_TFTInit_TypeDef::vsyncPolarity

TFT Polarity for Vertical Sync (VSYNC) Line.


hsize#

int EBI_TFTInit_TypeDef::hsize

Horizontal size in pixels.


hPorchFront#

int EBI_TFTInit_TypeDef::hPorchFront

Horizontal Front Porch Size.


hPorchBack#

int EBI_TFTInit_TypeDef::hPorchBack

Horizontal Back Porch Size.


hPulseWidth#

int EBI_TFTInit_TypeDef::hPulseWidth

Horizontal Synchronization Pulse Width.


vsize#

int EBI_TFTInit_TypeDef::vsize

Vertical size in pixels.


vPorchFront#

int EBI_TFTInit_TypeDef::vPorchFront

Vertical Front Porch Size.


vPorchBack#

int EBI_TFTInit_TypeDef::vPorchBack

Vertical Back Porch Size.


vPulseWidth#

int EBI_TFTInit_TypeDef::vPulseWidth

Vertical Synchronization Pulse Width.


addressOffset#

uint32_t EBI_TFTInit_TypeDef::addressOffset

TFT Frame Buffer address, offset to EBI bank base address.


dclkPeriod#

int EBI_TFTInit_TypeDef::dclkPeriod

TFT DCLK period in internal cycles.


startPosition#

int EBI_TFTInit_TypeDef::startPosition

Starting position of External Direct Drive relative to DCLK inactive edge.


setupCycles#

int EBI_TFTInit_TypeDef::setupCycles

Number of cycles RGB data is driven before active edge of DCLK.


holdCycles#

int EBI_TFTInit_TypeDef::holdCycles

Number of cycles RGB data is held after active edge of DCLK.