EUSART - Extended USART#

Extended Universal Synchronous/Asynchronous Receiver/Transmitter.

Introduction#

This module contains functions to control the Enhanced Universal Synchronous / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, therefore, be connected to an external transceiver to communicate with another host using the serial link.

It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, and IrDA devices.

EUSART has a wide selection of operating modes, frame formats, and baud rates. All features are supported through the API of this module.

This module does not support DMA configuration. UARTDRV and SPIDRV drivers provide full support for DMA and more.

Example#

EUSART Async TX example:

{
  EUSART_UartInit_TypeDef init = EUSART_UART_INIT_DEFAULT_HF;

  // Configure the clocks.
  CMU_ClockSelectSet(cmuClock_EUSART0CLK, cmuSelect_EM01GRPCCLK);
  CMU_ClockEnable(cmuClock_EUSART0CLK, true);
  // Initialize the EUSART
  EUSART_UartInitHf(EUSART0, &init);
  EUSART_Tx(EUSART0, data);
}

EUSART Sync SPI Transaction example:

{
  EUSART_SpiInit_TypeDef init_master = EUSART_SPI_MASTER_INIT_DEFAULT_HF;

  // Configure the clocks.
  CMU_ClockSelectSet(cmuClock_EM01GRPCCLK, cmuSelect_HFRCODPLL);
  CMU_ClockEnable(cmuClock_EUSART1, true);
  CMU_ClockEnable(cmuClock_GPIO, true);

  //Configure the SPI ports
  GPIO_PinModeSet(sclk_port, sclk_pin, gpioModePushPull, 0);
  GPIO_PinModeSet(mosi_port, mosi_pin, gpioModePushPull, 0);
  GPIO_PinModeSet(mosi_port, miso_pin, gpioModeInput, 0);

  // Connect EUSART to ports
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (mosi_port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
                                                   | (mosi_pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (miso_port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
                                                   | (miso_pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (sclk_port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
                                                   | (sclk_pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;

  // Initialize the EUSART
  EUSART_SpiInit(EUSART1, &init_master);
  EUSART_Spi_TxRx(EUSART1, data);
}

EM2 guidelines for non EM2-Capable instances#

Note

EUSART instances located in the PD1 power domain are non EM2-capable. The EUSART_EM2_CAPABLE() and EUSART_NOT_EM2_CAPABLE() macros can be used to determine whether or not a EUSART instance is EM2-Capable.

Follow theses steps when entering in EM2:

Wait for the current transaction to complete with TXCIF interrupt
Disable TX and RX using TXDIS and RXDIS cmd
Poll for EUSARTn_SYNCBUSY.TXDIS and EUSARTn_SYNCBUSY.RXDIS to go low
Wait for EUSARTn_STATUS.TXENS and EUSARTn_STATUS.RXENS to go low
Disable SCLKPEN and CSPEN in GPIO if they were previously enabled
Enter EM2

On wakeup from EM2, EUSART transmitter/receiver and relevant GPIO (SCLKPEN and CSPEN) must be re-enabled. For example:

{
  // Enable TX and RX
  EUSART_Enable(EUSART0, eusartEnable);
  BUS_RegMaskedWrite(&GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN,
                     _GPIO_EUSART_ROUTEEN_TXPEN_MASK | _GPIO_EUSART_ROUTEEN_SCLKPEN_MASK,
                     GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN);
}

Modules#

EUSART_AdvancedInit_TypeDef

EUSART_UartInit_TypeDef

EUSART_IrDAInit_TypeDef

EUSART_PrsTriggerInit_TypeDef

EUSART_DaliInit_TypeDef

Enumerations#

enum

EUSART_Enable_TypeDef {

eusartDisable = 0x0

eusartEnableRx = (EUSART_CMD_RXEN | EUSART_CMD_TXDIS)

eusartEnableTx = (EUSART_CMD_TXEN | EUSART_CMD_RXDIS)

eusartEnable = (EUSART_CMD_RXEN | EUSART_CMD_TXEN)

}

Enable selection.

enum

EUSART_Databits_TypeDef {

eusartDataBits7 = EUSART_FRAMECFG_DATABITS_SEVEN

eusartDataBits8 = EUSART_FRAMECFG_DATABITS_EIGHT

eusartDataBits9 = EUSART_FRAMECFG_DATABITS_NINE

}

Data bit selection.

enum

EUSART_Parity_TypeDef {

eusartNoParity = EUSART_FRAMECFG_PARITY_NONE

eusartEvenParity = EUSART_FRAMECFG_PARITY_EVEN

eusartOddParity = EUSART_FRAMECFG_PARITY_ODD

}

Parity selection.

enum

EUSART_Stopbits_TypeDef {

eusartStopbits0p5 = EUSART_FRAMECFG_STOPBITS_HALF

eusartStopbits1p5 = EUSART_FRAMECFG_STOPBITS_ONEANDAHALF

eusartStopbits1 = EUSART_FRAMECFG_STOPBITS_ONE

eusartStopbits2 = EUSART_FRAMECFG_STOPBITS_TWO

}

Stop bits selection.

enum

EUSART_OVS_TypeDef {

eusartOVS16 = EUSART_CFG0_OVS_X16

eusartOVS8 = EUSART_CFG0_OVS_X8

eusartOVS6 = EUSART_CFG0_OVS_X6

eusartOVS4 = EUSART_CFG0_OVS_X4

eusartOVS0 = EUSART_CFG0_OVS_DISABLE

}

Oversampling selection, used for asynchronous operation.

enum

EUSART_HwFlowControl_TypeDef {

eusartHwFlowControlNone = 0

eusartHwFlowControlCts

eusartHwFlowControlRts

eusartHwFlowControlCtsAndRts

}

HW flow control config.

enum

EUSART_LoopbackEnable_TypeDef {

eusartLoopbackEnable = EUSART_CFG0_LOOPBK

eusartLoopbackDisable = _EUSART_CFG0_RESETVALUE

}

Loopback enable.

enum

EUSART_MajorityVote_TypeDef {

eusartMajorityVoteEnable = EUSART_CFG0_MVDIS_DEFAULT

eusartMajorityVoteDisable = EUSART_CFG0_MVDIS

}

Majority vote enable.

enum

EUSART_BlockRx_TypeDef {

eusartBlockRxEnable = EUSART_CMD_RXBLOCKEN

eusartBlockRxDisable = EUSART_CMD_RXBLOCKDIS

}

Block reception enable.

enum

EUSART_TristateTx_TypeDef {

eusartTristateTxEnable = EUSART_CMD_TXTRIEN

eusartTristateTxDisable = EUSART_CMD_TXTRIDIS

}

TX output tristate enable.

enum

EUSART_IrDARxFilterEnable_TypeDef {

eusartIrDARxFilterEnable = EUSART_IRHFCFG_IRHFFILT_ENABLE

eusartIrDARxFilterDisable = EUSART_IRHFCFG_IRHFFILT_DISABLE

}

IrDA filter enable.

enum

EUSART_IrDAPulseWidth_Typedef {

eusartIrDAPulseWidthOne = EUSART_IRHFCFG_IRHFPW_ONE

eusartIrDAPulseWidthTwo = EUSART_IRHFCFG_IRHFPW_TWO

eusartIrDAPulseWidthThree = EUSART_IRHFCFG_IRHFPW_THREE

eusartIrDAPulseWidthFour = EUSART_IRHFCFG_IRHFPW_FOUR

}

Pulse width selection for IrDA mode.

enum

EUSART_PrsTriggerEnable_TypeDef {

eusartPrsTriggerDisable = 0x0

eusartPrsTriggerEnableRx = EUSART_TRIGCTRL_RXTEN

eusartPrsTriggerEnableTx = EUSART_TRIGCTRL_TXTEN

eusartPrsTriggerEnableRxTx = (EUSART_TRIGCTRL_RXTEN | EUSART_TRIGCTRL_TXTEN)

}

PRS trigger enable.

enum

EUSART_InvertIO_TypeDef {

eusartInvertIODisable = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE)

eusartInvertRxEnable = EUSART_CFG0_RXINV_ENABLE

eusartInvertTxEnable = EUSART_CFG0_TXINV_ENABLE

eusartInvertIOEnable = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE)

}

IO polarity selection.

enum

EUSART_AutoTxDelay_TypeDef {

eusartAutoTxDelayNone = EUSART_TIMINGCFG_TXDELAY_NONE

eusartAutoTxDelaySingle = EUSART_TIMINGCFG_TXDELAY_SINGLE

eusartAutoTxDelayDouble = EUSART_TIMINGCFG_TXDELAY_DOUBLE

eusartAutoTxDelayTripple = EUSART_TIMINGCFG_TXDELAY_TRIPPLE

}

Auto TX delay transmission.

enum

EUSART_RxFifoWatermark_TypeDef {

eusartRxFiFoWatermark1Frame = EUSART_CFG1_RXFIW_ONEFRAME

eusartRxFiFoWatermark2Frame = EUSART_CFG1_RXFIW_TWOFRAMES

eusartRxFiFoWatermark3Frame = EUSART_CFG1_RXFIW_THREEFRAMES

eusartRxFiFoWatermark4Frame = EUSART_CFG1_RXFIW_FOURFRAMES

}

RX FIFO Interrupt ans Status Watermark.

enum

EUSART_TxFifoWatermark_TypeDef {

eusartTxFiFoWatermark1Frame = EUSART_CFG1_TXFIW_ONEFRAME

eusartTxFiFoWatermark2Frame = EUSART_CFG1_TXFIW_TWOFRAMES

eusartTxFiFoWatermark3Frame = EUSART_CFG1_TXFIW_THREEFRAMES

eusartTxFiFoWatermark4Frame = EUSART_CFG1_TXFIW_FOURFRAMES

}

TX FIFO Interrupt and Status Watermark.

Typedefs#

typedef uint8_t

EUSART_PrsChannel_TypeDef

PRS Channel type.

Functions#

void

EUSART_UartInitHf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)

Initialize EUSART when used in UART mode with the high frequency clock.

void

EUSART_UartInitLf(EUSART_TypeDef *eusart, const EUSART_UartInit_TypeDef *init)

Initialize EUSART when used in UART mode with the low frequency clock.

void

EUSART_IrDAInit(EUSART_TypeDef *eusart, const EUSART_IrDAInit_TypeDef *irdaInit)

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

void

EUSART_Reset(EUSART_TypeDef *eusart)

Configure EUSART to its reset state.

void

EUSART_Enable(EUSART_TypeDef *eusart, EUSART_Enable_TypeDef enable)

Enable/disable EUSART receiver and/or transmitter.

uint8_t

EUSART_Rx(EUSART_TypeDef *eusart)

Receive one 8 bit frame, (or part of 9 bit frame).

uint16_t

EUSART_RxExt(EUSART_TypeDef *eusart)

Receive one 8-16 bit frame with extended information.

void

EUSART_Tx(EUSART_TypeDef *eusart, uint8_t data)

Transmit one frame.

void

EUSART_TxExt(EUSART_TypeDef *eusart, uint16_t data)

Transmit one 8-9 bit frame with extended control.

void

EUSART_BaudrateSet(EUSART_TypeDef *eusart, uint32_t refFreq, uint32_t baudrate)

Configure the baudrate (or as close as possible to a specified baudrate).

uint32_t

EUSART_BaudrateGet(EUSART_TypeDef *eusart)

Get the current baudrate.

void

EUSART_RxBlock(EUSART_TypeDef *eusart, EUSART_BlockRx_TypeDef enable)

Enable/Disable reception operation until the configured start frame is received.

void

EUSART_TxTristateSet(EUSART_TypeDef *eusart, EUSART_TristateTx_TypeDef enable)

Enable/Disable the tristating of the transmitter output.

void

EUSART_PrsTriggerEnable(EUSART_TypeDef *eusart, const EUSART_PrsTriggerInit_TypeDef *init)

Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.

uint32_t

EUSART_StatusGet(EUSART_TypeDef *eusart)

Get EUSART STATUS register.

void

EUSART_IntClear(EUSART_TypeDef *eusart, uint32_t flags)

Clear one or more pending EUSART interrupts.

void

EUSART_IntDisable(EUSART_TypeDef *eusart, uint32_t flags)

Disable one or more EUSART interrupts.

void

EUSART_IntEnable(EUSART_TypeDef *eusart, uint32_t flags)

Enable one or more EUSART interrupts.

uint32_t

EUSART_IntGet(EUSART_TypeDef *eusart)

Get pending EUSART interrupt flags.

uint32_t

EUSART_IntGetEnabled(EUSART_TypeDef *eusart)

Get enabled and pending EUSART interrupt flags.

void

EUSART_IntSet(EUSART_TypeDef *eusart, uint32_t flags)

Set one or more pending EUSART interrupts from SW.

Macros#

#define

EUSART0_FIFO_DEPTH 4

Define EUSART FIFO Depth information.

#define

EUSART1_FIFO_DEPTH EUSART0_FIFO_DEPTH

#define

EUSART2_FIFO_DEPTH EUSART0_FIFO_DEPTH

#define

EUSART3_FIFO_DEPTH EUSART0_FIFO_DEPTH

#define

EUSART4_FIFO_DEPTH EUSART0_FIFO_DEPTH

#define

EUSART_FIFO_DEPTH (n)

#define

EUSART_UART_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in UART mode with high-frequency clock.

#define

EUSART_DEFAULT_START_FRAME 0x00u

Default start frame configuration, i.e. feature disabled.

#define

EUSART_ADVANCED_INIT_DEFAULT undefined

Default configuration for EUSART advanced initialization structure.

#define

EUSART_UART_INIT_DEFAULT_LF undefined

Default configuration for EUSART initialization structure in UART mode with low-frequency clock.

#define

EUSART_IRDA_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.

#define

EUSART_IRDA_INIT_DEFAULT_LF undefined

Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

Enumeration Documentation#

EUSART_Enable_TypeDef#

EUSART_Enable_TypeDef

Enable selection.

Enumerator
eusartDisable	Disable the peripheral.
eusartEnableRx	Enable receiver only, transmitter disabled.
eusartEnableTx	Enable transmitter only, receiver disabled.
eusartEnable	Enable both receiver and transmitter.

Definition at line 176 of file platform/emlib/inc/em_eusart.h

EUSART_Databits_TypeDef#

EUSART_Databits_TypeDef

Data bit selection.

Enumerator
eusartDataBits7	7 data bits.
eusartDataBits8	8 data bits.
eusartDataBits9	9 data bits.

Definition at line 191 of file platform/emlib/inc/em_eusart.h

EUSART_Parity_TypeDef#

EUSART_Parity_TypeDef

Parity selection.

Enumerator
eusartNoParity	No parity.
eusartEvenParity	Even parity.
eusartOddParity	Odd parity.

Definition at line 207 of file platform/emlib/inc/em_eusart.h

EUSART_Stopbits_TypeDef#

EUSART_Stopbits_TypeDef

Stop bits selection.

Enumerator
eusartStopbits0p5	0.5 stop bits.
eusartStopbits1p5	1.5 stop bits.
eusartStopbits1	1 stop bits.
eusartStopbits2	2 stop bits.

Definition at line 214 of file platform/emlib/inc/em_eusart.h

EUSART_OVS_TypeDef#

EUSART_OVS_TypeDef

Oversampling selection, used for asynchronous operation.

Enumerator
eusartOVS16	16x oversampling (normal).
eusartOVS8	8x oversampling.
eusartOVS6	6x oversampling.
eusartOVS4	4x oversampling.
eusartOVS0	Oversampling disabled.

Definition at line 222 of file platform/emlib/inc/em_eusart.h

EUSART_HwFlowControl_TypeDef#

EUSART_HwFlowControl_TypeDef

HW flow control config.

Enumerator
eusartHwFlowControlNone	No HW Flow Control.
eusartHwFlowControlCts	CTS HW Flow Control.
eusartHwFlowControlRts	RTS HW Flow Control.
eusartHwFlowControlCtsAndRts	CTS and RTS HW Flow Control.

Definition at line 231 of file platform/emlib/inc/em_eusart.h

EUSART_LoopbackEnable_TypeDef#

EUSART_LoopbackEnable_TypeDef

Loopback enable.

Enumerator
eusartLoopbackEnable	Enable loopback.
eusartLoopbackDisable	Disable loopback.

Definition at line 239 of file platform/emlib/inc/em_eusart.h

EUSART_MajorityVote_TypeDef#

EUSART_MajorityVote_TypeDef

Majority vote enable.

Enumerator
eusartMajorityVoteEnable	Enable majority vote for 16x, 8x and 6x oversampling modes.
eusartMajorityVoteDisable	Disable majority vote for 16x, 8x and 6x oversampling modes.

Definition at line 245 of file platform/emlib/inc/em_eusart.h

EUSART_BlockRx_TypeDef#

EUSART_BlockRx_TypeDef

Block reception enable.

Enumerator
eusartBlockRxEnable	Block reception enable, resulting in all incoming frames being discarded.
eusartBlockRxDisable	Block reception disable, resulting in all incoming frames being loaded into the RX FIFO.

Definition at line 251 of file platform/emlib/inc/em_eusart.h

EUSART_TristateTx_TypeDef#

EUSART_TristateTx_TypeDef

TX output tristate enable.

Enumerator
eusartTristateTxEnable	Tristates the transmitter output.
eusartTristateTxDisable	Disables tristating of the transmitter output.

Definition at line 257 of file platform/emlib/inc/em_eusart.h

EUSART_IrDARxFilterEnable_TypeDef#

EUSART_IrDARxFilterEnable_TypeDef

IrDA filter enable.

Enumerator
eusartIrDARxFilterEnable	Enable filter on demodulator.
eusartIrDARxFilterDisable	Disable filter on demodulator.

Definition at line 263 of file platform/emlib/inc/em_eusart.h

EUSART_IrDAPulseWidth_Typedef#

EUSART_IrDAPulseWidth_Typedef

Pulse width selection for IrDA mode.

Enumerator
eusartIrDAPulseWidthOne	IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8.
eusartIrDAPulseWidthTwo	IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8.
eusartIrDAPulseWidthThree	IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8.
eusartIrDAPulseWidthFour	IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8.

Definition at line 269 of file platform/emlib/inc/em_eusart.h

EUSART_PrsTriggerEnable_TypeDef#

EUSART_PrsTriggerEnable_TypeDef

PRS trigger enable.

Enumerator
eusartPrsTriggerDisable	Disable trigger on both receiver and transmitter.
eusartPrsTriggerEnableRx	Enable receive trigger only, transmit disabled.
eusartPrsTriggerEnableTx	Enable transmit trigger only, receive disabled.
eusartPrsTriggerEnableRxTx	Enable trigger on both receive and transmit.

Definition at line 284 of file platform/emlib/inc/em_eusart.h

EUSART_InvertIO_TypeDef#

EUSART_InvertIO_TypeDef

IO polarity selection.

Enumerator
eusartInvertIODisable	Disable inversion on both RX and TX signals.
eusartInvertRxEnable	Invert RX signal, before receiver.
eusartInvertTxEnable	Invert TX signal, after transmitter.
eusartInvertIOEnable	Enable trigger on both receive and transmit.

Definition at line 302 of file platform/emlib/inc/em_eusart.h

EUSART_AutoTxDelay_TypeDef#

EUSART_AutoTxDelay_TypeDef

Auto TX delay transmission.

Enumerator
eusartAutoTxDelayNone	Frames are transmitted immediately.
eusartAutoTxDelaySingle	Transmission of new frames is delayed by a single bit period.
eusartAutoTxDelayDouble	Transmission of new frames is delayed by a two bit periods.
eusartAutoTxDelayTripple	Transmission of new frames is delayed by a three bit periods.

Definition at line 317 of file platform/emlib/inc/em_eusart.h

EUSART_RxFifoWatermark_TypeDef#

EUSART_RxFifoWatermark_TypeDef

RX FIFO Interrupt ans Status Watermark.

Enumerator
eusartRxFiFoWatermark1Frame
eusartRxFiFoWatermark2Frame
eusartRxFiFoWatermark3Frame
eusartRxFiFoWatermark4Frame

Definition at line 332 of file platform/emlib/inc/em_eusart.h

EUSART_TxFifoWatermark_TypeDef#

EUSART_TxFifoWatermark_TypeDef

TX FIFO Interrupt and Status Watermark.

Enumerator
eusartTxFiFoWatermark1Frame
eusartTxFiFoWatermark2Frame
eusartTxFiFoWatermark3Frame
eusartTxFiFoWatermark4Frame

Definition at line 354 of file platform/emlib/inc/em_eusart.h

Typedef Documentation#

EUSART_PrsChannel_TypeDef#

typedef uint8_t EUSART_PrsChannel_TypeDef

PRS Channel type.

Definition at line 299 of file platform/emlib/inc/em_eusart.h

Function Documentation#

EUSART_UartInitHf#

void EUSART_UartInitHf (EUSART_TypeDef * eusart, const EUSART_UartInit_TypeDef * init)

Initialize EUSART when used in UART mode with the high frequency clock.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	init	A pointer to the initialization structure.

Initialize EUSART when used in UART mode with the high frequency clock.

Definition at line 904 of file platform/emlib/inc/em_eusart.h

EUSART_UartInitLf#

void EUSART_UartInitLf (EUSART_TypeDef * eusart, const EUSART_UartInit_TypeDef * init)

Initialize EUSART when used in UART mode with the low frequency clock.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	init	A pointer to the initialization structure.

Initialize EUSART when used in UART mode with the low frequency clock.

Note

(1) When EUSART oversampling is set to eusartOVS0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate.

Definition at line 912 of file platform/emlib/inc/em_eusart.h

EUSART_IrDAInit#

void EUSART_IrDAInit (EUSART_TypeDef * eusart, const EUSART_IrDAInit_TypeDef * irdaInit)

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	irdaInit	A pointer to the initialization structure.

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

Definition at line 921 of file platform/emlib/inc/em_eusart.h

EUSART_Reset#

void EUSART_Reset (EUSART_TypeDef * eusart)

Configure EUSART to its reset state.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Configure EUSART to its reset state.

Definition at line 952 of file platform/emlib/inc/em_eusart.h

EUSART_Enable#

void EUSART_Enable (EUSART_TypeDef * eusart, EUSART_Enable_TypeDef enable)

Enable/disable EUSART receiver and/or transmitter.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	enable	Select the status for the receiver and transmitter.

Enable/disable EUSART receiver and/or transmitter.

Definition at line 960 of file platform/emlib/inc/em_eusart.h

EUSART_Rx#

uint8_t EUSART_Rx (EUSART_TypeDef * eusart)

Receive one 8 bit frame, (or part of 9 bit frame).

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Note

This function is normally used to receive one frame when operating with frame length of 8 bits. See EUSART_RxExt() for reception of 9 bit frames. Notice that possible parity/stop bits are not considered a part of the specified frame bit length.
This function will stall if buffer is empty until data is received.

Returns

Data received.

Receive one 8 bit frame, (or part of 9 bit frame).

Note

(1) Handles the case where the RX Fifo Watermark has been set to N frames, and when N is greater than one. Attempt to read a frame from the RX Fifo. If the read is unsuccessful (i.e. no frames in the RX fifo), the RXFU interrupt flag is set. If the flag is set, wait to read again until the RXFL status flag is set, indicating there are N frames in the RX Fifo, where N is equal to the RX watermark level. Once there are N frames in the Fifo, read and return one frame. For consecutive N-1 reads there will be data available in the Fifo. Therefore, the RXUF interrupt will not be triggered eliminating delays between reads and sending N data frames in "bursts".

Definition at line 975 of file platform/emlib/inc/em_eusart.h

EUSART_RxExt#

uint16_t EUSART_RxExt (EUSART_TypeDef * eusart)

Receive one 8-16 bit frame with extended information.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Note

This function is normally used to receive one frame and additional RX status information.
This function will stall if buffer is empty until data is received.

Returns

Data received and receive status.

Receive one 8-16 bit frame with extended information.

Definition at line 988 of file platform/emlib/inc/em_eusart.h

EUSART_Tx#

void EUSART_Tx (EUSART_TypeDef * eusart, uint8_t data)

Transmit one frame.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	data	Data to transmit.

Note

Depending on the frame length configuration, 8 (least significant) bits from data are transmitted. If the frame length is 9, 8 bits are transmitted from data. See EUSART_TxExt() for transmitting 9 bit frame with full control of all 9 bits.
This function will stall if the 4 frame FIFO is full, until the buffer becomes available.

Transmit one frame.

Definition at line 1003 of file platform/emlib/inc/em_eusart.h

EUSART_TxExt#

void EUSART_TxExt (EUSART_TypeDef * eusart, uint16_t data)

Transmit one 8-9 bit frame with extended control.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	data	Data to transmit.

Note

Possible parity/stop bits in asynchronous mode are not considered part of a specified frame bit length.
This function will stall if buffer is full until the buffer becomes available.

Transmit one 8-9 bit frame with extended control.

Definition at line 1016 of file platform/emlib/inc/em_eusart.h

EUSART_BaudrateSet#

void EUSART_BaudrateSet (EUSART_TypeDef * eusart, uint32_t refFreq, uint32_t baudrate)

Configure the baudrate (or as close as possible to a specified baudrate).

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	refFreq	The EUSART reference clock frequency in Hz that will be used. If set to 0, the currently configured peripheral clock is used.
N/A	baudrate	A baudrate to try to achieve.

Configure the baudrate (or as close as possible to a specified baudrate).

Note

(1) When the oversampling is disabled, the peripheral clock frequency must be at least three times higher than the chosen baud rate.

Definition at line 1072 of file platform/emlib/inc/em_eusart.h

EUSART_BaudrateGet#

uint32_t EUSART_BaudrateGet (EUSART_TypeDef * eusart)

Get the current baudrate.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Returns

The current baudrate.

Get the current baudrate.

Definition at line 1083 of file platform/emlib/inc/em_eusart.h

EUSART_RxBlock#

void EUSART_RxBlock (EUSART_TypeDef * eusart, EUSART_BlockRx_TypeDef enable)

Enable/Disable reception operation until the configured start frame is received.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	enable	Select the receiver blocking status.

Enable/Disable reception operation until the configured start frame is received.

Definition at line 1092 of file platform/emlib/inc/em_eusart.h

EUSART_TxTristateSet#

void EUSART_TxTristateSet (EUSART_TypeDef * eusart, EUSART_TristateTx_TypeDef enable)

Enable/Disable the tristating of the transmitter output.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	enable	Select the transmitter tristate status.

Enable/Disable the tristating of the transmitter output.

Definition at line 1101 of file platform/emlib/inc/em_eusart.h

EUSART_PrsTriggerEnable#

void EUSART_PrsTriggerEnable (EUSART_TypeDef * eusart, const EUSART_PrsTriggerInit_TypeDef * init)

Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	init	Pointer to the initialization structure.

Note

Initialize EUSART with EUSART_UartInitHf() or EUSART_UartInitLf() before enabling the PRS trigger.

Initialize the automatic enabling of transmissions and/or reception using the PRS as a trigger.

Definition at line 1114 of file platform/emlib/inc/em_eusart.h

EUSART_StatusGet#

uint32_t EUSART_StatusGet (EUSART_TypeDef * eusart)

Get EUSART STATUS register.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Returns

STATUS register value.

Definition at line 1124 of file platform/emlib/inc/em_eusart.h

EUSART_IntClear#

void EUSART_IntClear (EUSART_TypeDef * eusart, uint32_t flags)

Clear one or more pending EUSART interrupts.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Definition at line 1138 of file platform/emlib/inc/em_eusart.h

EUSART_IntDisable#

void EUSART_IntDisable (EUSART_TypeDef * eusart, uint32_t flags)

Disable one or more EUSART interrupts.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Definition at line 1152 of file platform/emlib/inc/em_eusart.h

EUSART_IntEnable#

void EUSART_IntEnable (EUSART_TypeDef * eusart, uint32_t flags)

Enable one or more EUSART interrupts.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Definition at line 1166 of file platform/emlib/inc/em_eusart.h

EUSART_IntGet#

uint32_t EUSART_IntGet (EUSART_TypeDef * eusart)

Get pending EUSART interrupt flags.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Returns

Pending EUSART interrupt sources.

Definition at line 1178 of file platform/emlib/inc/em_eusart.h

EUSART_IntGetEnabled#

uint32_t EUSART_IntGetEnabled (EUSART_TypeDef * eusart)

Get enabled and pending EUSART interrupt flags.

Parameters

N/A

eusart

Pointer to the EUSART peripheral register block.

Useful for handling more interrupt sources in the same interrupt handler.

Returns

Pending and enabled EUSART interrupt sources.

Definition at line 1191 of file platform/emlib/inc/em_eusart.h

EUSART_IntSet#

void EUSART_IntSet (EUSART_TypeDef * eusart, uint32_t flags)

Set one or more pending EUSART interrupts from SW.

Parameters

N/A	eusart	Pointer to the EUSART peripheral register block.
N/A	flags	Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

Definition at line 1212 of file platform/emlib/inc/em_eusart.h

Macro Definition Documentation#

EUSART0_FIFO_DEPTH#

#define EUSART0_FIFO_DEPTH

Value:

Define EUSART FIFO Depth information.

Definition at line 154 of file platform/emlib/inc/em_eusart.h

EUSART1_FIFO_DEPTH#

#define EUSART1_FIFO_DEPTH

Value:

EUSART0_FIFO_DEPTH

Definition at line 158 of file platform/emlib/inc/em_eusart.h

EUSART2_FIFO_DEPTH#

#define EUSART2_FIFO_DEPTH

Value:

EUSART0_FIFO_DEPTH

Definition at line 159 of file platform/emlib/inc/em_eusart.h

EUSART3_FIFO_DEPTH#

#define EUSART3_FIFO_DEPTH

Value:

EUSART0_FIFO_DEPTH

Definition at line 160 of file platform/emlib/inc/em_eusart.h

EUSART4_FIFO_DEPTH#

#define EUSART4_FIFO_DEPTH

Value:

EUSART0_FIFO_DEPTH

Definition at line 161 of file platform/emlib/inc/em_eusart.h

EUSART_FIFO_DEPTH#

#define EUSART_FIFO_DEPTH

Value:

(((n) == 0) ? EUSART0_FIFO_DEPTH \

: ((n) == 1) ? EUSART1_FIFO_DEPTH \

: ((n) == 2) ? EUSART2_FIFO_DEPTH \

: ((n) == 3) ? EUSART3_FIFO_DEPTH \

: ((n) == 4) ? EUSART4_FIFO_DEPTH \

: 0x0UL)

Definition at line 163 of file platform/emlib/inc/em_eusart.h

EUSART_UART_INIT_DEFAULT_HF#

#define EUSART_UART_INIT_DEFAULT_HF

Value:

{ \

eusartEnable, /* Enable RX/TX when initialization completed. */ \

0, /* Use current configured reference clock for configuring baud rate.*/ \

115200, /* 115200 bits/s. */ \

eusartOVS16, /* Oversampling x16. */ \

eusartDataBits8, /* 8 data bits. */ \

eusartNoParity, /* No parity. */ \

eusartStopbits1, /* 1 stop bit. */ \

eusartMajorityVoteEnable, /* Majority vote enabled. */ \

eusartLoopbackDisable, /* Loop back disabled. */ \

NULL, /* Default advanced settings. */ \

}

Default configuration for EUSART initialization structure in UART mode with high-frequency clock.

Definition at line 687 of file platform/emlib/inc/em_eusart.h

EUSART_DEFAULT_START_FRAME#

#define EUSART_DEFAULT_START_FRAME

Value:

0x00u

Default start frame configuration, i.e. feature disabled.

Definition at line 702 of file platform/emlib/inc/em_eusart.h

EUSART_ADVANCED_INIT_DEFAULT#

#define EUSART_ADVANCED_INIT_DEFAULT

Value:

{ \

eusartHwFlowControlNone, /* Flow control disabled. */ \

false, /* Collision detection disabled. */ \

false, /* Data is sent with the least significant bit first. */ \

eusartInvertIODisable, /* RX and TX signal active high. */ \

false, /* No DMA wake up on reception. */ \

false, /* No DMA wake up on transmission. */ \

false, /* Halt DMA on error disabled. */ \

EUSART_DEFAULT_START_FRAME, /* No start frame. */ \

false, /* TX auto tristate disabled. */ \

false, /* Do not use PRS signal as RX signal.*/ \

(EUSART_PrsChannel_TypeDef) 0u, /* EUSART RX connected to prs channel 0. */ \

false, /* Multiprocessor mode disabled. */ \

false, /* Multiprocessor address bit : 0.*/ \

eusartAutoTxDelayNone, /* Frames are transmitted immediately */ \

eusartRxFiFoWatermark1Frame, /* RXFL status/IF set when RX FIFO has at least one frame in it */ \

eusartTxFiFoWatermark1Frame, /* TXFL status/IF set when TX FIFO has space for at least one more frame */ \

}

Default configuration for EUSART advanced initialization structure.

Definition at line 705 of file platform/emlib/inc/em_eusart.h

EUSART_UART_INIT_DEFAULT_LF#

#define EUSART_UART_INIT_DEFAULT_LF

Value:

{ \

eusartEnable, /* Enable RX/TX when initialization completed. */ \

0, /* Use current configured reference clock for configuring baud rate.*/ \

9600, /* 9600 bits/s. */ \

eusartOVS0, /* Oversampling disabled. */ \

eusartDataBits8, /* 8 data bits. */ \

eusartNoParity, /* No parity. */ \

eusartStopbits1, /* 1 stop bit. */ \

eusartMajorityVoteDisable, /* Majority vote enabled. */ \

eusartLoopbackDisable, /* Loop back disabled. */ \

NULL, /* Default advanced settings. */ \

}

Default configuration for EUSART initialization structure in UART mode with low-frequency clock.

Definition at line 726 of file platform/emlib/inc/em_eusart.h

EUSART_IRDA_INIT_DEFAULT_HF#

#define EUSART_IRDA_INIT_DEFAULT_HF

Value:

{ \

EUSART_UART_INIT_DEFAULT_HF, /* Default high frequency configuration. */ \

false, /* Disable IrDA low frequency mode. */ \

eusartIrDARxFilterDisable, /* RX Filter disabled. */ \

eusartIrDAPulseWidthOne, /* Pulse width is set to 1/16. */ \

}

Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.

Definition at line 741 of file platform/emlib/inc/em_eusart.h

EUSART_IRDA_INIT_DEFAULT_LF#

#define EUSART_IRDA_INIT_DEFAULT_LF

Value:

{ \

eusartEnableRx, /* Enable RX when initialization completed (TX not allowed). */ \

0, /* Use current configured reference clock for configuring baud rate.*/ \

9600, /* 9600 bits/s. */ \

eusartOVS0, /* Oversampling disabled. */ \

eusartDataBits8, /* 8 data bits. */ \

eusartNoParity, /* No parity. */ \

eusartStopbits1, /* 1 stop bit. */ \

eusartMajorityVoteDisable, /* Majority vote enabled. */ \

eusartLoopbackDisable, /* Loop back disabled. */ \

NULL, /* Default advanced settings. */ \

}, \

true, /* Enable IrDA low frequency mode. */ \

eusartIrDARxFilterDisable, /* RX Filter disabled. */ \

eusartIrDAPulseWidthOne, /* Pulse width is set to 1. */ \

}

Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

Definition at line 750 of file platform/emlib/inc/em_eusart.h