VDAC initialization structure, common for both channels.

Public Attributes#

uint32_t

Number of prescaled CLK_DAC + 1 for the vdac to warmup.

bool

Halt during debug.

bool

Always allow clk_dac.

bool

DMA Wakeup.

bool

Bias keep warm enable.

Channel refresh period.

Internal timer overflow period.

uint32_t

Prescaler for VDAC clock.

Reference voltage to use.

bool

Enable/disable reset of prescaler on CH 0 start.

bool

Sine reset mode.

bool

Enable/disable sine mode.

bool

Select if single ended or differential output mode.

Public Attribute Documentation#

warmupTime#

uint32_t VDAC_Init_TypeDef::warmupTime

Number of prescaled CLK_DAC + 1 for the vdac to warmup.


dbgHalt#

bool VDAC_Init_TypeDef::dbgHalt

Halt during debug.


onDemandClk#

bool VDAC_Init_TypeDef::onDemandClk

Always allow clk_dac.


dmaWakeUp#

bool VDAC_Init_TypeDef::dmaWakeUp

DMA Wakeup.


biasKeepWarm#

bool VDAC_Init_TypeDef::biasKeepWarm

Bias keep warm enable.


refresh#

VDAC_Refresh_TypeDef VDAC_Init_TypeDef::refresh

Channel refresh period.


timerOverflow#

VDAC_TimerOverflow_TypeDef VDAC_Init_TypeDef::timerOverflow

Internal timer overflow period.


prescaler#

uint32_t VDAC_Init_TypeDef::prescaler

Prescaler for VDAC clock.

Clock is source clock divided by prescaler+1.


reference#

VDAC_Ref_TypeDef VDAC_Init_TypeDef::reference

Reference voltage to use.


ch0ResetPre#

bool VDAC_Init_TypeDef::ch0ResetPre

Enable/disable reset of prescaler on CH 0 start.


sineReset#

bool VDAC_Init_TypeDef::sineReset

Sine reset mode.


sineEnable#

bool VDAC_Init_TypeDef::sineEnable

Enable/disable sine mode.


diff#

bool VDAC_Init_TypeDef::diff

Select if single ended or differential output mode.