enable#

bool WDOG_Init_TypeDef::enable

Enable Watchdog when initialization completed.

debugRun#

bool WDOG_Init_TypeDef::debugRun

Counter keeps running during debug halt.

clrSrc#

bool WDOG_Init_TypeDef::clrSrc

Select WDOG clear source: False: Write to the clear bit will clear the WDOG counter True: Rising edge on the PRS Source 0 will clear the WDOG counter.

em1Run#

bool WDOG_Init_TypeDef::em1Run

Counter keeps running when in EM1.

Available for series2.

em2Run#

bool WDOG_Init_TypeDef::em2Run

Counter keeps running when in EM2.

em3Run#

bool WDOG_Init_TypeDef::em3Run

Counter keeps running when in EM3.

em4Block#

bool WDOG_Init_TypeDef::em4Block

Block EMU from entering EM4.

prs0MissRstEn#

bool WDOG_Init_TypeDef::prs0MissRstEn

When set, a PRS Source 0 missing event will trigger a WDOG reset.

prs1MissRstEn#

bool WDOG_Init_TypeDef::prs1MissRstEn

When set, a PRS Source 1 missing event will trigger a WDOG reset.

lock#

bool WDOG_Init_TypeDef::lock

Block SW from disabling LFRCO/LFXO oscillators.

Block SW from modifying the configuration (a reset is needed to reconfigure).

perSel#

WDOG_PeriodSel_TypeDef WDOG_Init_TypeDef::perSel

Clock source to use for Watchdog.

Watchdog timeout period.

warnSel#

WDOG_WarnSel_TypeDef WDOG_Init_TypeDef::warnSel

Select warning time as % of the Watchdog timeout.

winSel#

WDOG_WinSel_TypeDef WDOG_Init_TypeDef::winSel

Select illegal window time as % of the Watchdog timeout.

resetDisable#

bool WDOG_Init_TypeDef::resetDisable

Disable Watchdog reset output if true.