CMU - Clock Management Unit#

Clock management unit (CMU) Peripheral API.

This module contains functions for the CMU peripheral of Silicon Labs 32-bit MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock multiplexers, pre-scalers, calibration modules and wait-states.

Modules#

CMU_LFXOInit_TypeDef

CMU_HFXOInit_TypeDef

CMU_BUFOUTLeaderInit_TypeDef

CMU_CrystalSharingFollowerInit_TypeDef

CMU_DPLLInit_TypeDef

CMU_USBPLL_Init_TypeDef

CMU_RFFPLL_Init_TypeDef

Enumerations#

enum
cmuHFRCODPLLFreq_1M0Hz = 1000000U
cmuHFRCODPLLFreq_2M0Hz = 2000000U
cmuHFRCODPLLFreq_4M0Hz = 4000000U
cmuHFRCODPLLFreq_7M0Hz = 7000000U
cmuHFRCODPLLFreq_13M0Hz = 13000000U
cmuHFRCODPLLFreq_16M0Hz = 16000000U
cmuHFRCODPLLFreq_19M0Hz = 19000000U
cmuHFRCODPLLFreq_26M0Hz = 26000000U
cmuHFRCODPLLFreq_32M0Hz = 32000000U
cmuHFRCODPLLFreq_38M0Hz = 38000000U
cmuHFRCODPLLFreq_48M0Hz = 48000000U
cmuHFRCODPLLFreq_56M0Hz = 56000000U
cmuHFRCODPLLFreq_64M0Hz = 64000000U
cmuHFRCODPLLFreq_80M0Hz = 80000000U
cmuHFRCODPLLFreq_100M0Hz = 100000000U
cmuHFRCODPLLFreq_UserDefined = 0
}

HFRCODPLL frequency bands.

enum
cmuHFXORefFreq_38M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) | (24UL << _USBPLL_CTRL_DIVX_SHIFT) | (19UL << _USBPLL_CTRL_DIVN_SHIFT)
cmuHFXORefFreq_38M4Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) | (25UL << _USBPLL_CTRL_DIVX_SHIFT) | (20UL << _USBPLL_CTRL_DIVN_SHIFT)
cmuHFXORefFreq_39M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) | (16UL << _USBPLL_CTRL_DIVX_SHIFT) | (13UL << _USBPLL_CTRL_DIVN_SHIFT)
cmuHFXORefFreq_40M0Hz = (1UL << _USBPLL_CTRL_DIVR_SHIFT) | (24UL << _USBPLL_CTRL_DIVX_SHIFT) | (20UL << _USBPLL_CTRL_DIVN_SHIFT)
}

HFXO reference frequency.

enum
cmuHFRCOEM23Freq_1M0Hz = 1000000U
cmuHFRCOEM23Freq_2M0Hz = 2000000U
cmuHFRCOEM23Freq_4M0Hz = 4000000U
cmuHFRCOEM23Freq_13M0Hz = 13000000U
cmuHFRCOEM23Freq_16M0Hz = 16000000U
cmuHFRCOEM23Freq_19M0Hz = 19000000U
cmuHFRCOEM23Freq_26M0Hz = 26000000U
cmuHFRCOEM23Freq_32M0Hz = 32000000U
cmuHFRCOEM23Freq_40M0Hz = 40000000U
cmuHFRCOEM23Freq_UserDefined = 0
}

HFRCOEM23 frequency bands.

enum
cmuClock_SYSCLK = (CMU_SYSCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_SYSTICK = (CMU_SYSTICK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_HCLK = (CMU_HCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EXPCLK = (CMU_EXPCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_PCLK = (CMU_PCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LSPCLK = (CMU_LSPCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_TRACECLK = (CMU_TRACECLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EM01GRPACLK = (CMU_EM01GRPACLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EM01GRPCCLK = (CMU_EM01GRPCCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EUSART0CLK = (CMU_EUART0CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_IADCCLK = (CMU_IADCCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EM23GRPACLK = (CMU_EM23GRPACLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_WDOG0CLK = (CMU_WDOG0CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_WDOG1CLK = (CMU_WDOG1CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_SYSRTCCLK = (CMU_SYSRTCCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EM4GRPACLK = (CMU_EM4GRPACLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_DPLLREFCLK = (CMU_DPLLREFCLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_VDAC0CLK = (CMU_VDAC0_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_PCNT0CLK = (CMU_PCNT_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LESENSEHFCLK = (CMU_LESENSEHF_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LESENSECLK = (CMU_LESENSE_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CORE = (CMU_CORE_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LDMA = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS)
cmuClock_LDMAXBAR = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LDMAXBAR_SHIFT << CMU_EN_BIT_POS)
cmuClock_RADIOAES = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_RADIOAES_SHIFT << CMU_EN_BIT_POS)
cmuClock_GPCRC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER2 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER2_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER3 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER3_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER4 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER4_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER5 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_TIMER5_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER6 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_TIMER6_SHIFT << CMU_EN_BIT_POS)
cmuClock_TIMER7 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_TIMER7_SHIFT << CMU_EN_BIT_POS)
cmuClock_IADC0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_IADC0_SHIFT << CMU_EN_BIT_POS)
cmuClock_AMUXCP0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_AMUXCP0_SHIFT << CMU_EN_BIT_POS)
cmuClock_LETIMER0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS)
cmuClock_WDOG0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_WDOG0_SHIFT << CMU_EN_BIT_POS)
cmuClock_WDOG1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_WDOG1_SHIFT << CMU_EN_BIT_POS)
cmuClock_I2C0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS)
cmuClock_I2C1 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS)
cmuClock_SYSCFG = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_SYSCFG_SHIFT << CMU_EN_BIT_POS)
cmuClock_DPLL0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_DPLL0_SHIFT << CMU_EN_BIT_POS)
cmuClock_HFRCO0 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_HFRCO0_SHIFT << CMU_EN_BIT_POS)
cmuClock_HFRCOEM23 = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_HFRCOEM23_SHIFT << CMU_EN_BIT_POS)
cmuClock_HFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_HFXO0_SHIFT << CMU_EN_BIT_POS)
cmuClock_FSRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_FSRCO_SHIFT << CMU_EN_BIT_POS)
cmuClock_LFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LFRCO_SHIFT << CMU_EN_BIT_POS)
cmuClock_LFXO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LFXO_SHIFT << CMU_EN_BIT_POS)
cmuClock_ULFRCO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_ULFRCO_SHIFT << CMU_EN_BIT_POS)
cmuClock_GPIO = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS)
cmuClock_PRS = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_PRS_SHIFT << CMU_EN_BIT_POS)
cmuClock_BURAM = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_BURAM_SHIFT << CMU_EN_BIT_POS)
cmuClock_BURTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_BURTC_SHIFT << CMU_EN_BIT_POS)
cmuClock_DCDC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_DCDC_SHIFT << CMU_EN_BIT_POS)
cmuClock_SYSRTC = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_SYSRTC0_SHIFT << CMU_EN_BIT_POS)
cmuClock_EUSART0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_EUSART0_SHIFT << CMU_EN_BIT_POS)
cmuClock_EUSART1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_EUSART1_SHIFT << CMU_EN_BIT_POS)
cmuClock_EUSART2 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_EUSART2_SHIFT << CMU_EN_BIT_POS)
cmuClock_EUSART3 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_EUSART3_SHIFT << CMU_EN_BIT_POS)
cmuClock_EUSART4 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_EUSART4_SHIFT << CMU_EN_BIT_POS)
cmuClock_SEMAILBOX = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_SEMAILBOXHOST_SHIFT << CMU_EN_BIT_POS)
cmuClock_SMU = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_SMU_SHIFT << CMU_EN_BIT_POS)
cmuClock_ICACHE = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_ICACHE0_SHIFT << CMU_EN_BIT_POS)
cmuClock_LESENSE = (CMU_CLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS)
cmuClock_ACMP0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_ACMP0_SHIFT << CMU_EN_BIT_POS)
cmuClock_ACMP1 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_ACMP1_SHIFT << CMU_EN_BIT_POS)
cmuClock_VDAC0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_VDAC0_SHIFT << CMU_EN_BIT_POS)
cmuClock_PCNT0 = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_PCNT0_SHIFT << CMU_EN_BIT_POS)
cmuClock_DMEM = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_DMEM_SHIFT << CMU_EN_BIT_POS)
cmuClock_MSC = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_MSC_SHIFT << CMU_EN_BIT_POS)
cmuClock_USB = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_USB_SHIFT << CMU_EN_BIT_POS)
cmuClock_ETAMPDET = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_ETAMPDET_SHIFT << CMU_EN_BIT_POS)
cmuClock_RFFPLL = (CMU_CLKEN1_EN_REG << CMU_EN_REG_POS) | (_CMU_CLKEN1_RFFPLL0_SHIFT << CMU_EN_BIT_POS)
}

Clock points in CMU clock-tree.

enum
cmuOsc_LFXO
cmuOsc_LFRCO
cmuOsc_FSRCO
cmuOsc_HFXO
cmuOsc_HFRCODPLL
cmuOsc_HFRCOEM23
cmuOsc_ULFRCO
}

Oscillator types.

enum
cmuSelect_Error
cmuSelect_Disabled
cmuSelect_FSRCO
cmuSelect_HFXO
cmuSelect_HFXORT
cmuSelect_HFRCODPLL
cmuSelect_HFRCODPLLRT
cmuSelect_HFRCOEM23
cmuSelect_CLKIN0
cmuSelect_LFXO
cmuSelect_LFRCO
cmuSelect_ULFRCO
cmuSelect_HCLK
cmuSelect_SYSCLK
cmuSelect_HCLKDIV1024
cmuSelect_EM01GRPACLK
cmuSelect_EM23GRPACLK
cmuSelect_EM01GRPCCLK
cmuSelect_EXPCLK
cmuSelect_PRS
cmuSelect_PCNTEXTCLK
cmuSelect_TEMPOSC
cmuSelect_PFMOSC
cmuSelect_BIASOSC
cmuSelect_USBPLL0
cmuSelect_RFFPLLSYS
}

Selectable clock sources.

enum
cmuDPLLEdgeSel_Fall = 0
cmuDPLLEdgeSel_Rise = 1
}

DPLL reference clock edge detect selector.

enum
cmuDPLLLockMode_Freq = _DPLL_CFG_MODE_FLL
cmuDPLLLockMode_Phase = _DPLL_CFG_MODE_PLL
}

DPLL lock mode selector.

enum
cmuLfxoOscMode_Crystal = _LFXO_CFG_MODE_XTAL
cmuLfxoOscMode_AcCoupledSine = _LFXO_CFG_MODE_BUFEXTCLK
cmuLfxoOscMode_External = _LFXO_CFG_MODE_DIGEXTCLK
}

LFXO oscillator modes.

enum
cmuLfxoStartupDelay_2Cycles = _LFXO_CFG_TIMEOUT_CYCLES2
cmuLfxoStartupDelay_256Cycles = _LFXO_CFG_TIMEOUT_CYCLES256
cmuLfxoStartupDelay_1KCycles = _LFXO_CFG_TIMEOUT_CYCLES1K
cmuLfxoStartupDelay_2KCycles = _LFXO_CFG_TIMEOUT_CYCLES2K
cmuLfxoStartupDelay_4KCycles = _LFXO_CFG_TIMEOUT_CYCLES4K
cmuLfxoStartupDelay_8KCycles = _LFXO_CFG_TIMEOUT_CYCLES8K
cmuLfxoStartupDelay_16KCycles = _LFXO_CFG_TIMEOUT_CYCLES16K
cmuLfxoStartupDelay_32KCycles = _LFXO_CFG_TIMEOUT_CYCLES32K
}

LFXO start-up timeout delay.

enum
cmuHfxoOscMode_Crystal = _HFXO_CFG_MODE_XTAL
cmuHfxoOscMode_ExternalSine = _HFXO_CFG_MODE_EXTCLK
cmuHfxoOscMode_ExternalSinePkDet = _HFXO_CFG_MODE_EXTCLKPKDET
}

HFXO oscillator modes.

enum
cmuHfxoCbLsbTimeout_8us = _HFXO_XTALCFG_TIMEOUTCBLSB_T8US
cmuHfxoCbLsbTimeout_20us = _HFXO_XTALCFG_TIMEOUTCBLSB_T20US
cmuHfxoCbLsbTimeout_41us = _HFXO_XTALCFG_TIMEOUTCBLSB_T41US
cmuHfxoCbLsbTimeout_62us = _HFXO_XTALCFG_TIMEOUTCBLSB_T62US
cmuHfxoCbLsbTimeout_83us = _HFXO_XTALCFG_TIMEOUTCBLSB_T83US
cmuHfxoCbLsbTimeout_104us = _HFXO_XTALCFG_TIMEOUTCBLSB_T104US
cmuHfxoCbLsbTimeout_125us = _HFXO_XTALCFG_TIMEOUTCBLSB_T125US
cmuHfxoCbLsbTimeout_166us = _HFXO_XTALCFG_TIMEOUTCBLSB_T166US
cmuHfxoCbLsbTimeout_208us = _HFXO_XTALCFG_TIMEOUTCBLSB_T208US
cmuHfxoCbLsbTimeout_250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T250US
cmuHfxoCbLsbTimeout_333us = _HFXO_XTALCFG_TIMEOUTCBLSB_T333US
cmuHfxoCbLsbTimeout_416us = _HFXO_XTALCFG_TIMEOUTCBLSB_T416US
cmuHfxoCbLsbTimeout_833us = _HFXO_XTALCFG_TIMEOUTCBLSB_T833US
cmuHfxoCbLsbTimeout_1250us = _HFXO_XTALCFG_TIMEOUTCBLSB_T1250US
cmuHfxoCbLsbTimeout_2083us = _HFXO_XTALCFG_TIMEOUTCBLSB_T2083US
cmuHfxoCbLsbTimeout_3750us = _HFXO_XTALCFG_TIMEOUTCBLSB_T3750US
}

HFXO core bias LSB change timeout.

enum
cmuHfxoSteadyStateTimeout_16us = _HFXO_XTALCFG_TIMEOUTSTEADY_T16US
cmuHfxoSteadyStateTimeout_41us = _HFXO_XTALCFG_TIMEOUTSTEADY_T41US
cmuHfxoSteadyStateTimeout_83us = _HFXO_XTALCFG_TIMEOUTSTEADY_T83US
cmuHfxoSteadyStateTimeout_125us = _HFXO_XTALCFG_TIMEOUTSTEADY_T125US
cmuHfxoSteadyStateTimeout_166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T166US
cmuHfxoSteadyStateTimeout_208us = _HFXO_XTALCFG_TIMEOUTSTEADY_T208US
cmuHfxoSteadyStateTimeout_250us = _HFXO_XTALCFG_TIMEOUTSTEADY_T250US
cmuHfxoSteadyStateTimeout_333us = _HFXO_XTALCFG_TIMEOUTSTEADY_T333US
cmuHfxoSteadyStateTimeout_416us = _HFXO_XTALCFG_TIMEOUTSTEADY_T416US
cmuHfxoSteadyStateTimeout_500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T500US
cmuHfxoSteadyStateTimeout_666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T666US
cmuHfxoSteadyStateTimeout_833us = _HFXO_XTALCFG_TIMEOUTSTEADY_T833US
cmuHfxoSteadyStateTimeout_1666us = _HFXO_XTALCFG_TIMEOUTSTEADY_T1666US
cmuHfxoSteadyStateTimeout_2500us = _HFXO_XTALCFG_TIMEOUTSTEADY_T2500US
cmuHfxoSteadyStateTimeout_4166us = _HFXO_XTALCFG_TIMEOUTSTEADY_T4166US
}

HFXO steady state timeout.

enum
cmuHfxoCoreDegen_None = _HFXO_XTALCTRL_COREDGENANA_NONE
cmuHfxoCoreDegen_33 = _HFXO_XTALCTRL_COREDGENANA_DGEN33
cmuHfxoCoreDegen_50 = _HFXO_XTALCTRL_COREDGENANA_DGEN50
cmuHfxoCoreDegen_100 = _HFXO_XTALCTRL_COREDGENANA_DGEN100
}

HFXO core degeneration control.

enum
cmuHfxoCtuneFixCap_None = _HFXO_XTALCTRL_CTUNEFIXANA_NONE
cmuHfxoCtuneFixCap_Xi = _HFXO_XTALCTRL_CTUNEFIXANA_XI
cmuHfxoCtuneFixCap_Xo = _HFXO_XTALCTRL_CTUNEFIXANA_XO
cmuHfxoCtuneFixCap_Both = _HFXO_XTALCTRL_CTUNEFIXANA_BOTH
}

HFXO XI and XO pin fixed capacitor control.

enum
cmuPrecisionDefault
cmuPrecisionHigh
}

Oscillator precision modes.

enum
startupTimeout42Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T42US
startupTimeout83Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T83US
startupTimeout108Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T108US
startupTimeout133Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T133US
startupTimeout158Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T158US
startupTimeout183Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T183US
startupTimeout208Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T208US
startupTimeout233Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T233US
startupTimeout258Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T258US
startupTimeout283Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T283US
startupTimeout333Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T333US
startupTimeout375Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T375US
startupTimeout417Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T417US
startupTimeout458Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T458US
startupTimeout500Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T500US
startupTimeout667Us = _HFXO_BUFOUTCTRL_TIMEOUTSTARTUP_T667US
}

Crystal sharing timeout start up timeout.

enum
PRS_Status_select_0
PRS_Status_select_1
}

PRS status select output signal.

Typedefs#

typedef uint32_t

Clock divider configuration.

Functions#

uint32_t
CMU_Calibrate(uint32_t cycles, CMU_Select_TypeDef ref)

Calibrate an oscillator.

void
CMU_CalibrateConfig(uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel)

Configure clock calibration.

uint32_t

Get calibration count value.

void
CMU_ClkOutPinConfig(uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin)

Direct a clock to a GPIO pin.

CMU_ClockDivGet(CMU_Clock_TypeDef clock)

Get clock divisor.

void
CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set clock divisor.

void
CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

uint32_t
CMU_ClockFreqGet(CMU_Clock_TypeDef clock)

Get clock frequency for a clock point.

CMU_ClockSelectGet(CMU_Clock_TypeDef clock)

Get currently selected reference clock used for a clock branch.

void
CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select reference clock/oscillator used for a clock branch.

uint16_t
CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

uint16_t
CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

Get HFRCODPLL band in use.

void
CMU_HFRCODPLLBandSet(CMU_HFRCODPLLFreq_TypeDef freq)

Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.

bool
CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init)

Lock the DPLL to a given frequency.

void
CMU_USBPLLInit(const CMU_USBPLL_Init_TypeDef *pllInit)

Initialize the USB PLL control registers.

void

Wait for USB PLL lock and ready.

void
CMU_RFFPLLInit(const CMU_RFFPLL_Init_TypeDef *pllInit)

Initialize the RFFPLL control registers.

void

Wait for RFF PLL lock and ready.

void
CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)

Initialize all HFXO control registers.

void
CMU_HFXOStartCrystalSharingLeader(const CMU_BUFOUTLeaderInit_TypeDef *bufoutInit, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) leader control registers.

void
CMU_HFXOCrystalSharingFollowerInit(CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, unsigned int prsAsyncCh, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) follower control registers.

sl_status_t
CMU_HFXOCTuneSet(uint32_t ctune)

Set the HFXO crystal tuning capacitance.

uint32_t

Get the HFXO crystal tuning capacitance.

void
CMU_HFXOCTuneDeltaSet(int32_t delta)

Set the HFXO crystal tuning delta.

int32_t

Get the HFXO crystal tuning delta.

void

Recalibrate the HFXO's Core Bias Current.

void
CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)

Initialize LFXO control registers.

void
CMU_LFXOPrecisionSet(uint16_t precision)

Sets LFXO's crystal precision, in PPM.

uint16_t

Gets LFXO's crystal precision, in PPM.

void
CMU_HFXOPrecisionSet(uint16_t precision)

Sets HFXO's crystal precision, in PPM.

uint16_t

Gets HFXO's crystal precision, in PPM.

uint32_t
CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)

Get oscillator frequency tuning setting.

void
CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

void
CMU_UpdateWaitStates(uint32_t freq, int vscale)

Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.

void
CMU_PCNTClockExternalSet(unsigned int instance, bool external)

Select the PCNTn clock.

Get HFRCOEM23 band in use.

void
CMU_HFRCOEM23BandSet(CMU_HFRCOEM23Freq_TypeDef freq)

Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.

void
CMU_CalibrateCont(bool enable)

Configure continuous calibration mode.

void

Start calibration.

void

Stop calibration counters.

void

Unlock the DPLL.

void
CMU_IntClear(uint32_t flags)

Clear one or more pending CMU interrupt flags.

void
CMU_IntDisable(uint32_t flags)

Disable one or more CMU interrupt sources.

void
CMU_IntEnable(uint32_t flags)

Enable one or more CMU interrupt sources.

uint32_t

Get pending CMU interrupt sources.

uint32_t

Get enabled and pending CMU interrupt flags.

void
CMU_IntSet(uint32_t flags)

Set one or more pending CMU interrupt sources.

void
CMU_Lock(void)

Lock CMU register access in order to protect registers contents against unintended modification.

void
CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

void

Unlock CMU register access so that writing to registers is possible.

void

Lock WDOG register access in order to protect registers contents against unintended modification.

void

Unlock WDOG register access so that writing to registers is possible.

uint32_t
CMU_PrescToLog2(uint32_t presc)

Convert prescaler divider to a logarithmic value.

Macros#

#define

Macro to set clock sources in the clock tree.

#define

Disable clocks configuration.

#define
CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM01GRPACLKCTRL.

#define

Mode DISABLED for CMU_EM01GRPBCLKCTRL

#define
CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED (_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL.

#define

Mode DISABLED for CMU_EM23GRPACLKCTRL

#define
CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM23GRPACLKCTRL.

#define

Mode DISABLED for CMU_EM4GRPACLKCTRL

#define
CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED (_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM4GRPACLKCTRL.

#define

Mode DISABLED for CMU_WDOG0CLKCTRL

#define
CMU_WDOG0CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG0CLKCTRL

#define

Mode DISABLED for CMU_WDOG1CLKCTRL

#define
CMU_WDOG1CLKCTRL_CLKSEL_DISABLED (_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG1CLKCTRL

#define

Mode DISABLED for CMU_EUSART0CLKCTRL

#define
CMU_EUSART0CLKCTRL_CLKSEL_DISABLED (_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EUSART0CLKCTRL.

#define

Mode DISABLED for CMU_SYSRTC0CLKCTRL

#define
CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED (_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL.

#define
CMU_HFRCODPLL_MIN cmuHFRCODPLLFreq_1M0Hz

HFRCODPLL maximum frequency.

#define
CMU_HFRCODPLL_MAX cmuHFRCODPLLFreq_80M0Hz

HFRCODPLL minimum frequency.

#define
CMU_HFRCOEM23_MIN cmuHFRCOEM23Freq_1M0Hz

HFRCOEM23 maximum frequency.

#define
CMU_HFRCOEM23_MAX cmuHFRCOEM23Freq_40M0Hz

HFRCOEM23 minimum frequency.

#define

Default LFXO initialization values for XTAL mode.

#define

Default LFXO initialization values for external clock mode.

#define

Default LFXO initialization values for external sine mode.

#define
CMU_HFXOINIT_CTUNEFIXANA_DEFAULT cmuHfxoCtuneFixCap_Xo

Default configuration of fixed tuning capacitance on XO for EFR32XG25.

#define

Default HFXO initialization values for XTAL mode.

#define

Default HFXO initialization values for external sine mode.

#define

Default HFXO initialization values for external sine mode with peak detector.

#define

Default crystal sharing master initialization values.

#define

Default crystal sharing follower initialization values.

#define

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

#define

DPLL initialization values for 76,800,000 Hz using HFXO as reference clock, M = 1919, N = 3839.

#define

DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.

#define

Default configurations for DPLL initialization.

#define

Default configurations for USB PLL initialization if the HFXO frequency is 38 MHz.

#define

Default configurations for USB PLL initialization if the HFXO frequency is 38.4 MHz.

#define

Default configurations for USB PLL initialization if the HFXO frequency is 39 MHz.

#define

Default configurations for USB PLL initialization if the HFXO frequency is 40 MHz.

#define

Radio frequency locked loop default initialization values.

#define

Radio frequency locked loop initialization values for 97.5MHz.

Enumeration Documentation#

CMU_HFRCODPLLFreq_TypeDef#

CMU_HFRCODPLLFreq_TypeDef

HFRCODPLL frequency bands.

Enumerator
cmuHFRCODPLLFreq_1M0Hz

1MHz RC band.

cmuHFRCODPLLFreq_2M0Hz

2MHz RC band.

cmuHFRCODPLLFreq_4M0Hz

4MHz RC band.

cmuHFRCODPLLFreq_7M0Hz

7MHz RC band.

cmuHFRCODPLLFreq_13M0Hz

13MHz RC band.

cmuHFRCODPLLFreq_16M0Hz

16MHz RC band.

cmuHFRCODPLLFreq_19M0Hz

19MHz RC band.

cmuHFRCODPLLFreq_26M0Hz

26MHz RC band.

cmuHFRCODPLLFreq_32M0Hz

32MHz RC band.

cmuHFRCODPLLFreq_38M0Hz

38MHz RC band.

cmuHFRCODPLLFreq_48M0Hz

48MHz RC band.

cmuHFRCODPLLFreq_56M0Hz

56MHz RC band.

cmuHFRCODPLLFreq_64M0Hz

64MHz RC band.

cmuHFRCODPLLFreq_80M0Hz

80MHz RC band.

cmuHFRCODPLLFreq_100M0Hz

100MHz RC band.

cmuHFRCODPLLFreq_UserDefined

Definition at line 175 of file platform/emlib/inc/em_cmu.h

CMU_HFXORefFreq_TypeDef#

CMU_HFXORefFreq_TypeDef

HFXO reference frequency.

Enumerator
cmuHFXORefFreq_38M0Hz

38MHz input frequency.

cmuHFXORefFreq_38M4Hz

38.4MHz input frequency.

cmuHFXORefFreq_39M0Hz

39MHz input frequency.

cmuHFXORefFreq_40M0Hz

40MHz input frequency.


Definition at line 198 of file platform/emlib/inc/em_cmu.h

CMU_HFRCOEM23Freq_TypeDef#

CMU_HFRCOEM23Freq_TypeDef

HFRCOEM23 frequency bands.

Enumerator
cmuHFRCOEM23Freq_1M0Hz

1MHz RC band.

cmuHFRCOEM23Freq_2M0Hz

2MHz RC band.

cmuHFRCOEM23Freq_4M0Hz

4MHz RC band.

cmuHFRCOEM23Freq_13M0Hz

13MHz RC band.

cmuHFRCOEM23Freq_16M0Hz

16MHz RC band.

cmuHFRCOEM23Freq_19M0Hz

19MHz RC band.

cmuHFRCOEM23Freq_26M0Hz

26MHz RC band.

cmuHFRCOEM23Freq_32M0Hz

32MHz RC band.

cmuHFRCOEM23Freq_40M0Hz

40MHz RC band.

cmuHFRCOEM23Freq_UserDefined

Definition at line 221 of file platform/emlib/inc/em_cmu.h

CMU_Clock_TypeDef#

CMU_Clock_TypeDef

Clock points in CMU clock-tree.

Enumerator
cmuClock_SYSCLK

SYSTEM clock.

cmuClock_SYSTICK

SYSTICK clock.

cmuClock_HCLK

Core and AHB bus interface clock.

cmuClock_EXPCLK

Export clock.

cmuClock_PCLK

Peripheral APB bus interface clock.

cmuClock_LSPCLK

Low speed peripheral APB bus interface clock.

cmuClock_TRACECLK

Debug trace.

cmuClock_EM01GRPACLK

EM01GRPA clock.

cmuClock_EM01GRPCCLK

EM01GRPC clock.

cmuClock_EUSART0CLK

EUSART0 clock.

cmuClock_IADCCLK

IADC clock.

cmuClock_EM23GRPACLK

EM23GRPA clock.

cmuClock_WDOG0CLK

WDOG0 clock.

cmuClock_WDOG1CLK

WDOG1 clock.

cmuClock_SYSRTCCLK

SYSRTC clock.

cmuClock_EM4GRPACLK

EM4GRPA clock.

cmuClock_DPLLREFCLK

DPLLREF clock.

cmuClock_VDAC0CLK

VDAC0 clock.

cmuClock_PCNT0CLK

PCNT0 clock.

cmuClock_LESENSEHFCLK

LESENSE high frequency clock.

cmuClock_LESENSECLK

LESENSE low frequency clock.

cmuClock_CORE

Cortex-M33 core clock.

cmuClock_LDMA

LDMA clock.

cmuClock_LDMAXBAR

LDMAXBAR clock.

cmuClock_RADIOAES

RADIOAES clock.

cmuClock_GPCRC

GPCRC clock.

cmuClock_TIMER0

TIMER0 clock.

cmuClock_TIMER1

TIMER1 clock.

cmuClock_TIMER2

TIMER2 clock.

cmuClock_TIMER3

TIMER3 clock.

cmuClock_TIMER4

TIMER4 clock.

cmuClock_TIMER5

TIMER5 clock.

cmuClock_TIMER6

TIMER6 clock.

cmuClock_TIMER7

TIMER7 clock.

cmuClock_IADC0

IADC0 clock.

cmuClock_AMUXCP0

AMUXCP0 clock.

cmuClock_LETIMER0

LETIMER0 clock.

cmuClock_WDOG0

WDOG0 clock.

cmuClock_WDOG1

WDOG1 clock.

cmuClock_I2C0

I2C0 clock.

cmuClock_I2C1

I2C1 clock.

cmuClock_SYSCFG

SYSCFG clock.

cmuClock_DPLL0

DPLL0 clock.

cmuClock_HFRCO0

HFRCO0 clock.

cmuClock_HFRCOEM23

HFRCOEM23 clock.

cmuClock_HFXO

HFXO clock.

cmuClock_FSRCO

FSRCO clock.

cmuClock_LFRCO

LFRCO clock.

cmuClock_LFXO

LFXO clock.

cmuClock_ULFRCO

ULFRCO clock.

cmuClock_GPIO

GPIO clock.

cmuClock_PRS

PRS clock.

cmuClock_BURAM

BURAM clock.

cmuClock_BURTC

BURTC clock.

cmuClock_DCDC

DCDC clock.

cmuClock_SYSRTC

SYSRTC clock.

cmuClock_EUSART0

EUSART0 clock.

cmuClock_EUSART1

EUSART1 clock.

cmuClock_EUSART2

EUSART2 clock.

cmuClock_EUSART3

EUSART3 clock.

cmuClock_EUSART4

EUSART4 clock.

cmuClock_SEMAILBOX

SEMAILBOX clock.

cmuClock_SMU

SMU clock.

cmuClock_ICACHE

ICACHE clock.

cmuClock_LESENSE

LESENSE clock.

cmuClock_ACMP0

ACMP0 clock.

cmuClock_ACMP1

ACMP1 clock.

cmuClock_VDAC0

VDAC0 clock.

cmuClock_PCNT0

PCNT0 clock.

cmuClock_DMEM

DMEM clock.

cmuClock_MSC

MSC clock.

cmuClock_USB

USB clock.

cmuClock_ETAMPDET

ETAMPDET clock.

cmuClock_RFFPLL

RFFPLL clock.


Definition at line 296 of file platform/emlib/inc/em_cmu.h

CMU_Osc_TypeDef#

CMU_Osc_TypeDef

Oscillator types.

Enumerator
cmuOsc_LFXO

Low frequency crystal oscillator.

cmuOsc_LFRCO

Low frequency RC oscillator.

cmuOsc_FSRCO

Fast startup fixed frequency RC oscillator.

cmuOsc_HFXO

High frequency crystal oscillator.

cmuOsc_HFRCODPLL

High frequency RC and DPLL oscillator.

cmuOsc_HFRCOEM23

High frequency deep sleep RC oscillator.

cmuOsc_ULFRCO

Ultra low frequency RC oscillator.


Definition at line 638 of file platform/emlib/inc/em_cmu.h

CMU_Select_TypeDef#

CMU_Select_TypeDef

Selectable clock sources.

Enumerator
cmuSelect_Error

Usage error.

cmuSelect_Disabled

Clock selector disabled.

cmuSelect_FSRCO

Fast startup fixed frequency RC oscillator.

cmuSelect_HFXO

High frequency crystal oscillator.

cmuSelect_HFXORT

Re-timed high frequency crystal oscillator.

cmuSelect_HFRCODPLL

High frequency RC and DPLL oscillator.

cmuSelect_HFRCODPLLRT

Re-timed high frequency RC and DPLL oscillator.

cmuSelect_HFRCOEM23

High frequency deep sleep RC oscillator.

cmuSelect_CLKIN0

External clock input.

cmuSelect_LFXO

Low frequency crystal oscillator.

cmuSelect_LFRCO

Low frequency RC oscillator.

cmuSelect_ULFRCO

Ultra low frequency RC oscillator.

cmuSelect_HCLK

Core and AHB bus interface clock.

cmuSelect_SYSCLK

System clock.

cmuSelect_HCLKDIV1024

Prescaled HCLK frequency clock.

cmuSelect_EM01GRPACLK

EM01GRPA clock.

cmuSelect_EM23GRPACLK

EM23GRPA clock.

cmuSelect_EM01GRPCCLK

EM01GRPC clock.

cmuSelect_EXPCLK

Pin export clock.

cmuSelect_PRS

PRS input as clock.

cmuSelect_PCNTEXTCLK

Pulse counter external source or PRS as clock.

cmuSelect_TEMPOSC

Temperature oscillator.

cmuSelect_PFMOSC

PFM oscillator.

cmuSelect_BIASOSC

BIAS oscillator.

cmuSelect_USBPLL0

PLL clock for USB.

cmuSelect_RFFPLLSYS

Radio frequency friendly PLL system clock source.


Definition at line 675 of file platform/emlib/inc/em_cmu.h

CMU_DPLLEdgeSel_TypeDef#

CMU_DPLLEdgeSel_TypeDef

DPLL reference clock edge detect selector.

Enumerator
cmuDPLLEdgeSel_Fall

Detect falling edge of reference clock.

cmuDPLLEdgeSel_Rise

Detect rising edge of reference clock.


Definition at line 719 of file platform/emlib/inc/em_cmu.h

CMU_DPLLLockMode_TypeDef#

CMU_DPLLLockMode_TypeDef

DPLL lock mode selector.

Enumerator
cmuDPLLLockMode_Freq

Frequency lock mode.

cmuDPLLLockMode_Phase

Phase lock mode.


Definition at line 725 of file platform/emlib/inc/em_cmu.h

CMU_LfxoOscMode_TypeDef#

CMU_LfxoOscMode_TypeDef

LFXO oscillator modes.

Enumerator
cmuLfxoOscMode_Crystal

Crystal oscillator.

cmuLfxoOscMode_AcCoupledSine

External AC coupled sine.

cmuLfxoOscMode_External

External digital clock.


Definition at line 731 of file platform/emlib/inc/em_cmu.h

CMU_LfxoStartupDelay_TypeDef#

CMU_LfxoStartupDelay_TypeDef

LFXO start-up timeout delay.

Enumerator
cmuLfxoStartupDelay_2Cycles

2 cycles start-up delay.

cmuLfxoStartupDelay_256Cycles

256 cycles start-up delay.

cmuLfxoStartupDelay_1KCycles

1K cycles start-up delay.

cmuLfxoStartupDelay_2KCycles

2K cycles start-up delay.

cmuLfxoStartupDelay_4KCycles

4K cycles start-up delay.

cmuLfxoStartupDelay_8KCycles

8K cycles start-up delay.

cmuLfxoStartupDelay_16KCycles

16K cycles start-up delay.

cmuLfxoStartupDelay_32KCycles

32K cycles start-up delay.


Definition at line 738 of file platform/emlib/inc/em_cmu.h

CMU_HfxoOscMode_TypeDef#

CMU_HfxoOscMode_TypeDef

HFXO oscillator modes.

Enumerator
cmuHfxoOscMode_Crystal

Crystal oscillator.

cmuHfxoOscMode_ExternalSine

External digital clock.

cmuHfxoOscMode_ExternalSinePkDet

External digital clock with peak detector used.


Definition at line 750 of file platform/emlib/inc/em_cmu.h

CMU_HfxoCbLsbTimeout_TypeDef#

CMU_HfxoCbLsbTimeout_TypeDef

HFXO core bias LSB change timeout.

Enumerator
cmuHfxoCbLsbTimeout_8us

8 us timeout.

cmuHfxoCbLsbTimeout_20us

20 us timeout.

cmuHfxoCbLsbTimeout_41us

41 us timeout.

cmuHfxoCbLsbTimeout_62us

62 us timeout.

cmuHfxoCbLsbTimeout_83us

83 us timeout.

cmuHfxoCbLsbTimeout_104us

104 us timeout.

cmuHfxoCbLsbTimeout_125us

125 us timeout.

cmuHfxoCbLsbTimeout_166us

166 us timeout.

cmuHfxoCbLsbTimeout_208us

208 us timeout.

cmuHfxoCbLsbTimeout_250us

250 us timeout.

cmuHfxoCbLsbTimeout_333us

333 us timeout.

cmuHfxoCbLsbTimeout_416us

416 us timeout.

cmuHfxoCbLsbTimeout_833us

833 us timeout.

cmuHfxoCbLsbTimeout_1250us

1250 us timeout.

cmuHfxoCbLsbTimeout_2083us

2083 us timeout.

cmuHfxoCbLsbTimeout_3750us

3750 us timeout.


Definition at line 759 of file platform/emlib/inc/em_cmu.h

CMU_HfxoSteadyStateTimeout_TypeDef#

CMU_HfxoSteadyStateTimeout_TypeDef

HFXO steady state timeout.

Enumerator
cmuHfxoSteadyStateTimeout_16us

16 us timeout.

cmuHfxoSteadyStateTimeout_41us

41 us timeout.

cmuHfxoSteadyStateTimeout_83us

83 us timeout.

cmuHfxoSteadyStateTimeout_125us

125 us timeout.

cmuHfxoSteadyStateTimeout_166us

166 us timeout.

cmuHfxoSteadyStateTimeout_208us

208 us timeout.

cmuHfxoSteadyStateTimeout_250us

250 us timeout.

cmuHfxoSteadyStateTimeout_333us

333 us timeout.

cmuHfxoSteadyStateTimeout_416us

416 us timeout.

cmuHfxoSteadyStateTimeout_500us

500 us timeout.

cmuHfxoSteadyStateTimeout_666us

666 us timeout.

cmuHfxoSteadyStateTimeout_833us

833 us timeout.

cmuHfxoSteadyStateTimeout_1666us

1666 us timeout.

cmuHfxoSteadyStateTimeout_2500us

2500 us timeout.

cmuHfxoSteadyStateTimeout_4166us

4166 us timeout.


Definition at line 779 of file platform/emlib/inc/em_cmu.h

CMU_HfxoCoreDegen_TypeDef#

CMU_HfxoCoreDegen_TypeDef

HFXO core degeneration control.

Enumerator
cmuHfxoCoreDegen_None

No core degeneration.

cmuHfxoCoreDegen_33

Core degeneration control 33.

cmuHfxoCoreDegen_50

Core degeneration control 50.

cmuHfxoCoreDegen_100

Core degeneration control 100.


Definition at line 801 of file platform/emlib/inc/em_cmu.h

CMU_HfxoCtuneFixCap_TypeDef#

CMU_HfxoCtuneFixCap_TypeDef

HFXO XI and XO pin fixed capacitor control.

Enumerator
cmuHfxoCtuneFixCap_None

No fixed capacitors.

cmuHfxoCtuneFixCap_Xi

Fixed capacitor on XI pin.

cmuHfxoCtuneFixCap_Xo

Fixed capacitor on XO pin.

cmuHfxoCtuneFixCap_Both

Fixed capacitor on both pins.


Definition at line 809 of file platform/emlib/inc/em_cmu.h

CMU_Precision_TypeDef#

CMU_Precision_TypeDef

Oscillator precision modes.

Enumerator
cmuPrecisionDefault

Default precision mode.

cmuPrecisionHigh

High precision mode.


Definition at line 817 of file platform/emlib/inc/em_cmu.h

CMU_BufoutTimeoutStartup_TypeDef#

CMU_BufoutTimeoutStartup_TypeDef

Crystal sharing timeout start up timeout.

Enumerator
startupTimeout42Us

Timeout set to 42 us.

startupTimeout83Us

Timeout set to 83 us.

startupTimeout108Us

Timeout set to 108 us.

startupTimeout133Us

Timeout set to 133 us.

startupTimeout158Us

Timeout set to 158 us.

startupTimeout183Us

Timeout set to 183 us.

startupTimeout208Us

Timeout set to 208 us.

startupTimeout233Us

Timeout set to 233 us.

startupTimeout258Us

Timeout set to 258 us.

startupTimeout283Us

Timeout set to 283 us.

startupTimeout333Us

Timeout set to 333 us.

startupTimeout375Us

Timeout set to 375 us.

startupTimeout417Us

Timeout set to 417 us.

startupTimeout458Us

Timeout set to 458 us.

startupTimeout500Us

Timeout set to 500 us.

startupTimeout667Us

Timeout set to 667 us.


Definition at line 1100 of file platform/emlib/inc/em_cmu.h

CMU_PRS_Status_Output_Select_TypeDef#

CMU_PRS_Status_Output_Select_TypeDef

PRS status select output signal.

Enumerator
PRS_Status_select_0

PRS status 0 output signal.

PRS_Status_select_1

PRS status 1 output signal.


Definition at line 1135 of file platform/emlib/inc/em_cmu.h

Typedef Documentation#

CMU_ClkDiv_TypeDef#

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.


Definition at line 172 of file platform/emlib/inc/em_cmu.h

Function Documentation#

CMU_Calibrate#

uint32_t CMU_Calibrate (uint32_t cycles, CMU_Select_TypeDef ref)

Calibrate an oscillator.

Parameters
[in]cycles

The number of HCLK cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.

[in]ref

The reference clock used to compare against HCLK.

Run a calibration of a selectable reference clock againt HCLK. Please refer to the reference manual, CMU chapter, for further details.

Note

  • This function will not return until calibration measurement is completed.

Returns

  • The number of ticks the selected reference clock ticked while running cycles ticks of the HCLK clock.


Definition at line 293 of file platform/emlib/src/em_cmu.c

CMU_CalibrateConfig#

void CMU_CalibrateConfig (uint32_t downCycles, CMU_Select_TypeDef downSel, CMU_Select_TypeDef upSel)

Configure clock calibration.

Parameters
[in]downCycles

The number of downSel clock cycles to run calibration. Increasing this number increases precision, but the calibration will take more time.

[in]downSel

The clock which will be counted down downCycles cycles.

[in]upSel

The reference clock, the number of cycles generated by this clock will be counted and added up, the result can be given with the CMU_CalibrateCountGet() function call.

Configure a calibration for a selectable clock source against another selectable reference clock. Refer to the reference manual, CMU chapter, for further details.

Note


Definition at line 335 of file platform/emlib/src/em_cmu.c

CMU_CalibrateCountGet#

uint32_t CMU_CalibrateCountGet (void )

Get calibration count value.

Parameters
N/A

Note

  • If continuous calibration mode is active, calibration busy will almost always be off, and reading the value will be just needed, where the normal case would be that this function call has been triggered by the CALRDY interrupt flag.

Returns

  • Calibration count, the number of UPSEL clocks (see CMU_CalibrateConfig()) in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.


Definition at line 473 of file platform/emlib/src/em_cmu.c

CMU_ClkOutPinConfig#

void CMU_ClkOutPinConfig (uint32_t clkNo, CMU_Select_TypeDef sel, CMU_ClkDiv_TypeDef clkDiv, GPIO_Port_TypeDef port, unsigned int pin)

Direct a clock to a GPIO pin.

Parameters
[in]clkNo

Selects between CLKOUT0, CLKOUT1 or CLKOUT2 outputs. Use values 0, 1 or 2.

[in]sel

Select clock source.

[in]clkDiv

Select a clock divisor (1..32). Only applicable when cmuSelect_EXPCLK is selected as clock source.

[in]port

GPIO port.

[in]pin

GPIO pin.

Note

  • Refer to the reference manual and the datasheet for details on which GPIO port/pins that are available.


Definition at line 508 of file platform/emlib/src/em_cmu.c

CMU_ClockDivGet#

CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)

Get clock divisor.

Parameters
[in]clock

Clock point to get divisor for. Notice that not all clock points have a divisors. Please refer to CMU overview in reference manual.

Returns

  • The current clock point divisor. 1 is returned if clock specifies a clock point without divisor.


Definition at line 625 of file platform/emlib/src/em_cmu.c

CMU_ClockDivSet#

void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set clock divisor.

Parameters
[in]clock

Clock point to set divisor for. Notice that not all clock points have a divisor, please refer to CMU overview in the reference manual.

[in]div

The clock divisor to use.


Definition at line 694 of file platform/emlib/src/em_cmu.c

CMU_ClockEnable#

void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

Parameters
[in]clock

The clock to enable/disable.

[in]enable
  • true - enable specified clock.

  • false - disable specified clock.

Module clocks sre disabled after reset. If a module clock is disabled, the registers of that module are not accessible and accessing such registers will hardfault the Cortex core.


Definition at line 808 of file platform/emlib/src/em_cmu.c

CMU_ClockFreqGet#

uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)

Get clock frequency for a clock point.

Parameters
[in]clock

Clock point to fetch frequency for.

Returns

  • The current frequency in Hz.


Definition at line 958 of file platform/emlib/src/em_cmu.c

CMU_ClockSelectGet#

CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)

Get currently selected reference clock used for a clock branch.

Parameters
[in]clock

Clock branch to fetch selected ref. clock for.

Returns

  • Reference clock used for clocking selected branch, cmuSelect_Error if invalid clock provided.


Definition at line 1191 of file platform/emlib/src/em_cmu.c

CMU_ClockSelectSet#

void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select reference clock/oscillator used for a clock branch.

Parameters
[in]clock

Clock branch to select reference clock for.

[in]ref

Reference selected for clocking, please refer to reference manual for for details on which reference is available for a specific clock branch.


Definition at line 1534 of file platform/emlib/src/em_cmu.c

CMU_LF_ClockPrecisionGet#

uint16_t CMU_LF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

Parameters
[in]clock

Clock branch.

Returns

  • Precision, in PPM, of the specified clock branch.

Note

  • This function is only for internal usage.

  • The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.


Definition at line 2394 of file platform/emlib/src/em_cmu.c

CMU_HF_ClockPrecisionGet#

uint16_t CMU_HF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

Parameters
[in]clock

Clock branch.

Returns

  • Precision, in PPM, of the specified clock branch.

Note

  • This function is only for internal usage.

  • The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.


Definition at line 2447 of file platform/emlib/src/em_cmu.c

CMU_HFRCODPLLBandGet#

CMU_HFRCODPLLFreq_TypeDef CMU_HFRCODPLLBandGet (void )

Get HFRCODPLL band in use.

Parameters
N/A

Returns

  • HFRCODPLL band in use.


Definition at line 2476 of file platform/emlib/src/em_cmu.c

CMU_HFRCODPLLBandSet#

void CMU_HFRCODPLLBandSet (CMU_HFRCODPLLFreq_TypeDef freq)

Set HFRCODPLL band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freq

HFRCODPLL frequency band to activate.


Definition at line 2489 of file platform/emlib/src/em_cmu.c

CMU_DPLLLock#

bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef * init)

Lock the DPLL to a given frequency.

Parameters
[in]init

DPLL setup parameter struct.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note

  • This function does not check if the given N & M values will actually produce the desired target frequency.
    N & M limitations:
    300 < N <= 4095
    0 <= M <= 4095
    Any peripheral running off HFRCODPLL should be switched to a lower frequency clock (if possible) prior to calling this function to avoid over-clocking.

Returns

  • Returns false on invalid target frequency or DPLL locking error.


Definition at line 2629 of file platform/emlib/src/em_cmu.c

CMU_USBPLLInit#

void CMU_USBPLLInit (const CMU_USBPLL_Init_TypeDef * pllInit)

Initialize the USB PLL control registers.

Parameters
[in]pllInit

USB PLL parameters

Note

  • The HFXO reference frequency must be updated if crystal value is different from default value.


Definition at line 2824 of file platform/emlib/src/em_cmu.c

CMU_WaitUSBPLLLock#

void CMU_WaitUSBPLLLock (void )

Wait for USB PLL lock and ready.

Parameters
N/A

Definition at line 1658 of file platform/emlib/inc/em_cmu.h

CMU_RFFPLLInit#

void CMU_RFFPLLInit (const CMU_RFFPLL_Init_TypeDef * pllInit)

Initialize the RFFPLL control registers.

Parameters
[in]pllInit

RFF PLL parameters


Definition at line 2876 of file platform/emlib/src/em_cmu.c

CMU_WaitRFFPLLLock#

void CMU_WaitRFFPLLLock (void )

Wait for RFF PLL lock and ready.

Parameters
N/A

Definition at line 1672 of file platform/emlib/inc/em_cmu.h

CMU_HFXOInit#

void CMU_HFXOInit (const CMU_HFXOInit_TypeDef * hfxoInit)

Initialize all HFXO control registers.

Parameters
[in]hfxoInit

HFXO setup parameters.

Note

  • HFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function returns early if HFXO is already selected as SYSCLK.


Definition at line 2921 of file platform/emlib/src/em_cmu.c

CMU_HFXOStartCrystalSharingLeader#

void CMU_HFXOStartCrystalSharingLeader (const CMU_BUFOUTLeaderInit_TypeDef * bufoutInit, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) leader control registers.

Parameters
[in]bufoutInit

Bufout setup parameters.

[in]port

Bufout request GPIO port.

[in]pin

Bufout request GPIO pin.

Configure the bufout request input GPIO as a clock request signal to add the crystal sharing follower chip as a source of clock request.

Warnings

  • If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.


Definition at line 3157 of file platform/emlib/src/em_cmu.c

CMU_HFXOCrystalSharingFollowerInit#

void CMU_HFXOCrystalSharingFollowerInit (CMU_PRS_Status_Output_Select_TypeDef prsStatusSelectOutput, unsigned int prsAsyncCh, GPIO_Port_TypeDef port, unsigned int pin)

Initialize HFXO Bufout (Crystal sharing) follower control registers.

Parameters
[in]prsStatusSelectOutput

Selected HFXO PRS signal output.

[in]prsAsyncCh

PRS producer asynchronous signal channel.

[in]port

Bufout request GPIO port.

[in]pin

Bufout request GPIO pin.

Configure the clock request signal to a specified GPIO to automatically request the high frequency crystal oscillator sine wave clock. This function must be used in conjunction with CMU_HFXOInit() configured with EXTERNAL_SINE or EXTERNAL_SINEPKDET mode.

Warnings

  • If EM2 capabilities are needed, a GPIO that fully retains its capabilities while in EM2 must be selected.

Note

  • This function can be emulated on XG21/XG22 chips by controlling the clock request GPIO to ask the crystal sharing leader clock when needed.


Definition at line 3216 of file platform/emlib/src/em_cmu.c

CMU_HFXOCTuneSet#

sl_status_t CMU_HFXOCTuneSet (uint32_t ctune)

Set the HFXO crystal tuning capacitance.

Parameters
[in]ctune

The desired tuning capacitance value. Each step corresponds to approximately 80fF. Min value is 0. Max value is 255.

Returns

  • SL_STATUS_OK if initialization parameter is valid. SL_STATUS_INVALID_PARAMETER if initialization parameter is invalid.

Note

  • While the oscillator is running in steady operation state, it may be desirable to modify the tuning capacitance via CTUNEXIANA and CTUNEXOANA fields in the HFXO_XTALCTRL register. When tuning, care should be taken to make small changes to the CTUNE registers. Ideally, change the CTUNE registers by one LSB at a time and alternate between the XI and XO registers. Sufficient wait time for settling, on the order of TIMEOUTSTEADY, should pass before new frequency measurement is taken.


Definition at line 3301 of file platform/emlib/src/em_cmu.c

CMU_HFXOCTuneGet#

uint32_t CMU_HFXOCTuneGet (void )

Get the HFXO crystal tuning capacitance.

Parameters
N/A

Returns

  • The HFXO crystal tuning capacitance.

Note

  • This function only returns the CTUNE XI value. The XO value can be different and can be found using the delta (difference between XI and XO). See CMU_HFXOCTuneDeltaGet to retrieve the delta value.


Definition at line 3366 of file platform/emlib/src/em_cmu.c

CMU_HFXOCTuneDeltaSet#

void CMU_HFXOCTuneDeltaSet (int32_t delta)

Set the HFXO crystal tuning delta.

Parameters
[in]delta

Chip dependent crystal capacitor bank delta between HFXO XI and XO.

Note

  • The delta between XI and XO is applicable for the series 2 EFR32xG2x devices only.


Definition at line 3418 of file platform/emlib/src/em_cmu.c

CMU_HFXOCTuneDeltaGet#

int32_t CMU_HFXOCTuneDeltaGet (void )

Get the HFXO crystal tuning delta.

Parameters
N/A

Returns

  • Chip dependent crystal capacitor bank tuning delta.


Definition at line 3430 of file platform/emlib/src/em_cmu.c

CMU_HFXOCoreBiasCurrentCalibrate#

void CMU_HFXOCoreBiasCurrentCalibrate (void )

Recalibrate the HFXO's Core Bias Current.

Parameters
N/A

Note

  • Care should be taken when using this function as it can cause disturbance on the HFXO frequency while the optimization is underway. It's recommended to only use this function when HFXO isn't being used. It's also a blocking function that can be time consuming.


Definition at line 3445 of file platform/emlib/src/em_cmu.c

CMU_LFXOInit#

void CMU_LFXOInit (const CMU_LFXOInit_TypeDef * lfxoInit)

Initialize LFXO control registers.

Parameters
[in]lfxoInit

LFXO setup parameters

Note

  • LFXO configuration should be obtained from a configuration tool, app note or crystal datasheet. This function disables the LFXO to ensure a valid state before update.


Definition at line 3505 of file platform/emlib/src/em_cmu.c

CMU_LFXOPrecisionSet#

void CMU_LFXOPrecisionSet (uint16_t precision)

Sets LFXO's crystal precision, in PPM.

Parameters
[in]precision

LFXO's crystal precision, in PPM.

Note

  • LFXO precision should be obtained from a crystal datasheet.


Definition at line 3562 of file platform/emlib/src/em_cmu.c

CMU_LFXOPrecisionGet#

uint16_t CMU_LFXOPrecisionGet (void )

Gets LFXO's crystal precision, in PPM.

Parameters
[in]

LFXO's crystal precision, in PPM.


Definition at line 3574 of file platform/emlib/src/em_cmu.c

CMU_HFXOPrecisionSet#

void CMU_HFXOPrecisionSet (uint16_t precision)

Sets HFXO's crystal precision, in PPM.

Parameters
[in]precision

HFXO's crystal precision, in PPM.

Note

  • HFXO precision should be obtained from a crystal datasheet.


Definition at line 3589 of file platform/emlib/src/em_cmu.c

CMU_HFXOPrecisionGet#

uint16_t CMU_HFXOPrecisionGet (void )

Gets HFXO's crystal precision, in PPM.

Parameters
[in]

HFXO's crystal precision, in PPM.


Definition at line 3601 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningGet#

uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)

Get oscillator frequency tuning setting.

Parameters
[in]osc

Oscillator to get tuning value for.

Returns

  • The oscillator frequency tuning setting in use.


Definition at line 3672 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningSet#

void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

Parameters
[in]osc

Oscillator to set tuning value for.

[in]val

The oscillator frequency tuning setting to use.

Note

  • Oscillator tuning is done during production, and the tuning value is automatically loaded after a reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.


Definition at line 3737 of file platform/emlib/src/em_cmu.c

CMU_UpdateWaitStates#

void CMU_UpdateWaitStates (uint32_t freq, int vscale)

Configure wait state settings necessary to switch to a given core clock frequency at a certain voltage scale level.

Parameters
[in]freq

The core clock frequency to configure wait-states.

[in]vscale

The voltage scale to configure wait-states. Expected values are 0 or 1, higher number is lower voltage.

  • 0 = 1.1 V (VSCALE2)

  • 1 = 1.0 V (VSCALE1)

This function will set up the necessary flash wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.


Definition at line 3863 of file platform/emlib/src/em_cmu.c

CMU_PCNTClockExternalSet#

void CMU_PCNTClockExternalSet (unsigned int instance, bool external)

Select the PCNTn clock.

Parameters
[in]instance

PCNT instance number to set selected clock source for.

[in]external

Set to true to select the external clock, false to select EM23GRPACLK.


Definition at line 3882 of file platform/emlib/src/em_cmu.c

CMU_HFRCOEM23BandGet#

CMU_HFRCOEM23Freq_TypeDef CMU_HFRCOEM23BandGet (void )

Get HFRCOEM23 band in use.

Parameters
N/A

Returns

  • HFRCOEM23 band in use.


Definition at line 3904 of file platform/emlib/src/em_cmu.c

CMU_HFRCOEM23BandSet#

void CMU_HFRCOEM23BandSet (CMU_HFRCOEM23Freq_TypeDef freq)

Set HFRCOEM23 band and the tuning value based on the value in the calibration table made during production.

Parameters
[in]freq

HFRCOEM23 frequency band to activate.


Definition at line 3917 of file platform/emlib/src/em_cmu.c

CMU_CalibrateCont#

void CMU_CalibrateCont (bool enable)

Configure continuous calibration mode.

Parameters
[in]enable

If true, enables continuous calibration, if false disables continuous calibration.


Definition at line 1444 of file platform/emlib/inc/em_cmu.h

CMU_CalibrateStart#

void CMU_CalibrateStart (void )

Start calibration.

Parameters
N/A

Note


Definition at line 1456 of file platform/emlib/inc/em_cmu.h

CMU_CalibrateStop#

void CMU_CalibrateStop (void )

Stop calibration counters.

Parameters
N/A

Definition at line 1465 of file platform/emlib/inc/em_cmu.h

CMU_DPLLUnlock#

void CMU_DPLLUnlock (void )

Unlock the DPLL.

Parameters
N/A

Note

  • The HFRCODPLL oscillator is not turned off.


Definition at line 1476 of file platform/emlib/inc/em_cmu.h

CMU_IntClear#

void CMU_IntClear (uint32_t flags)

Clear one or more pending CMU interrupt flags.

Parameters
[in]flags

CMU interrupt sources to clear.


Definition at line 1492 of file platform/emlib/inc/em_cmu.h

CMU_IntDisable#

void CMU_IntDisable (uint32_t flags)

Disable one or more CMU interrupt sources.

Parameters
[in]flags

CMU interrupt sources to disable.


Definition at line 1504 of file platform/emlib/inc/em_cmu.h

CMU_IntEnable#

void CMU_IntEnable (uint32_t flags)

Enable one or more CMU interrupt sources.

Parameters
[in]flags

CMU interrupt sources to enable.

Note

  • Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if such a pending interrupt should be ignored.


Definition at line 1521 of file platform/emlib/inc/em_cmu.h

CMU_IntGet#

uint32_t CMU_IntGet (void )

Get pending CMU interrupt sources.

Parameters
N/A

Returns

  • CMU interrupt sources pending.


Definition at line 1533 of file platform/emlib/inc/em_cmu.h

CMU_IntGetEnabled#

uint32_t CMU_IntGetEnabled (void )

Get enabled and pending CMU interrupt flags.

Parameters
N/A

Useful for handling more interrupt sources in the same interrupt handler.

Note

  • The event bits are not cleared by the use of this function.

Returns

  • Pending and enabled CMU interrupt sources. The return value is the bitwise AND of

    • the enabled interrupt sources in CMU_IEN and

    • the pending interrupt flags CMU_IF


Definition at line 1554 of file platform/emlib/inc/em_cmu.h

CMU_IntSet#

void CMU_IntSet (uint32_t flags)

Set one or more pending CMU interrupt sources.

Parameters
[in]flags

CMU interrupt sources to set to pending.


Definition at line 1569 of file platform/emlib/inc/em_cmu.h

CMU_Lock#

void CMU_Lock (void )

Lock CMU register access in order to protect registers contents against unintended modification.

Parameters
N/A

See the reference manual for CMU registers that will be locked.

Note

  • If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.


Definition at line 1587 of file platform/emlib/inc/em_cmu.h

CMU_OscillatorEnable#

void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

Parameters
[in]osc

The oscillator to enable/disable.

[in]enable
  • true - enable specified oscillator.

  • false - disable specified oscillator.

[in]wait

Only used if enable is true.

  • true - wait for oscillator start-up time to timeout before returning.

  • false - do not wait for oscillator start-up time to timeout before returning.

Note

  • This is a dummy function to solve backward compatibility issues.


Definition at line 1612 of file platform/emlib/inc/em_cmu.h

CMU_Unlock#

void CMU_Unlock (void )

Unlock CMU register access so that writing to registers is possible.

Parameters
N/A

Definition at line 1625 of file platform/emlib/inc/em_cmu.h

CMU_WdogLock#

void CMU_WdogLock (void )

Lock WDOG register access in order to protect registers contents against unintended modification.

Parameters
N/A

Note

  • If locking the WDOG registers, they must be unlocked prior to using any emlib API functions modifying registers protected by the lock.


Definition at line 1639 of file platform/emlib/inc/em_cmu.h

CMU_WdogUnlock#

void CMU_WdogUnlock (void )

Unlock WDOG register access so that writing to registers is possible.

Parameters
N/A

Definition at line 1648 of file platform/emlib/inc/em_cmu.h

CMU_PrescToLog2#

uint32_t CMU_PrescToLog2 (uint32_t presc)

Convert prescaler divider to a logarithmic value.

Parameters
[in]presc

Prescaler value used to set the frequency divider. The divider is equal to ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be equal to (divider - 1).

It only works for even numbers equal to 2^n.

Returns

  • Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.


Definition at line 3629 of file platform/emlib/inc/em_cmu.h

Macro Definition Documentation#

CMU_CLOCK_SELECT_SET#

#define CMU_CLOCK_SELECT_SET
Value:
(clock, sel)

Macro to set clock sources in the clock tree.


Definition at line 55 of file platform/emlib/inc/em_cmu.h

_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Disable clocks configuration.

Mode DISABLED for CMU_EM01GRPACLKCTRL


Definition at line 153 of file platform/emlib/inc/em_cmu.h

CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_EM01GRPACLKCTRL_CLKSEL_DISABLED  << 0)

Shifted mode DISABLED for CMU_EM01GRPACLKCTRL.


Definition at line 154 of file platform/emlib/inc/em_cmu.h

_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_EM01GRPBCLKCTRL


Definition at line 155 of file platform/emlib/inc/em_cmu.h

CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED#

#define CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_EM01GRPBCLKCTRL_CLKSEL_DISABLED  << 0)

Shifted mode DISABLED for CMU_EM01GRPBCLKCTRL.


Definition at line 156 of file platform/emlib/inc/em_cmu.h

_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_EM23GRPACLKCTRL


Definition at line 157 of file platform/emlib/inc/em_cmu.h

CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_EM23GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM23GRPACLKCTRL.


Definition at line 158 of file platform/emlib/inc/em_cmu.h

_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED#

#define _CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_EM4GRPACLKCTRL


Definition at line 159 of file platform/emlib/inc/em_cmu.h

CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED#

#define CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_EM4GRPACLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EM4GRPACLKCTRL.


Definition at line 160 of file platform/emlib/inc/em_cmu.h

_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_WDOG0CLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_WDOG0CLKCTRL


Definition at line 161 of file platform/emlib/inc/em_cmu.h

CMU_WDOG0CLKCTRL_CLKSEL_DISABLED#

#define CMU_WDOG0CLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_WDOG0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG0CLKCTRL


Definition at line 162 of file platform/emlib/inc/em_cmu.h

_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED#

#define _CMU_WDOG1CLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_WDOG1CLKCTRL


Definition at line 163 of file platform/emlib/inc/em_cmu.h

CMU_WDOG1CLKCTRL_CLKSEL_DISABLED#

#define CMU_WDOG1CLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_WDOG1CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_WDOG1CLKCTRL


Definition at line 164 of file platform/emlib/inc/em_cmu.h

_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_EUSART0CLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_EUSART0CLKCTRL


Definition at line 165 of file platform/emlib/inc/em_cmu.h

CMU_EUSART0CLKCTRL_CLKSEL_DISABLED#

#define CMU_EUSART0CLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_EUSART0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_EUSART0CLKCTRL.


Definition at line 166 of file platform/emlib/inc/em_cmu.h

_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED#

#define _CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED
Value:
0x00000000UL

Mode DISABLED for CMU_SYSRTC0CLKCTRL


Definition at line 167 of file platform/emlib/inc/em_cmu.h

CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED#

#define CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED
Value:
(_CMU_SYSRTC0CLKCTRL_CLKSEL_DISABLED << 0)

Shifted mode DISABLED for CMU_SYSRTC0CLKCTRL.


Definition at line 168 of file platform/emlib/inc/em_cmu.h

CMU_HFRCODPLL_MIN#

#define CMU_HFRCODPLL_MIN
Value:
cmuHFRCODPLLFreq_1M0Hz

HFRCODPLL maximum frequency.


Definition at line 215 of file platform/emlib/inc/em_cmu.h

CMU_HFRCODPLL_MAX#

#define CMU_HFRCODPLL_MAX
Value:
cmuHFRCODPLLFreq_80M0Hz

HFRCODPLL minimum frequency.


Definition at line 217 of file platform/emlib/inc/em_cmu.h

CMU_HFRCOEM23_MIN#

#define CMU_HFRCOEM23_MIN
Value:
cmuHFRCOEM23Freq_1M0Hz

HFRCOEM23 maximum frequency.


Definition at line 235 of file platform/emlib/inc/em_cmu.h

CMU_HFRCOEM23_MAX#

#define CMU_HFRCOEM23_MAX
Value:
cmuHFRCOEM23Freq_40M0Hz

HFRCOEM23 minimum frequency.


Definition at line 237 of file platform/emlib/inc/em_cmu.h

CMU_LFXOINIT_DEFAULT#

#define CMU_LFXOINIT_DEFAULT
Value:
{ \
1, \
38, \
cmuLfxoStartupDelay_4KCycles, \
cmuLfxoOscMode_Crystal, \
false, /* highAmplitudeEn */ \
true, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for XTAL mode.


Definition at line 844 of file platform/emlib/inc/em_cmu.h

CMU_LFXOINIT_EXTERNAL_CLOCK#

#define CMU_LFXOINIT_EXTERNAL_CLOCK
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_External, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external clock mode.


Definition at line 860 of file platform/emlib/inc/em_cmu.h

CMU_LFXOINIT_EXTERNAL_SINE#

#define CMU_LFXOINIT_EXTERNAL_SINE
Value:
{ \
0U, \
0U, \
cmuLfxoStartupDelay_2Cycles, \
cmuLfxoOscMode_AcCoupledSine, \
false, /* highAmplitudeEn */ \
false, /* agcEn */ \
false, /* failDetEM4WUEn */ \
false, /* failDetEn */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false /* Lock registers */ \
}

Default LFXO initialization values for external sine mode.


Definition at line 876 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_CTUNEFIXANA_DEFAULT#

#define CMU_HFXOINIT_CTUNEFIXANA_DEFAULT
Value:
cmuHfxoCtuneFixCap_Xo

Default configuration of fixed tuning capacitance on XO for EFR32XG25.


Definition at line 941 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_DEFAULT#

#define CMU_HFXOINIT_DEFAULT
Value:
{ \
cmuHfxoCbLsbTimeout_416us, \
cmuHfxoSteadyStateTimeout_833us, /* First lock */ \
cmuHfxoSteadyStateTimeout_83us, /* Subsequent locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
32U, /* coreBiasStartup */ \
32U, /* imCoreBiasStartup */ \
cmuHfxoCoreDegen_None, \
CMU_HFXOINIT_CTUNEFIXANA_DEFAULT, \
_HFXO_XTALCTRL_CTUNEXOANA_DEFAULT, /* ctuneXoAna */ \
_HFXO_XTALCTRL_CTUNEXIANA_DEFAULT, /* ctuneXiAna */ \
60U, /* coreBiasAna */ \
false, /* enXiDcBiasAna */ \
cmuHfxoOscMode_Crystal, \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for XTAL mode.


Definition at line 950 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_EXTERNAL_SINE#

#define CMU_HFXOINIT_EXTERNAL_SINE
Value:
{ \
(CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
0U, /* coreBiasStartup */ \
0U, /* imCoreBiasStartup */ \
cmuHfxoCoreDegen_None, \
cmuHfxoCtuneFixCap_None, \
0U, /* ctuneXoAna */ \
0U, /* ctuneXiAna */ \
0U, /* coreBiasAna */ \
false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
cmuHfxoOscMode_ExternalSine, \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna (Never enable in sine mode) */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for external sine mode.


Definition at line 975 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_EXTERNAL_SINEPKDET#

#define CMU_HFXOINIT_EXTERNAL_SINEPKDET
Value:
{ \
(CMU_HfxoCbLsbTimeout_TypeDef)0, /* timeoutCbLsb */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, first lock */ \
(CMU_HfxoSteadyStateTimeout_TypeDef)0, /* timeoutSteady, subseq. locks */ \
0U, /* ctuneXoStartup */ \
0U, /* ctuneXiStartup */ \
0U, /* coreBiasStartup */ \
0U, /* imCoreBiasStartup */ \
cmuHfxoCoreDegen_None, \
cmuHfxoCtuneFixCap_None, \
0U, /* ctuneXoAna */ \
0U, /* ctuneXiAna */ \
0U, /* coreBiasAna */ \
false, /* enXiDcBiasAna, false=DC true=AC coupling of signal */ \
cmuHfxoOscMode_ExternalSinePkDet, \
false, /* forceXo2GndAna */ \
false, /* forceXi2GndAna (Never enable in sine mode) */ \
false, /* DisOndemand */ \
false, /* ForceEn */ \
false, /* em23OnDemand */ \
false /* Lock registers */ \
}

Default HFXO initialization values for external sine mode with peak detector.


Definition at line 1000 of file platform/emlib/inc/em_cmu.h

CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT#

#define CMU_HFXO_CRYSTAL_INIT_LEADER_DEFAULT
Value:
{ \
true, /* minimalStartupDelay */ \
startupTimeout208Us, /* timeoutStartup */ \
}

Default crystal sharing master initialization values.


Definition at line 1126 of file platform/emlib/inc/em_cmu.h

CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT#

#define CMU_HFXO_CRYSTAL_INIT_Follower_DEFAULT
Value:
{ \
PRS_Status_select_0, /* prsStatusSelectOutput */ \
true, /* em23OnDemand */ \
false /* regLock */ \
}

Default crystal sharing follower initialization values.


Definition at line 1148 of file platform/emlib/inc/em_cmu.h

CMU_DPLL_LFXO_TO_40MHZ#

#define CMU_DPLL_LFXO_TO_40MHZ
Value:
{ \
39998805, /* Target frequency. */ \
3661, /* Factor N. */ \
2, /* Factor M. */ \
cmuSelect_LFXO, /* Select LFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.


Definition at line 1173 of file platform/emlib/inc/em_cmu.h

CMU_DPLL_HFXO_TO_76_8MHZ#

#define CMU_DPLL_HFXO_TO_76_8MHZ
Value:
{ \
76800000, /* Target frequency. */ \
3839, /* Factor N. */ \
1919, /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 76,800,000 Hz using HFXO as reference clock, M = 1919, N = 3839.


Definition at line 1189 of file platform/emlib/inc/em_cmu.h

CMU_DPLL_HFXO_TO_80MHZ#

#define CMU_DPLL_HFXO_TO_80MHZ
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

DPLL initialization values for 80,000,000 Hz using HFXO as reference clock, M = 1919, N = 3999.


Definition at line 1205 of file platform/emlib/inc/em_cmu.h

CMU_DPLLINIT_DEFAULT#

#define CMU_DPLLINIT_DEFAULT
Value:
{ \
80000000, /* Target frequency. */ \
(4000 - 1), /* Factor N. */ \
(1920 - 1), /* Factor M. */ \
cmuSelect_HFXO, /* Select HFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true, /* Enable automatic lock recovery. */ \
false /* Don't enable dither function. */ \
}

Default configurations for DPLL initialization.

When using this macro you need to modify the N and M factor and the desired frequency to match the components placed on the board.


Definition at line 1222 of file platform/emlib/inc/em_cmu.h

CMU_USBPLL_REFFREQ_38MHZ#

#define CMU_USBPLL_REFFREQ_38MHZ
Value:
{ \
cmuHFXORefFreq_38M0Hz, /* Reference frequency. */ \
false, /* Disable shunt regulator. */ \
false, /* Disable PLL always on. */ \
false, /* Force enable. */ \
true /* Enable register lock. */ \
}

Default configurations for USB PLL initialization if the HFXO frequency is 38 MHz.


Definition at line 1248 of file platform/emlib/inc/em_cmu.h

CMU_USBPLL_REFFREQ_38_4MHZ#

#define CMU_USBPLL_REFFREQ_38_4MHZ
Value:
{ \
cmuHFXORefFreq_38M4Hz, /* Reference frequency. */ \
false, /* Disable shunt regulator. */ \
false, /* Disable PLL always on. */ \
false, /* Force enable. */ \
true /* Enable register lock. */ \
}

Default configurations for USB PLL initialization if the HFXO frequency is 38.4 MHz.


Definition at line 1261 of file platform/emlib/inc/em_cmu.h

CMU_USBPLL_REFFREQ_39MHZ#

#define CMU_USBPLL_REFFREQ_39MHZ
Value:
{ \
cmuHFXORefFreq_39M0Hz, /* Reference frequency. */ \
false, /* Disable shunt regulator. */ \
false, /* Disable PLL always on. */ \
false, /* Force enable. */ \
true /* Enable register lock. */ \
}

Default configurations for USB PLL initialization if the HFXO frequency is 39 MHz.


Definition at line 1274 of file platform/emlib/inc/em_cmu.h

CMU_USBPLL_REFFREQ_40MHZ#

#define CMU_USBPLL_REFFREQ_40MHZ
Value:
{ \
cmuHFXORefFreq_40M0Hz, /* Reference frequency. */ \
false, /* Disable shunt regulator. */ \
false, /* Disable PLL always on. */ \
false, /* Force enable. */ \
true /* Enable register lock. */ \
}

Default configurations for USB PLL initialization if the HFXO frequency is 40 MHz.


Definition at line 1287 of file platform/emlib/inc/em_cmu.h

CMU_RFFPLL_DEFAULT#

#define CMU_RFFPLL_DEFAULT
Value:
{ \
100000000UL, /* Host target frequency. */ \
false, /* Disable on-demand requests. */ \
false, /* Force enable. */ \
true, /* Enable register lock. */ \
_RFFPLL_RFFPLLCTRL1_DIVY_DEFAULT, /* Divider Y for digital. */ \
_RFFPLL_RFFPLLCTRL1_DIVX_DEFAULT, /* Divider X for Radio. */ \
_RFFPLL_RFFPLLCTRL1_DIVN_DEFAULT /* Feedback divider N. */ \
}

Radio frequency locked loop default initialization values.


Definition at line 1318 of file platform/emlib/inc/em_cmu.h

CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ#

#define CMU_RFFPLL_97_5_MHZ_REF_FREQ_39_MHZ
Value:
{ \
97500000UL, /* Host target frequency. */ \
false, /* Disable on-demand requests. */ \
false, /* Force enable. */ \
true, /* Enable register lock. */ \
20U, /* Divider Y for digital. */ \
6U, /* Divider X for Radio. */ \
100U /* Feedback divider N. */ \
}

Radio frequency locked loop initialization values for 97.5MHz.


Definition at line 1330 of file platform/emlib/inc/em_cmu.h