DPLL initialization structure.

Frequency will be Fref*(N+1)/(M+1).

Public Attributes#

uint32_t
frequency

PLL frequency value, max 80 MHz.

uint16_t
n

Factor N.

uint16_t
m

Factor M.

CMU_Select_TypeDef
refClk

Reference clock selector.

CMU_DPLLEdgeSel_TypeDef
edgeSel

Reference clock edge detect selector.

CMU_DPLLLockMode_TypeDef
lockMode

DPLL lock mode selector.

bool
autoRecover

Enable automatic lock recovery.

bool
ditherEn

Enable dither functionality.

Public Attribute Documentation#

frequency#

uint32_t CMU_DPLLInit_TypeDef::frequency

PLL frequency value, max 80 MHz.


n#

uint16_t CMU_DPLLInit_TypeDef::n

Factor N.

300 <= N <= 4095


m#

uint16_t CMU_DPLLInit_TypeDef::m

Factor M.

M <= 4095


refClk#

CMU_Select_TypeDef CMU_DPLLInit_TypeDef::refClk

Reference clock selector.



edgeSel#

CMU_DPLLEdgeSel_TypeDef CMU_DPLLInit_TypeDef::edgeSel

Reference clock edge detect selector.


lockMode#

CMU_DPLLLockMode_TypeDef CMU_DPLLInit_TypeDef::lockMode

DPLL lock mode selector.



autoRecover#

bool CMU_DPLLInit_TypeDef::autoRecover

Enable automatic lock recovery.



ditherEn#

bool CMU_DPLLInit_TypeDef::ditherEn

Enable dither functionality.