VDAC initialization structure, common for both channels.
Public Attributes#
uint32_t
Number of prescaled CLK_DAC + 1 for the vdac to warmup.
bool
Halt during debug.
bool
Always allow clk_dac.
bool
DMA Wakeup.
bool
Bias keep warm enable.
Channel refresh period.
Internal timer overflow period.
uint32_t
Prescaler for VDAC clock.
Reference voltage to use.
bool
Enable/disable reset of prescaler on CH 0 start.
bool
Sine reset mode.
bool
Enable/disable sine mode.
bool
Select if single ended or differential output mode.
bool
PRS controlled sinemode enable.
bool
PRS controlled channel output enable.
Public Attribute Documentation#
warmupTime#
uint32_t VDAC_Init_TypeDef::warmupTime
Number of prescaled CLK_DAC + 1 for the vdac to warmup.
timerOverflow#
VDAC_TimerOverflow_TypeDef VDAC_Init_TypeDef::timerOverflow
Internal timer overflow period.
prescaler#
uint32_t VDAC_Init_TypeDef::prescaler
Prescaler for VDAC clock.
Clock is source clock divided by prescaler+1.