Si7210 Details#
Register interface and implementation details.
Registers#
Hardware revision ID register
The most significant byte of the last conversion result
The least significant byte of the last conversion result
Select the data after filtering
Power control register
Enables auto increment of the I2C register address pointer
Control register 1, output pin configuration
Control register 2, output pin configuration
Sleep time control register
Control register 3, output pin and sleep time configuration
Coefficient A0
Coefficient A1
Coefficient A2
Control register 4, Digital filter configuration
Coefficient A3
Coefficient A4
Coefficient A5
OTP address of the data to read
Data read from OTP
OTP read control register
On-chip test coil control
Revision ID mask, Hardware revision ID register
Revision ID shift value, Hardware revision ID register
Chip ID mask, Hardware revision ID register
Revision ID shift value, Hardware revision ID register
New data available mask, MSB of last conversion result register
New data available shift value, MSB of last conversion result register
MSB bits of conversion mask, MSB of last conversion result register
MSB bits of conversion shift value, MSB of last conversion result register
Sleep mode bit mask, Power control register
Sleep mode bit shift value, Power control register
Stop bit mask, Power control register
Stop bit shift value, Power control register
One burst mesurement bit mask, Power control register
One burst mesurement bit shift value, Power control register
Save the current state of OTP regs bit mask, Power control register
Save the current state of OTP regs bit shift value, Power control register
Measurement in progress bit mask, Power control register
Measurement in progress bit shift value, Power control register
Switching point mask, Control register 1
Switching point shift value, Control register 1
Output polarity setting bit mask, Control register 1
Output polarity setting bit shift value, Control register 1
Switch hysteresis mask, Control register 2
Switch hyteresis shift value, Control register 2
Switch polarity mask, Control register 2
Switchi polarity shift value, Control register 2
Sleep timer enable bit mask, Control register 3
Sleep timer enable bit shift value, Control register 3
Sleep time reduction enable bit mask, Control register 3
Sleep time reduction bit shift value, Control register 3
Tamper switch threshold mask, Control register 3
Tamper switch threshold shift value, Control register 3
IIR filter enable bit mask, Control register 4
IIR filter enable bit shift value, Control register 4
Number of samples to average mask, Control register 4
Number of samples to average shift value, Control register 4
Measurement burst size mask, Control register 4
Measurement burst size shift value, Control register 4
OTP busy indicator bit mask, OTP read control register
OTP busy indicator bit shift value, OTP read control register
OTP read enable bit mask, OTP read control register
OTP read enable bit shift value, OTP read control register
OTP Control register 1, output pin configuration
OTP Control register 2, output pin configuration
OTP Sleep time control register
OTP Control register 3, output pin and sleep time configuration
OTP Coefficient A0
OTP Coefficient A1
OTP Coefficient A2
OTP Control register 4, Digital filter configuration
OTP Coefficient A3
OTP Coefficient A4
OTP Coefficient A5
OTP Base part number
OTP Variant number
OTP Serial number
OTP On-chip field generator calibration value
OTP 20mT scale no magnet temperature compensation value
OTP 200mT scale no magnet temperature compensation value
OTP 20mT scale neodymium magnet temperature compensation value
OTP 200mT scale neodymium temperature compensation value
OTP 20mT scale ceramic magnet temperature compensation value
OTP 200mT scale ceramic magnet temperature compensation value
Functions#
Read register from the OTP area of the Si7021 device.
Read register from the Hall sensor device.
Write a register in the Hall sensor device.
Set the given bit(s) in a register in the Hall sensor device.
Clear the given bit(s) in a register in the Hall sensor device.
Calculate the sw_op value from the threshold by finding the inverse of the formula: threshold = (16 + sw_op[3:0]) * 2^sw_op[6:4].
Calculate the sw_hyst value from the hysteresis by finding the inverse of the formula: hysteresis = (8 + sw_hyst[2:0]) * 2^sw_hyst[5:3].
Calculate the sw_tamper value from the tamper threshold by finding the inverse of the formula: tamper = (16 + sw_tamper[3:0]) * 2^(sw_tamper[5:4] + 5)
Calculate the slTime value from the sleep time by finding the inverse of the formula: tsleep = (32 + slTime[4:0]) * 2^(8 + slTime[7:5]) / 12 MHz.
Registers Documentation#
SI7210_REG_ADDR_DSPSIGM#
#define SI7210_REG_ADDR_DSPSIGMValue:
0xC1
The most significant byte of the last conversion result
SI7210_REG_ADDR_DSPSIGL#
#define SI7210_REG_ADDR_DSPSIGLValue:
0xC2
The least significant byte of the last conversion result
SI7210_REG_ADDR_DSPSIGSEL#
#define SI7210_REG_ADDR_DSPSIGSELValue:
0xC3
Select the data after filtering
SI7210_REG_ADDR_ARAUTOINC#
#define SI7210_REG_ADDR_ARAUTOINCValue:
0xC5
Enables auto increment of the I2C register address pointer
SI7210_REG_ADDR_CTRL1#
#define SI7210_REG_ADDR_CTRL1Value:
0xC6
Control register 1, output pin configuration
SI7210_REG_ADDR_CTRL2#
#define SI7210_REG_ADDR_CTRL2Value:
0xC7
Control register 2, output pin configuration
SI7210_REG_ADDR_CTRL3#
#define SI7210_REG_ADDR_CTRL3Value:
0xC9
Control register 3, output pin and sleep time configuration
SI7210_REG_ADDR_CTRL4#
#define SI7210_REG_ADDR_CTRL4Value:
0xCD
Control register 4, Digital filter configuration
SI7210_REG_HREVID_REVID_MASK#
#define SI7210_REG_HREVID_REVID_MASKValue:
0x0F
Revision ID mask, Hardware revision ID register
SI7210_REG_HREVID_REVID_SHIFT#
#define SI7210_REG_HREVID_REVID_SHIFTValue:
0
Revision ID shift value, Hardware revision ID register
SI7210_REG_HREVID_CHIPID_MASK#
#define SI7210_REG_HREVID_CHIPID_MASKValue:
0xF0
Chip ID mask, Hardware revision ID register
SI7210_REG_HREVID_CHIPID_SHIFT#
#define SI7210_REG_HREVID_CHIPID_SHIFTValue:
4
Revision ID shift value, Hardware revision ID register
SI7210_REG_DSPSIGM_FRESH_MASK#
#define SI7210_REG_DSPSIGM_FRESH_MASKValue:
0x80
New data available mask, MSB of last conversion result register
SI7210_REG_DSPSIGM_FRESH_SHIFT#
#define SI7210_REG_DSPSIGM_FRESH_SHIFTValue:
7
New data available shift value, MSB of last conversion result register
SI7210_REG_DSPSIGM_DSPSIGM_MASK#
#define SI7210_REG_DSPSIGM_DSPSIGM_MASKValue:
0x7F
MSB bits of conversion mask, MSB of last conversion result register
SI7210_REG_DSPSIGM_DSPSIGM_SHIFT#
#define SI7210_REG_DSPSIGM_DSPSIGM_SHIFTValue:
0
MSB bits of conversion shift value, MSB of last conversion result register
SI7210_REG_POWER_CTRL_SLEEP_MASK#
#define SI7210_REG_POWER_CTRL_SLEEP_MASKValue:
0x01
Sleep mode bit mask, Power control register
SI7210_REG_POWER_CTRL_SLEEP_SHIFT#
#define SI7210_REG_POWER_CTRL_SLEEP_SHIFTValue:
0
Sleep mode bit shift value, Power control register
SI7210_REG_POWER_CTRL_STOP_MASK#
#define SI7210_REG_POWER_CTRL_STOP_MASKValue:
0x02
Stop bit mask, Power control register
SI7210_REG_POWER_CTRL_STOP_SHIFT#
#define SI7210_REG_POWER_CTRL_STOP_SHIFTValue:
1
Stop bit shift value, Power control register
SI7210_REG_POWER_CTRL_ONEBURST_MASK#
#define SI7210_REG_POWER_CTRL_ONEBURST_MASKValue:
0x04
One burst mesurement bit mask, Power control register
SI7210_REG_POWER_CTRL_ONEBURST_SHIFT#
#define SI7210_REG_POWER_CTRL_ONEBURST_SHIFTValue:
2
One burst mesurement bit shift value, Power control register
SI7210_REG_POWER_CTRL_USESTORE_MASK#
#define SI7210_REG_POWER_CTRL_USESTORE_MASKValue:
0x08
Save the current state of OTP regs bit mask, Power control register
SI7210_REG_POWER_CTRL_USESTORE_SHIFT#
#define SI7210_REG_POWER_CTRL_USESTORE_SHIFTValue:
3
Save the current state of OTP regs bit shift value, Power control register
SI7210_REG_POWER_CTRL_MEAS_MASK#
#define SI7210_REG_POWER_CTRL_MEAS_MASKValue:
0x80
Measurement in progress bit mask, Power control register
SI7210_REG_POWER_CTRL_MEAS_SHIFT#
#define SI7210_REG_POWER_CTRL_MEAS_SHIFTValue:
7
Measurement in progress bit shift value, Power control register
SI7210_REG_CTRL1_SW_OP_MASK#
#define SI7210_REG_CTRL1_SW_OP_MASKValue:
0x7F
Switching point mask, Control register 1
SI7210_REG_CTRL1_SW_OP_SHIFT#
#define SI7210_REG_CTRL1_SW_OP_SHIFTValue:
0
Switching point shift value, Control register 1
SI7210_REG_CTRL1_SW_LOW4FIELD_MASK#
#define SI7210_REG_CTRL1_SW_LOW4FIELD_MASKValue:
0x80
Output polarity setting bit mask, Control register 1
SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFT#
#define SI7210_REG_CTRL1_SW_LOW4FIELD_SHIFTValue:
7
Output polarity setting bit shift value, Control register 1
SI7210_REG_CTRL2_SW_HYST_MASK#
#define SI7210_REG_CTRL2_SW_HYST_MASKValue:
0x3F
Switch hysteresis mask, Control register 2
SI7210_REG_CTRL2_SW_HYST_SHIFT#
#define SI7210_REG_CTRL2_SW_HYST_SHIFTValue:
0
Switch hyteresis shift value, Control register 2
SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASK#
#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_MASKValue:
0xC0
Switch polarity mask, Control register 2
SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFT#
#define SI7210_REG_CTRL2_SW_FIELDPOLSEL_SHIFTValue:
6
Switchi polarity shift value, Control register 2
SI7210_REG_CTRL3_SLTIMEENA_MASK#
#define SI7210_REG_CTRL3_SLTIMEENA_MASKValue:
0x01
Sleep timer enable bit mask, Control register 3
SI7210_REG_CTRL3_SLTIMEENA_SHIFT#
#define SI7210_REG_CTRL3_SLTIMEENA_SHIFTValue:
0
Sleep timer enable bit shift value, Control register 3
SI7210_REG_CTRL3_SLFAST_MASK#
#define SI7210_REG_CTRL3_SLFAST_MASKValue:
0x02
Sleep time reduction enable bit mask, Control register 3
SI7210_REG_CTRL3_SLFAST_SHIFT#
#define SI7210_REG_CTRL3_SLFAST_SHIFTValue:
1
Sleep time reduction bit shift value, Control register 3
SI7210_REG_CTRL3_SW_TAMPER_MASK#
#define SI7210_REG_CTRL3_SW_TAMPER_MASKValue:
0xFC
Tamper switch threshold mask, Control register 3
SI7210_REG_CTRL3_SW_TAMPER_SHIFT#
#define SI7210_REG_CTRL3_SW_TAMPER_SHIFTValue:
2
Tamper switch threshold shift value, Control register 3
SI7210_REG_CTRL4_IIR_MASK#
#define SI7210_REG_CTRL4_IIR_MASKValue:
0x01
IIR filter enable bit mask, Control register 4
SI7210_REG_CTRL4_IIR_SHIFT#
#define SI7210_REG_CTRL4_IIR_SHIFTValue:
0
IIR filter enable bit shift value, Control register 4
SI7210_REG_CTRL4_DF_BW_MASK#
#define SI7210_REG_CTRL4_DF_BW_MASKValue:
0x1E
Number of samples to average mask, Control register 4
SI7210_REG_CTRL4_DF_BW_SHIFT#
#define SI7210_REG_CTRL4_DF_BW_SHIFTValue:
1
Number of samples to average shift value, Control register 4
SI7210_REG_CTRL4_DF_BURSTSIZE_MASK#
#define SI7210_REG_CTRL4_DF_BURSTSIZE_MASKValue:
0x0E
Measurement burst size mask, Control register 4
SI7210_REG_CTRL4_DF_BURSTSIZE_SHIFT#
#define SI7210_REG_CTRL4_DF_BURSTSIZE_SHIFTValue:
5
Measurement burst size shift value, Control register 4
SI7210_REG_OTP_CTRL_BUSY_MASK#
#define SI7210_REG_OTP_CTRL_BUSY_MASKValue:
0x01
OTP busy indicator bit mask, OTP read control register
SI7210_REG_OTP_CTRL_BUSY_SHIFT#
#define SI7210_REG_OTP_CTRL_BUSY_SHIFTValue:
0
OTP busy indicator bit shift value, OTP read control register
SI7210_REG_OTP_CTRL_READ_EN_MASK#
#define SI7210_REG_OTP_CTRL_READ_EN_MASKValue:
0x02
OTP read enable bit mask, OTP read control register
SI7210_REG_OTP_CTRL_READ_EN_SHIFT#
#define SI7210_REG_OTP_CTRL_READ_EN_SHIFTValue:
1
OTP read enable bit shift value, OTP read control register
SI7210_OTP_ADDR_CTRL1#
#define SI7210_OTP_ADDR_CTRL1Value:
0x04
OTP Control register 1, output pin configuration
SI7210_OTP_ADDR_CTRL2#
#define SI7210_OTP_ADDR_CTRL2Value:
0x05
OTP Control register 2, output pin configuration
SI7210_OTP_ADDR_CTRL3#
#define SI7210_OTP_ADDR_CTRL3Value:
0x08
OTP Control register 3, output pin and sleep time configuration
SI7210_OTP_ADDR_CTRL4#
#define SI7210_OTP_ADDR_CTRL4Value:
0x0C
OTP Control register 4, Digital filter configuration
SI7210_OTP_ADDR_BASE_PART_NUMBER#
#define SI7210_OTP_ADDR_BASE_PART_NUMBERValue:
0x14
OTP Base part number
SI7210_OTP_ADDR_BPERVCAL#
#define SI7210_OTP_ADDR_BPERVCALValue:
0x20
OTP On-chip field generator calibration value
SI7210_OTP_ADDR_COEFFS_20MT#
#define SI7210_OTP_ADDR_COEFFS_20MTValue:
0x21
OTP 20mT scale no magnet temperature compensation value
SI7210_OTP_ADDR_COEFFS_200MT#
#define SI7210_OTP_ADDR_COEFFS_200MTValue:
0x27
OTP 200mT scale no magnet temperature compensation value
SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUM#
#define SI7210_OTP_ADDR_COEFFS_20MT_NEODYMIUMValue:
0x2D
OTP 20mT scale neodymium magnet temperature compensation value
SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUM#
#define SI7210_OTP_ADDR_COEFFS_200MT_NEODYMIUMValue:
0x33
OTP 200mT scale neodymium temperature compensation value
SI7210_OTP_ADDR_COEFFS_20MT_CERAMIC#
#define SI7210_OTP_ADDR_COEFFS_20MT_CERAMICValue:
0x39
OTP 20mT scale ceramic magnet temperature compensation value
SI7210_OTP_ADDR_COEFFS_200MT_CERAMIC#
#define SI7210_OTP_ADDR_COEFFS_200MT_CERAMICValue:
0x3F
OTP 200mT scale ceramic magnet temperature compensation value
Function Documentation#
sl_si7210_read_otp_register#
sl_status_t sl_si7210_read_otp_register (sl_i2cspm_t * i2cspm, uint8_t otpAddr, uint8_t * otpData)
Read register from the OTP area of the Si7021 device.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| sl_i2cspm_t * | [in] | i2cspm | The I2CSPM instance to use. |
| uint8_t | [in] | otpAddr | The register address to read from in the sensor |
| uint8_t * | [out] | otpData | The data read from the device |
sl_si7210_read_register#
sl_status_t sl_si7210_read_register (sl_i2cspm_t * i2cspm, uint8_t addr, uint8_t * data)
Read register from the Hall sensor device.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| sl_i2cspm_t * | [in] | i2cspm | The I2CSPM instance to use. |
| uint8_t | [in] | addr | The register address to read from in the sensor |
| uint8_t * | [out] | data | The data read from the device |
sl_si7210_write_register#
sl_status_t sl_si7210_write_register (sl_i2cspm_t * i2cspm, uint8_t addr, uint8_t data)
Write a register in the Hall sensor device.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| sl_i2cspm_t * | [in] | i2cspm | The I2CSPM instance to use. |
| uint8_t | [in] | addr | The register address to write |
| uint8_t | [in] | data | The data to write to the register |
sl_si7210_set_register_bits#
sl_status_t sl_si7210_set_register_bits (sl_i2cspm_t * i2cspm, uint8_t addr, uint8_t mask)
Set the given bit(s) in a register in the Hall sensor device.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| sl_i2cspm_t * | [in] | i2cspm | The I2CSPM instance to use. |
| uint8_t | [in] | addr | The address of the register |
| uint8_t | [in] | mask | The mask specifies which bits should be set. If a given bit of the mask is 1, that register bit will be set to 1. All the other register bits will be untouched. |
sl_si7210_clear_register_bits#
sl_status_t sl_si7210_clear_register_bits (sl_i2cspm_t * i2cspm, uint8_t addr, uint8_t mask)
Clear the given bit(s) in a register in the Hall sensor device.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| sl_i2cspm_t * | [in] | i2cspm | The I2CSPM instance to use. |
| uint8_t | [in] | addr | The address of the register |
| uint8_t | [in] | mask | The mask specifies which bits should be clear. If a given bit of the mask is 1 that register bit will be cleared to 0. All the other register bits will be untouched. |
sl_si7210_calculate_sw_op#
uint8_t sl_si7210_calculate_sw_op (float threshold)
Calculate the sw_op value from the threshold by finding the inverse of the formula: threshold = (16 + sw_op[3:0]) * 2^sw_op[6:4].
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| float | [in] | threshold | Threshold value |
Returns
The value of the sw_op bitfield
sl_si7210_calculate_sw_hyst#
uint8_t sl_si7210_calculate_sw_hyst (float hysteresis, bool scale200mT)
Calculate the sw_hyst value from the hysteresis by finding the inverse of the formula: hysteresis = (8 + sw_hyst[2:0]) * 2^sw_hyst[5:3].
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| float | [in] | hysteresis | Hysteresis value |
| bool | [in] | scale200mT | scale200mT=false : full-scale equals 20mT scale200mT=true : full-scale equals 200mT |
Returns
The value of the sw_hyst bitfield
sl_si7210_calculate_sw_tamper#
uint8_t sl_si7210_calculate_sw_tamper (float tamper, bool scale200mT)
Calculate the sw_tamper value from the tamper threshold by finding the inverse of the formula: tamper = (16 + sw_tamper[3:0]) * 2^(sw_tamper[5:4] + 5)
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| float | [in] | tamper | scale200mT=false : full-scale equals 20mT scale200mT=true : full-scale equals 200mT |
| bool | N/A | scale200mT |
Returns
The value of the sw_tamper bitfield
sl_si7210_calculate_sltime#
uint8_t sl_si7210_calculate_sltime (uint32_t samplePeriod, uint8_t * slFast)
Calculate the slTime value from the sleep time by finding the inverse of the formula: tsleep = (32 + slTime[4:0]) * 2^(8 + slTime[7:5]) / 12 MHz.
| Type | Direction | Argument Name | Description |
|---|---|---|---|
| uint32_t | [in] | samplePeriod | The sleep time |
| uint8_t * | [out] | slFast | The value of the slFast bit |
Returns
The value of the slTime bitfield