ADC - Analog to Digital Converter#


Introduction#

This module provides a hardware abstraction layer (HAL) interface to the ADC peripheral. It allows the user to initialize and configure the ADC to perform one or more conversions triggered immediately or continuously. The ADC stores its conversion results as a FIFO. Additionally, the ADC can be triggered by an external event or by a timer event.

For more details on the ADC initialization and configuration options available, please refer to the following structures and their corresponding attributes:


Example#

The following code snippet is an example of how to configure the ADC peripheral to perform a single immediate conversion:

{
  // Enable ADC bus clock.
  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_ADC0);

  // Get clock branch frequency to configure the ADC.
  sl_clock_branch_t clock_branch;
  uint32_t branch_clock_freq;
  clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_ADC0);
  sl_clock_manager_get_clock_branch_frequency(clock_branch, &branch_clock_freq);

  sl_hal_adc_scan_entry_t entry = SL_HAL_ADC_SCAN_ENTRY_DEFAULT;
  entry.pos_port = SL_HAL_ADC_PORT_POS_PORTA;
  entry.pos_pin = 0;

  sl_hal_adc_init_t init = SL_HAL_ADC_INIT_DEFAULT;
  init.scan_trigger = SL_HAL_ADC_TRIGGER_IMMEDIATE;
  init.scan_trigger_action = SL_HAL_ADC_TRIGGER_ACTION_ONCE;

  sl_hal_adc_config_t config = SL_HAL_ADC_CONFIG_DEFAULT;
  config.acquisition_time = 16;

  init.entries[SL_HAL_ADC_CHANNEL_ID_0] = entry;

  sl_hal_adc_reset(ADC0);
  sl_hal_adc_enable_interrupts(ADC0, ADC_IF_SCANENTRYDONE);

  init.config[SL_HAL_ADC_CONFIG_ID_0] = config;

  sl_hal_adc_init(ADC0, &init, branch_clock_freq);
  sl_hal_adc_enable(ADC0);

  sl_hal_adc_flush_fifo(ADC0);
  while (sl_hal_adc_get_status(ADC0) & ADC_STATUS_SCANFIFOFLUSHING) ;

  uint32_t scan_mask = 1U << SL_HAL_ADC_CONFIG_ID_0;
  sl_hal_adc_set_scan_mask(ADC0, scan_mask);

  sl_hal_adc_result_t result;

  // Trigger scan and pull results from fifo.
  sl_hal_adc_start(ADC0);
  while (!sl_hal_adc_get_enabled_pending_interrupts(ADC0)) ;

  result = sl_hal_adc_pull(ADC0);

  sl_hal_adc_clear_interrupts(ADC0, ADC_IF_SCANENTRYDONE);
}

Hardware Limitations and Workarounds#

Continuous Single Channel Conversion Generates Invalid Accumulation Results#

Description#

When the ADC continuously scans a single channel under certain conditions, the conversion results are incorrectly accumulated.

The conversion result is invalid if all of the following conditions are met:

  • One channel is being converted in the scan sequence.

  • ADC is performing continuous conversions

    • ADC init structure's scan_trigger_action is set to SL_HAL_ADC_TRIGGER_ACTION_CONTINUOUS.

  • ADC is accumulating 4 or more conversions per output

    • ADC configuration structure's average is set to SL_HAL_ADC_AVERAGE_X4 or higher.

  • Scan repetition delay is disabled

    • ADC init structure's repetition_delay is set to SL_HAL_ADC_DELAY_NO.

  • The internal ADC clocks CLK_CORE_ADC and CLK_SRC_ADC are equal

Workaround#

There are two workarounds:

  • Enable scan repetition delay by setting the ADC init structure's repetition_delay to any option other than SL_HAL_ADC_DELAY_NO.

  • Configure CLK_SRC_ADC to be twice the frequency of CLK_CORE_ADC

Modules#

sl_hal_adc_config_t

sl_hal_adc_scan_entry_t

sl_hal_adc_init_t

sl_hal_adc_result_t

Enumerations#

enum
SL_HAL_ADC_WARMUP_NORMAL = _ADC_CTRL_WARMUPMODE_NORMAL
SL_HAL_ADC_WARMUP_KEEPWARM = _ADC_CTRL_WARMUPMODE_KEEPWARM
SL_HAL_ADC_WARMUP_KEEPSTANDBY = _ADC_CTRL_WARMUPMODE_KEEPSTANDBY
}

Warm-up mode.

enum
SL_HAL_ADC_REFERENCE_VREFINT = _ADC_CTRL_REFSEL_VREFINT
SL_HAL_ADC_REFERENCE_VREFPL = _ADC_CTRL_REFSEL_VREFPL
SL_HAL_ADC_REFERENCE_VREFPH = _ADC_CTRL_REFSEL_VREFPH
SL_HAL_ADC_REFERENCE_VDDA = _ADC_CTRL_REFSEL_VDDA
SL_HAL_ADC_REFERENCE_VREFPBUF = _ADC_CTRL_REFSEL_VREFPBUF
}

Voltage reference.

enum
SL_HAL_ADC_HSCLKRATE_DIV1 = _ADC_CTRL_HSCLKRATE_DIV1
SL_HAL_ADC_HSCLKRATE_DIV2 = _ADC_CTRL_HSCLKRATE_DIV2
SL_HAL_ADC_HSCLKRATE_DIV3 = _ADC_CTRL_HSCLKRATE_DIV3
SL_HAL_ADC_HSCLKRATE_DIV4 = _ADC_CTRL_HSCLKRATE_DIV4
SL_HAL_ADC_HSCLKRATE_DIV5 = _ADC_CTRL_HSCLKRATE_DIV5
SL_HAL_ADC_HSCLKRATE_DIV6 = _ADC_CTRL_HSCLKRATE_DIV6
SL_HAL_ADC_HSCLKRATE_DIV7 = _ADC_CTRL_HSCLKRATE_DIV7
SL_HAL_ADC_HSCLKRATE_DIV8 = _ADC_CTRL_HSCLKRATE_DIV8
}

First clock divider.

enum
SL_HAL_ADC_TRIGGER_IMMEDIATE = _ADC_TRIGGER_SCANTRIGSEL_IMMEDIATE
SL_HAL_ADC_TRIGGER_TIMER = _ADC_TRIGGER_SCANTRIGSEL_TIMER
SL_HAL_ADC_TRIGGER_PRSCLKGRP = _ADC_TRIGGER_SCANTRIGSEL_PRSCLKGRP
SL_HAL_ADC_TRIGGER_PRSPOS = _ADC_TRIGGER_SCANTRIGSEL_PRSPOS
SL_HAL_ADC_TRIGGER_PRSNEG = _ADC_TRIGGER_SCANTRIGSEL_PRSNEG
}

ADC scan trigger.

enum
SL_HAL_ADC_TRIGGER_ACTION_ONCE = _ADC_TRIGGER_SCANTRIGACTION_ONCE
SL_HAL_ADC_TRIGGER_ACTION_CONTINUOUS = _ADC_TRIGGER_SCANTRIGACTION_CONTINUOUS
}

ADC scan trigger action.

enum
SL_HAL_ADC_DELAY_NO = _ADC_TRIGGER_REPDELAY_NODELAY
SL_HAL_ADC_DELAY_CYCLES_2 = _ADC_TRIGGER_REPDELAY_CYCLE2
SL_HAL_ADC_DELAY_CYCLES_4 = _ADC_TRIGGER_REPDELAY_CYCLE4
SL_HAL_ADC_DELAY_CYCLES_8 = _ADC_TRIGGER_REPDELAY_CYCLE8
SL_HAL_ADC_DELAY_CYCLES_16 = _ADC_TRIGGER_REPDELAY_CYCLE16
SL_HAL_ADC_DELAY_CYCLES_32 = _ADC_TRIGGER_REPDELAY_CYCLE32
SL_HAL_ADC_DELAY_CYCLES_64 = _ADC_TRIGGER_REPDELAY_CYCLE64
SL_HAL_ADC_DELAY_CYCLES_128 = _ADC_TRIGGER_REPDELAY_CYCLE128
SL_HAL_ADC_DELAY_CYCLES_256 = _ADC_TRIGGER_REPDELAY_CYCLE256
SL_HAL_ADC_DELAY_CYCLES_512 = _ADC_TRIGGER_REPDELAY_CYCLE512
SL_HAL_ADC_DELAY_CYCLES_1024 = _ADC_TRIGGER_REPDELAY_CYCLE1024
}

Delay value between one sequence of the table and the next start of sequence.

enum
SL_HAL_ADC_ANALOG_GAIN_0_3125 = _ADC_CFG_ANALOGGAIN_GAIN_0_3125
SL_HAL_ADC_ANALOG_GAIN_0_5 = _ADC_CFG_ANALOGGAIN_GAIN_0_5
SL_HAL_ADC_ANALOG_GAIN_1 = _ADC_CFG_ANALOGGAIN_GAIN_1
SL_HAL_ADC_ANALOG_GAIN_2 = _ADC_CFG_ANALOGGAIN_GAIN_2
SL_HAL_ADC_ANALOG_GAIN_4 = _ADC_CFG_ANALOGGAIN_GAIN_4
}

Analog gain.

enum
SL_HAL_ADC_AVERAGE_X1 = _ADC_CFG_AVERAGESEL_X1
SL_HAL_ADC_AVERAGE_X2 = _ADC_CFG_AVERAGESEL_X2
SL_HAL_ADC_AVERAGE_X4 = _ADC_CFG_AVERAGESEL_X4
SL_HAL_ADC_AVERAGE_X8 = _ADC_CFG_AVERAGESEL_X8
SL_HAL_ADC_AVERAGE_X16 = _ADC_CFG_AVERAGESEL_X16
SL_HAL_ADC_AVERAGE_X32 = _ADC_CFG_AVERAGESEL_X32
SL_HAL_ADC_AVERAGE_X64 = _ADC_CFG_AVERAGESEL_X64
SL_HAL_ADC_AVERAGE_X128 = _ADC_CFG_AVERAGESEL_X128
SL_HAL_ADC_AVERAGE_X256 = _ADC_CFG_AVERAGESEL_X256
SL_HAL_ADC_AVERAGE_X512 = _ADC_CFG_AVERAGESEL_X512
SL_HAL_ADC_AVERAGE_X1024 = _ADC_CFG_AVERAGESEL_X1024
}

Number of samples used for averaging.

enum
SL_HAL_ADC_ALIGNMENT_RIGHT_16 = _ADC_SCANFIFOCFG_ALIGNMENT_RIGHT16
SL_HAL_ADC_ALIGNMENT_RIGHT_12 = _ADC_SCANFIFOCFG_ALIGNMENT_RIGHT12
SL_HAL_ADC_ALIGNMENT_RIGHT_8 = _ADC_SCANFIFOCFG_ALIGNMENT_RIGHT8
SL_HAL_ADC_ALIGNMENT_LEFT_16 = _ADC_SCANFIFOCFG_ALIGNMENT_LEFT16
SL_HAL_ADC_ALIGNMENT_LEFT_12 = _ADC_SCANFIFOCFG_ALIGNMENT_LEFT12
SL_HAL_ADC_ALIGNMENT_LEFT_8 = _ADC_SCANFIFOCFG_ALIGNMENT_LEFT8
}

Alignment of output data written into FIFO.

enum
SL_HAL_ADC_DATA_VALID_1 = _ADC_SCANFIFOCFG_DVL_VALID1
SL_HAL_ADC_DATA_VALID_2 = _ADC_SCANFIFOCFG_DVL_VALID2
SL_HAL_ADC_DATA_VALID_3 = _ADC_SCANFIFOCFG_DVL_VALID3
SL_HAL_ADC_DATA_VALID_4 = _ADC_SCANFIFOCFG_DVL_VALID4
SL_HAL_ADC_DATA_VALID_5 = _ADC_SCANFIFOCFG_DVL_VALID5
SL_HAL_ADC_DATA_VALID_6 = _ADC_SCANFIFOCFG_DVL_VALID6
SL_HAL_ADC_DATA_VALID_7 = _ADC_SCANFIFOCFG_DVL_VALID7
SL_HAL_ADC_DATA_VALID_8 = _ADC_SCANFIFOCFG_DVL_VALID8
SL_HAL_ADC_DATA_VALID_9 = _ADC_SCANFIFOCFG_DVL_VALID9
SL_HAL_ADC_DATA_VALID_10 = _ADC_SCANFIFOCFG_DVL_VALID10
SL_HAL_ADC_DATA_VALID_11 = _ADC_SCANFIFOCFG_DVL_VALID11
SL_HAL_ADC_DATA_VALID_12 = _ADC_SCANFIFOCFG_DVL_VALID12
SL_HAL_ADC_DATA_VALID_13 = _ADC_SCANFIFOCFG_DVL_VALID13
SL_HAL_ADC_DATA_VALID_14 = _ADC_SCANFIFOCFG_DVL_VALID14
SL_HAL_ADC_DATA_VALID_15 = _ADC_SCANFIFOCFG_DVL_VALID15
SL_HAL_ADC_DATA_VALID_16 = _ADC_SCANFIFOCFG_DVL_VALID16
}

Data valid level before requesting DMA transfer.

enum
SL_HAL_ADC_PORT_NEG_GND = _ADC_SCAN_PORTNEG_GND
SL_HAL_ADC_PORT_NEG_PORTA = _ADC_SCAN_PORTNEG_PORTA
SL_HAL_ADC_PORT_NEG_PORTB = _ADC_SCAN_PORTNEG_PORTB
SL_HAL_ADC_PORT_NEG_PORTC = _ADC_SCAN_PORTNEG_PORTC
SL_HAL_ADC_PORT_NEG_PORTD = _ADC_SCAN_PORTNEG_PORTD
}

Port (A, B, C, D) or special signal assigned to the negative input of the ADC.

enum
SL_HAL_ADC_PORT_POS_GND = _ADC_SCAN_PORTPOS_GND
SL_HAL_ADC_PORT_POS_SUPPLY = _ADC_SCAN_PORTPOS_SUPPLY
SL_HAL_ADC_PORT_POS_PORTA = _ADC_SCAN_PORTPOS_PORTA
SL_HAL_ADC_PORT_POS_PORTB = _ADC_SCAN_PORTPOS_PORTB
SL_HAL_ADC_PORT_POS_PORTC = _ADC_SCAN_PORTPOS_PORTC
SL_HAL_ADC_PORT_POS_PORTD = _ADC_SCAN_PORTPOS_PORTD
}

Port (A, B, C, D) or special signal assigned to the positive input of the ADC.

enum
SL_HAL_ADC_CONFIG_ID_0 = 0U
SL_HAL_ADC_CONFIG_ID_1
SL_HAL_ADC_CONFIG_ID_MAX
}

Configuration identifier.

enum
SL_HAL_ADC_CHANNEL_ID_0 = 0U
SL_HAL_ADC_CHANNEL_ID_1
SL_HAL_ADC_CHANNEL_ID_2
SL_HAL_ADC_CHANNEL_ID_3
SL_HAL_ADC_CHANNEL_ID_4
SL_HAL_ADC_CHANNEL_ID_5
SL_HAL_ADC_CHANNEL_ID_6
SL_HAL_ADC_CHANNEL_ID_7
SL_HAL_ADC_CHANNEL_ID_8
SL_HAL_ADC_CHANNEL_ID_9
SL_HAL_ADC_CHANNEL_ID_10
SL_HAL_ADC_CHANNEL_ID_11
SL_HAL_ADC_CHANNEL_ID_12
SL_HAL_ADC_CHANNEL_ID_13
SL_HAL_ADC_CHANNEL_ID_14
SL_HAL_ADC_CHANNEL_ID_15
SL_HAL_ADC_CHANNEL_ID_MAX
}

Channel identifier.

Functions#

void
sl_hal_adc_init(ADC_TypeDef *adc, const sl_hal_adc_init_t *init, uint32_t branch_clock_freq)

Initialize the ADC.

void
sl_hal_adc_reset(ADC_TypeDef *adc)

Reset the ADC.

void
sl_hal_adc_set_scan_mask(ADC_TypeDef *adc, uint32_t mask)

Set a new Scan Table mask.

uint32_t
sl_hal_adc_get_scan_mask(ADC_TypeDef *adc)

Get the working scan table mask.

void
sl_hal_adc_update_scan_entry(ADC_TypeDef *adc, uint8_t id, const sl_hal_adc_scan_entry_t *entry)

Update an entry in the scan table.

sl_hal_adc_pull(const ADC_TypeDef *adc)

Pull the value at the top of the FIFO.

sl_hal_adc_peek(const ADC_TypeDef *adc)

Peek at the top of the FIFO without removing the data.

uint32_t
sl_hal_adc_get_fifo_count(const ADC_TypeDef *adc)

Get the ADC's current FIFO count.

uint32_t

Get the ADC's internal reference voltage in millivolts.

uint32_t
sl_hal_adc_get_timer_frequency(const ADC_TypeDef *adc, uint32_t branch_clock_freq)

Calculate and return the clock frequency of the ADC's local timer.

void
sl_hal_adc_set_timer_period(ADC_TypeDef *adc, uint16_t timer_period)

Set the timer period to periodically trigger a timer event.

void
sl_hal_adc_set_clock_prescalers(ADC_TypeDef *adc, uint32_t branch_clock_freq, uint8_t hsclkrate, uint8_t adcprescale)

Set both ADC prescalers.

void
sl_hal_adc_enable(ADC_TypeDef *adc)

Enable the ADC.

void
sl_hal_adc_disable(ADC_TypeDef *adc)

Disable the ADC.

void
sl_hal_adc_start(ADC_TypeDef *adc)

Start the ADC.

void
sl_hal_adc_stop(ADC_TypeDef *adc)

Stop the ADC.

void
sl_hal_adc_enable_timer(ADC_TypeDef *adc)

Enable the ADC's local timer.

void
sl_hal_adc_disable_timer(ADC_TypeDef *adc)

Disable the ADC's local timer and resets the counter.

void
sl_hal_adc_flush_fifo(ADC_TypeDef *adc)

Flush the scan FIFO.

void
sl_hal_adc_wait_sync(ADC_TypeDef *adc)

Wait for ongoing sync of register(s) to the low-frequency domain to complete.

void
sl_hal_adc_wait_ready(ADC_TypeDef *adc)

Wait for disabling to finish.

uint32_t
sl_hal_adc_get_status(ADC_TypeDef *adc)

Return the content of the status register.

void
sl_hal_adc_enable_interrupts(ADC_TypeDef *adc, uint32_t flags)

Enable one or more ADC interrupts.

void
sl_hal_adc_disable_interrupts(ADC_TypeDef *adc, uint32_t flags)

Disable one or more ADC interrupts.

void
sl_hal_adc_clear_interrupts(ADC_TypeDef *adc, uint32_t flags)

Clear one or more pending ADC interrupts.

void
sl_hal_adc_set_interrupts(ADC_TypeDef *adc, uint32_t flags)

Set one or more pending ADC interrupts from software.

uint32_t

Get pending ADC interrupt flags.

uint32_t

Get enabled and pending ADC interrupt flags.

Macros#

#define
SL_HAL_ADC_REF_VALID (ref)

Validation of the ADC register block pointer reference for assert statements.

#define
SL_HAL_ADC_INIT_DEFAULT undefined

Default ADC initialization structure.

#define
SL_HAL_ADC_CONFIG_DEFAULT undefined

Default ADC config structure.

#define
SL_HAL_ADC_SCAN_ENTRY_DEFAULT undefined

Default ADC scan entry structure.

Enumeration Documentation#

sl_hal_adc_warmup_mode_t#

sl_hal_adc_warmup_mode_t

Warm-up mode.

Enumerator
SL_HAL_ADC_WARMUP_NORMAL

Shut down the ADC after conversions have completed.

SL_HAL_ADC_WARMUP_KEEPWARM

Keep the ADC fully powered after conversions have completed.

SL_HAL_ADC_WARMUP_KEEPSTANDBY

Allow the ADC to have 1us warmup instead of 5us after the first conversion.


sl_hal_adc_voltage_reference_t#

sl_hal_adc_voltage_reference_t

Voltage reference.

Enumerator
SL_HAL_ADC_REFERENCE_VREFINT

Internal voltage reference.

SL_HAL_ADC_REFERENCE_VREFPL

External reference pin low voltage (1.05-1.25).

SL_HAL_ADC_REFERENCE_VREFPH

External reference pin high voltage (>1.25).

SL_HAL_ADC_REFERENCE_VDDA

Analog voltage supply.

SL_HAL_ADC_REFERENCE_VREFPBUF

External reference pin buffered.


sl_hal_adc_high_speed_clock_rate_t#

sl_hal_adc_high_speed_clock_rate_t

First clock divider.

Enumerator
SL_HAL_ADC_HSCLKRATE_DIV1

Use clk_per directly.

SL_HAL_ADC_HSCLKRATE_DIV2

Divide clk_per by 2.

SL_HAL_ADC_HSCLKRATE_DIV3

Divide clk_per by 3.

SL_HAL_ADC_HSCLKRATE_DIV4

Divide clk_per by 4.

SL_HAL_ADC_HSCLKRATE_DIV5

Divide clk_per by 5.

SL_HAL_ADC_HSCLKRATE_DIV6

Divide clk_per by 6.

SL_HAL_ADC_HSCLKRATE_DIV7

Divide clk_per by 7.

SL_HAL_ADC_HSCLKRATE_DIV8

Divide clk_per by 8.


sl_hal_adc_trigger_t#

sl_hal_adc_trigger_t

ADC scan trigger.

Enumerator
SL_HAL_ADC_TRIGGER_IMMEDIATE

Start scan queue immediately.

SL_HAL_ADC_TRIGGER_TIMER

Timer starts scan queue.

SL_HAL_ADC_TRIGGER_PRSCLKGRP

PRS0 from timer in same clock group starts scan queue.

SL_HAL_ADC_TRIGGER_PRSPOS

PRS0 positive edge starts scan queue.

SL_HAL_ADC_TRIGGER_PRSNEG

PRS0 negative edge starts scan queue.


sl_hal_adc_trigger_action_t#

sl_hal_adc_trigger_action_t

ADC scan trigger action.

Enumerator
SL_HAL_ADC_TRIGGER_ACTION_ONCE

Once per trigger.

SL_HAL_ADC_TRIGGER_ACTION_CONTINUOUS

Continuously after trigger.


sl_hal_adc_repetition_delay_t#

sl_hal_adc_repetition_delay_t

Delay value between one sequence of the table and the next start of sequence.

Enumerator
SL_HAL_ADC_DELAY_NO

No delay.

SL_HAL_ADC_DELAY_CYCLES_2

2 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_4

4 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_8

8 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_16

16 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_32

32 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_64

64 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_128

128 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_256

256 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_512

512 conversion clock cycles.

SL_HAL_ADC_DELAY_CYCLES_1024

1024 conversion clock cycles.


sl_hal_adc_analog_gain_t#

sl_hal_adc_analog_gain_t

Analog gain.

Enumerator
SL_HAL_ADC_ANALOG_GAIN_0_3125

Gain for sampling cap of 0.3125x.

SL_HAL_ADC_ANALOG_GAIN_0_5

Gain for sampling cap of 0.5x.

SL_HAL_ADC_ANALOG_GAIN_1

Gain for sampling cap of 1x.

SL_HAL_ADC_ANALOG_GAIN_2

Gain for sampling cap of 2x.

SL_HAL_ADC_ANALOG_GAIN_4

Gain for sampling cap of 3x.


sl_hal_adc_samples_t#

sl_hal_adc_samples_t

Number of samples used for averaging.

Enumerator
SL_HAL_ADC_AVERAGE_X1

1 sample for each conversion result.

SL_HAL_ADC_AVERAGE_X2

2 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X4

4 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X8

8 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X16

16 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X32

32 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X64

64 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X128

128 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X256

256 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X512

512 samples for each conversion result.

SL_HAL_ADC_AVERAGE_X1024

1024 samples for each conversion result.


sl_hal_adc_alignment_t#

sl_hal_adc_alignment_t

Alignment of output data written into FIFO.

Enumerator
SL_HAL_ADC_ALIGNMENT_RIGHT_16

ID[7:0], SIGN_EXT, DATA[15:0].

SL_HAL_ADC_ALIGNMENT_RIGHT_12

ID[7:0], SIGN_EXT, DATA[11:0].

SL_HAL_ADC_ALIGNMENT_RIGHT_8

ID[7:0], SIGN_EXT, DATA[7:0].

SL_HAL_ADC_ALIGNMENT_LEFT_16

DATA[15:0], 00000000, ID[7:0].

SL_HAL_ADC_ALIGNMENT_LEFT_12

DATA[11:0], 000000000000, ID[7:0].

SL_HAL_ADC_ALIGNMENT_LEFT_8

DATA[7:0], 0000000000000000, ID[7:0].


sl_hal_adc_data_valid_t#

sl_hal_adc_data_valid_t

Data valid level before requesting DMA transfer.

Enumerator
SL_HAL_ADC_DATA_VALID_1

1 valid entry to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_2

2 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_3

3 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_4

4 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_5

5 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_6

6 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_7

7 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_8

8 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_9

9 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_10

10 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_11

11 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_12

12 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_13

13 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_14

14 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_15

15 valid entries to set SCANFIFODVL interrupt.

SL_HAL_ADC_DATA_VALID_16

16 valid entries to set SCANFIFODVL interrupt.


sl_hal_adc_port_negative_t#

sl_hal_adc_port_negative_t

Port (A, B, C, D) or special signal assigned to the negative input of the ADC.

Enumerator
SL_HAL_ADC_PORT_NEG_GND

Ground.

SL_HAL_ADC_PORT_NEG_PORTA

Port A.

SL_HAL_ADC_PORT_NEG_PORTB

Port B.

SL_HAL_ADC_PORT_NEG_PORTC

Port C.

SL_HAL_ADC_PORT_NEG_PORTD

Port D.


sl_hal_adc_port_positive_t#

sl_hal_adc_port_positive_t

Port (A, B, C, D) or special signal assigned to the positive input of the ADC.

Enumerator
SL_HAL_ADC_PORT_POS_GND

Ground.

SL_HAL_ADC_PORT_POS_SUPPLY

Supply.

SL_HAL_ADC_PORT_POS_PORTA

Port A.

SL_HAL_ADC_PORT_POS_PORTB

Port B.

SL_HAL_ADC_PORT_POS_PORTC

Port C.

SL_HAL_ADC_PORT_POS_PORTD

Port D.


sl_hal_adc_config_id_t#

sl_hal_adc_config_id_t

Configuration identifier.

Enumerator
SL_HAL_ADC_CONFIG_ID_0
SL_HAL_ADC_CONFIG_ID_1
SL_HAL_ADC_CONFIG_ID_MAX

sl_hal_adc_channel_id_t#

sl_hal_adc_channel_id_t

Channel identifier.

Enumerator
SL_HAL_ADC_CHANNEL_ID_0
SL_HAL_ADC_CHANNEL_ID_1
SL_HAL_ADC_CHANNEL_ID_2
SL_HAL_ADC_CHANNEL_ID_3
SL_HAL_ADC_CHANNEL_ID_4
SL_HAL_ADC_CHANNEL_ID_5
SL_HAL_ADC_CHANNEL_ID_6
SL_HAL_ADC_CHANNEL_ID_7
SL_HAL_ADC_CHANNEL_ID_8
SL_HAL_ADC_CHANNEL_ID_9
SL_HAL_ADC_CHANNEL_ID_10
SL_HAL_ADC_CHANNEL_ID_11
SL_HAL_ADC_CHANNEL_ID_12
SL_HAL_ADC_CHANNEL_ID_13
SL_HAL_ADC_CHANNEL_ID_14
SL_HAL_ADC_CHANNEL_ID_15
SL_HAL_ADC_CHANNEL_ID_MAX

Function Documentation#

sl_hal_adc_init#

void sl_hal_adc_init (ADC_TypeDef * adc, const sl_hal_adc_init_t * init, uint32_t branch_clock_freq)

Initialize the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

const sl_hal_adc_init_t *[in]init

A pointer to the ADC initialization structure.

uint32_t[in]branch_clock_freq

Incoming peripheral frequency. Should be retrieved using the Clock Manager service.

Note

  • The ADC peripheral's internal clock prescalers and timebase will be set to sensible defaults according to the input parameter branch_clock_freq provided. These default prescalers can be modified using sl_hal_adc_set_clock_prescalers. The branch_clock_freq can be obtained for adc0 using the Device Manager and Clock Manager services as such:

    {
      #include "sl_clock_manager.h"
      #include "sl_device_peripheral.h"
    
      sl_clock_branch_t clock_branch;
      clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_ADC0);
    
      uint32_t branch_clock_freq;
      sl_clock_manager_get_clock_branch_frequency(clock_branch, &branch_clock_freq);
    }
    
  • For SiXG301, due to hardware limitations, the ADC cannot be configured for hardware averaging if the adcprescale is 0 (divide by 1). If hardware averaging is desired, then an adc0 branch_clock_freq of 34 - 40Mhz, 68 - 80Mhz, 102 - 120Mhz or 136 - 160Mhz can be used to guarantee that the calculated adcprescale is 1.


sl_hal_adc_reset#

void sl_hal_adc_reset (ADC_TypeDef * adc)

Reset the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_set_scan_mask#

void sl_hal_adc_set_scan_mask (ADC_TypeDef * adc, uint32_t mask)

Set a new Scan Table mask.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

uint32_t[in]mask

New scan table mask.

Note

  • The working scan table is updated when it's not being scanned. Each bit in the mask corresponds to a given ADC channel, and setting a given bit to 1 will enable the conversion of the respective ADC channel.


sl_hal_adc_get_scan_mask#

uint32_t sl_hal_adc_get_scan_mask (ADC_TypeDef * adc)

Get the working scan table mask.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Returns

  • The working scan table mask.


sl_hal_adc_update_scan_entry#

void sl_hal_adc_update_scan_entry (ADC_TypeDef * adc, uint8_t id, const sl_hal_adc_scan_entry_t * entry)

Update an entry in the scan table.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

uint8_t[in]id

ID of scan table entry to add.

const sl_hal_adc_scan_entry_t *[in]entry

A pointer to a Scan Table entry structure.


sl_hal_adc_pull#

sl_hal_adc_result_t sl_hal_adc_pull (const ADC_TypeDef * adc)

Pull the value at the top of the FIFO.

Parameters
TypeDirectionArgument NameDescription
const ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

FIFO count reduced.

Returns

  • The data at the top of the FIFO.


sl_hal_adc_peek#

sl_hal_adc_result_t sl_hal_adc_peek (const ADC_TypeDef * adc)

Peek at the top of the FIFO without removing the data.

Parameters
TypeDirectionArgument NameDescription
const ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Returns

  • The data at the top of the FIFO.

Note

  • The FIFO's count remains unchanged.


sl_hal_adc_get_fifo_count#

uint32_t sl_hal_adc_get_fifo_count (const ADC_TypeDef * adc)

Get the ADC's current FIFO count.

Parameters
TypeDirectionArgument NameDescription
const ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Returns

  • The ADC's current FIFO count.


sl_hal_adc_get_internal_reference_voltage#

uint32_t sl_hal_adc_get_internal_reference_voltage (const ADC_TypeDef * adc)

Get the ADC's internal reference voltage in millivolts.

Parameters
TypeDirectionArgument NameDescription
const ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Returns

  • The ADC's internal reference voltage in millivolts.


sl_hal_adc_get_timer_frequency#

uint32_t sl_hal_adc_get_timer_frequency (const ADC_TypeDef * adc, uint32_t branch_clock_freq)

Calculate and return the clock frequency of the ADC's local timer.

Parameters
TypeDirectionArgument NameDescription
const ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

uint32_t[in]branch_clock_freq

Incoming peripheral frequency. Should be retrieved using the Clock Manager service.

Returned value is based on the clock branch selected for the ADC peripheral and the current hsclkrate prescaler.

Returns

  • The clock frequency of the ADC's local timer.

Note

The branch_clock_freq can be obtained for adc0 using the Device Manager and Clock Manager services as such:

#include "sl_clock_manager.h"
#include "sl_device_peripheral.h"

sl_clock_branch_t clock_branch;
clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_ADC0);

uint32_t branch_clock_freq;
sl_clock_manager_get_clock_branch_frequency(clock_branch, &branch_clock_freq);

sl_hal_adc_set_timer_period#

void sl_hal_adc_set_timer_period (ADC_TypeDef * adc, uint16_t timer_period)

Set the timer period to periodically trigger a timer event.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

uint16_t[in]timer_period

The number of clock cycles between ADC timer events.

Timer events can be used to trigger an ADC scan.

Note

  • The ADC's local timer must be disabled before calling this function.


sl_hal_adc_set_clock_prescalers#

void sl_hal_adc_set_clock_prescalers (ADC_TypeDef * adc, uint32_t branch_clock_freq, uint8_t hsclkrate, uint8_t adcprescale)

Set both ADC prescalers.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

uint32_t[in]branch_clock_freq

Incoming peripheral frequency. Should be retrieved using the Clock Manager service.

uint8_t[in]hsclkrate

This prescaler divides the branch clock frequency and the resulting clock is ADC_SRC_CLK. This clocks the ADC peripheral's local timer. The value can be set to an integer value from 0 to 5. The branch clock frequency is divided by (hsclkrate + 1). ADC_SRC_CLK must be less than 40MHz.

uint8_t[in]adcprescale

This prescaler divides the ADC_SRC_CLK and the resulting clock is ADC_CORE_CLK. This clocks the core functionality of the ADC peripheral. The value can be set to 0 (no divider) or 1 (divide by 2). The operating frequency of ADC_CORE_CLK is between 17MHz and 22MHz.

Re-calculates and updates the timebase.

Note

  • The ADC must be disabled before making changes to the clock prescalers. The branch_clock_freq can be obtained for adc0 using the Device Manager and Clock Manager services as such:

    {
      #include "sl_clock_manager.h"
      #include "sl_device_peripheral.h"
    
      sl_clock_branch_t clock_branch;
      clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_ADC0);
    
      uint32_t branch_clock_freq;
      sl_clock_manager_get_clock_branch_frequency(clock_branch, &branch_clock_freq);
    }
    

sl_hal_adc_enable#

void sl_hal_adc_enable (ADC_TypeDef * adc)

Enable the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_disable#

void sl_hal_adc_disable (ADC_TypeDef * adc)

Disable the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_start#

void sl_hal_adc_start (ADC_TypeDef * adc)

Start the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Note

  • Enables the scan sequence and will start a scan if using the immediate trigger mode.


sl_hal_adc_stop#

void sl_hal_adc_stop (ADC_TypeDef * adc)

Stop the ADC.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_enable_timer#

void sl_hal_adc_enable_timer (ADC_TypeDef * adc)

Enable the ADC's local timer.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_disable_timer#

void sl_hal_adc_disable_timer (ADC_TypeDef * adc)

Disable the ADC's local timer and resets the counter.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_flush_fifo#

void sl_hal_adc_flush_fifo (ADC_TypeDef * adc)

Flush the scan FIFO.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Note

  • The ADC must be enabled. The operation is completed when SCANFIFOFLUSHING STATUS bit is low. The Scan queue should be disabled. Any incoming scan queue data will be discarded during the flush.


sl_hal_adc_wait_sync#

void sl_hal_adc_wait_sync (ADC_TypeDef * adc)

Wait for ongoing sync of register(s) to the low-frequency domain to complete.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_wait_ready#

void sl_hal_adc_wait_ready (ADC_TypeDef * adc)

Wait for disabling to finish.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.


sl_hal_adc_get_status#

uint32_t sl_hal_adc_get_status (ADC_TypeDef * adc)

Return the content of the status register.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

A pointer to the ADC peripheral register block.

Returns

  • Status register.


sl_hal_adc_enable_interrupts#

void sl_hal_adc_enable_interrupts (ADC_TypeDef * adc, uint32_t flags)

Enable one or more ADC interrupts.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

uint32_t[in]flags

Pending ADC interrupt source to enable. Use a bitwise logic OR combination of valid interrupt flags for ADC module (ADC_IEN_nnn).


sl_hal_adc_disable_interrupts#

void sl_hal_adc_disable_interrupts (ADC_TypeDef * adc, uint32_t flags)

Disable one or more ADC interrupts.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

uint32_t[in]flags

Pending ADC interrupt source to disable. Use a bitwise logic OR combination of valid interrupt flags for ADC module (ADC_IEN_nnn).


sl_hal_adc_clear_interrupts#

void sl_hal_adc_clear_interrupts (ADC_TypeDef * adc, uint32_t flags)

Clear one or more pending ADC interrupts.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

uint32_t[in]flags

Pending ADC interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for ADC module (ADC_IEN_nnn).


sl_hal_adc_set_interrupts#

void sl_hal_adc_set_interrupts (ADC_TypeDef * adc, uint32_t flags)

Set one or more pending ADC interrupts from software.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

uint32_t[in]flags

Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for ADC module (ADC_IEN_nnn).


sl_hal_adc_get_pending_interrupts#

uint32_t sl_hal_adc_get_pending_interrupts (ADC_TypeDef * adc)

Get pending ADC interrupt flags.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

Returns

  • Pending ADC interrupt sources.


sl_hal_adc_get_enabled_pending_interrupts#

uint32_t sl_hal_adc_get_enabled_pending_interrupts (ADC_TypeDef * adc)

Get enabled and pending ADC interrupt flags.

Parameters
TypeDirectionArgument NameDescription
ADC_TypeDef *[in]adc

Pointer to the ADC peripheral register block.

Useful for handling more interrupt sources in the same interrupt handler.

Returns

  • Pending and enabled ADC interrupt sources.