PDM initialization structure.
Public Attributes#
bool
Enable stereo mode for channel pair CH0 and CH1.
PDM filter order.
Number of PDM channels.
PDM filter data output format.
FIFO Data valid level water-mark.
Ch 0 clock polarity.
Ch 1 clock polarity.
uint32_t
PDM gain.
uint32_t
PDM down sampling rate.
uint32_t
PDM clock prescaler, resulting PDM clock is input clock / (prescaler + 1).
Public Attribute Documentation#
ch0ch1_stereo_enable#
bool sl_hal_pdm_init_t::ch0ch1_stereo_enable
Enable stereo mode for channel pair CH0 and CH1.
number_channels#
sl_hal_pdm_number_of_channels_t sl_hal_pdm_init_t::number_channels
Number of PDM channels.
fifo_valid_watermark#
sl_hal_pdm_fifo_valid_watermark_t sl_hal_pdm_init_t::fifo_valid_watermark
FIFO Data valid level water-mark.
ch0_clock_polarity#
sl_hal_pdm_ch_clock_polarity_t sl_hal_pdm_init_t::ch0_clock_polarity
Ch 0 clock polarity.
ch1_clock_polarity#
sl_hal_pdm_ch_clock_polarity_t sl_hal_pdm_init_t::ch1_clock_polarity
Ch 1 clock polarity.
clk_prescaler#
uint32_t sl_hal_pdm_init_t::clk_prescaler
PDM clock prescaler, resulting PDM clock is input clock / (prescaler + 1).