VDAC initialization structure, common for both channels.
Public Attributes#
Number of prescaled CLK_DAC + 1 for the VDAC to warmup.
Halt during debug.
Always allow clk_dac.
DMA Wakeup.
Bias keep warm enable.
Channel refresh period.
Internal timer overflow period.
Prescaler for VDAC clock. Clock is source clock divided by prescaler+1.
Reference voltage to use.
Enable/disable reset of prescaler on CH 0 start.
Sine reset mode.
Enable/disable sine mode.
Select if single ended or differential output mode.
PRS controlled sinemode enable.
PRS controlled channel output enable.
Public Attribute Documentation#
warmup_time#
uint32_t sl_hal_vdac_init_t::warmup_time
Number of prescaled CLK_DAC + 1 for the VDAC to warmup.
timer_overflow#
sl_hal_vdac_timer_overflow_period_t sl_hal_vdac_init_t::timer_overflow
Internal timer overflow period.
prescaler#
uint32_t sl_hal_vdac_init_t::prescaler
Prescaler for VDAC clock. Clock is source clock divided by prescaler+1.
ch0_reset_prescaler#
bool sl_hal_vdac_init_t::ch0_reset_prescaler
Enable/disable reset of prescaler on CH 0 start.