Silicon Labs Secure Engine Manager API definitions.

The tamper configuration is one-time-programmable, and is done using the initialise OTP command to the SE (see sl_se_init_otp). This means that tamper settings must be written together with secure boot settings, and are immutable after they are written. After tamper has been initialized, it is possible to temporarily disable one or several tamper signals using an authenticated command, similar to secure debug unlock. This is only possible if the debug public key has been installed on the device. It is only possible to disable the customer enabled response. The default response to a signal cannot be disabled.

Tamper is configured by providing the following:

Tamper configuration table

Setting

Description

Tamper response levels

A response level for each tamper signal.

It is not possible to degrade the default response level of a tamper signal, so if a response is set to a lower level than the default response level listed in the table in the Signals section, this won't have any effect.

Filter settings

The tamper filter counter has two settings:

  • Reset period

  • Trigger threshold

These options can be set to the values given in the tables in the Response Filter section. Please see the examples section for a suggested use of the tamper filter signal.

Flags

The tamper flags is used to configure two options:

  • Digital Glitch Detector Always On – This option will keep the digital glitch detector running even while the SE is not performing any operations. This leads to increased energy consumption.

  • Keep Tamper Alive During Sleep (not available on EFR32xG21B devices) – If set, the tamper module keeps running at sleep mode (down to EM3).

Reset threshold

The number of consecutive tamper resets before the the part enters debug mode.

If the threshold is set to 0, the part will never enter the debug mode due to tamper reset.

Example Usage#

The glitch detectors can see spurious activations, and should typically not be used to directly drive a serious tamper response. Instead they should feed their signals into a tamper interrupt (to handle the response logic on the M33), or into the tamper filter counter, which can be used to activate a high level response if a number of incidents occur in a short time window. The time period and counter threshold must be tuned to the use case. In the following example the device will erase OTP and become inoperable if 4 glitch signals is seen in a 1 minute time period.

Since you can only configure tamper once for each device, please make sure that this is the configuration you actually want before you execute this example on actual device.

sl_se_otp_init_t otp_settings_init = SL_SE_OTP_INIT_DEFAULT;

// Configure tamper levels
otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_FILTER] = SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP;
otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHFALLING] = SL_SE_TAMPER_LEVEL_FILTER;
otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_VGLITCHRISING] = SL_SE_TAMPER_LEVEL_FILTER;
otp_settings_init.tamper_levels[SL_SE_TAMPER_SIGNAL_DGLITCH] = SL_SE_TAMPER_LEVEL_FILTER;


// Configure tamper filter options
otp_settings_init.tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_1MIN;
otp_settings_init.tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4;


// Commit OTP settings. This command is only available once!
sl_se_init_otp(&otp_settings_init);

RTOS Mode and Multi-Thread Safety#

Note

  • The SE Manager API is multi-thread safe, but does not support preemption. This means the API cannot be called from ISR or critical/atomic sections when running in an RTOS thread. When using the SE Manager API in a bare-metal application, it is the application developer's responsibility to not call the SE Manager APIs when another operation is in progress.

The SE Manager supports multi-thread safe APIs for MicriumOS and FreeRTOS interfacing with CMSIS RTOS2 APIs.

In the cases where Micrium OS or FreeRTOS are included in the project (RTOS-mode), the SE Manager will be configured with threading and yield support. Configure sl_se_command_context_t with sl_se_set_yield to yield the CPU core when the SE Manager is waiting for the Secure Engine to complete a mailbox command.

For threading support the SE Manager applies an SE lock mechanism to protect the Secure Engine Mailbox interface from being accessed by more than one thread, ensuring multi-thread safety. For yielding the CPU core while waiting for the SE, the SE Manager APIs that invoke SE mailbox commands will wait on a semaphore which is signaled in the ISR that handles the SE mailbox completion interrupt. Hence other threads may run on the CPU core while the SE is processing the mailbox command.

License#

Copyright 2020 Silicon Laboratories Inc. www.silabs.com

SPDX-License-Identifier: Zlib

The licensor of this software is Silicon Laboratories Inc.

This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software.

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required.

  2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.

  3. This notice may not be removed or altered from any source distribution.

Macros#

#define
SL_SE_COMMAND_CONTEXT_INIT { SLI_SE_MAILBOX_COMMAND_DEFAULT(0), false, false }

Context initialization values.

#define
SL_SE_OTP_INIT_DEFAULT undefined

Default configuration for OTP initialisation structure.

#define
SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY (1UL << 10)

Flags that can be used with asymmetric keys Asymmetric key can only be used for signing (not key exchange)

#define
SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN (1UL << 12)

Described key belongs to a custom ECC domain.

#define
SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY (1UL << 13)

Storage buffer contains public part of an asymmetric key.

#define
SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY (1UL << 14)

Storage buffer contains private part of an asymmetric key.

#define
SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS (1UL << 15)

Allow usage of this key by other bus masters or TrustZone levels than the one which created/imported the key.

#define
SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY (SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY)

Old definition. Retained for backwards compatibility.

#define
SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DPA (1 << 9)

Flags that can be used with symmetric keys Usage of key requires DPA countermeasures.

#define
SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DFA (1 << 8)

Usage of key requires DFA countermeasures.

#define
SL_SE_KEY_FLAG_NON_EXPORTABLE (1UL << 24)

Do not allow exporting the key to plaintext.

#define
SL_SE_KEY_FLAG_IS_DEVICE_GENERATED (1UL << 25)

Indicate that the key has been generated by this device.

#define
SL_SE_KEY_FLAG_IS_RESTRICTED (1UL << 25 | 1UL << 24)

Indicate that the key can only be used to sign SE generated content.

#define
SL_SE_KEY_TYPE_ALGORITHM_MASK 0xf0000000

Mask for algorithm field in key type.

#define
SL_SE_KEY_TYPE_ALGORITHM_OFFSET 28

Offset of algorithm field in key type.

#define
SL_SE_KEY_TYPE_ATTRIBUTES_MASK 0x00007fff

Mask for attributes field in key type.

#define
SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET 0

Offset of attributes field in key type.

#define
SL_SE_KEY_TYPE_SYMMETRIC 0x00000000

Symmetric key type.

#define
SL_SE_KEY_TYPE_AES_128 0x00000010

Symmetric key type for AES-128 (16 byte key)

#define
SL_SE_KEY_TYPE_AES_192 0x00000018

Symmetric key type for AES-192 (24 byte key)

#define
SL_SE_KEY_TYPE_AES_256 0x00000020

Symmetric key type for AES-256 (32 byte key)

#define
SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM (0x8U << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

ECC Weierstrass Prime key type.

#define
SL_SE_KEY_TYPE_ECC_MONTGOMERY (0xbU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

ECC Montgomery key type.

#define
SL_SE_KEY_TYPE_ECC_EDDSA (0xcU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

EDDSA key type.

#define
SL_SE_KEY_TYPE_ECC_P192 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x18))

ECC NIST P-192.

#define
SL_SE_KEY_TYPE_ECC_P224 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x1C))

ECC NIST P-224.

#define
SL_SE_KEY_TYPE_ECC_P256 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x20))

ECC NIST P-256.

#define
SL_SE_KEY_TYPE_ECC_ED25519 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x20))

ECC Ed25519 key for EdDSA.

#define
SL_SE_KEY_TYPE_ECC_X25519 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x20))

ECC X25519 key for ECDH.

#define
SL_SE_KEY_TYPE_CHACHA20 0x00000020

Symmetric key type for ChaCha20.

#define
SL_SE_KEY_TYPE_ECC_P384 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x30))

ECC NIST P-384.

#define
SL_SE_KEY_TYPE_ECC_P521 (SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x42))

ECC NIST P-521.

#define
SL_SE_KEY_TYPE_ECC_X448 (SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x38))

ECC X448 key for ECDH.

#define
SL_SE_KEY_TYPE_ECC_ED448 (SL_SE_KEY_TYPE_ECC_EDDSA | (0x38))

ECC Ed448 key for EdDSA.

#define
SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT 0x00

Key storage methods.

#define
SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED 0x01

Key is stored encrypted in application memory.

#define
SL_SE_KEY_STORAGE_INTERNAL_VOLATILE 0x02

Key is stored inside the SE, and will persist until system reset or explicitly deleted.

#define
SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE 0x03

Key is one of the pre-defined keys (pre-loaded or write-once) available in the SE.

#define
SL_SE_KEY_STORAGE_INTERNAL_KSU 0x04

Key is stored in the KSURAM, an internal Key Slot RAM.

#define
SL_SE_KEY_SLOT_VOLATILE_0 0x00

List of available internal SE key slots.

#define
SL_SE_KEY_SLOT_VOLATILE_1 0x01

Internal volatile slot 1.

#define
SL_SE_KEY_SLOT_VOLATILE_2 0x02

Internal volatile slot 2.

#define
SL_SE_KEY_SLOT_VOLATILE_3 0x03

Internal volatile slot 3.

#define
SL_SE_KEY_SLOT_INTERNAL_MIN 0xF7

Minimum key slot value for internal keys.

#define
SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY 0xF7

Internal TrustZone root key.

#define
SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY 0xF8

Internal immutable application secure debug key.

#define
SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY 0xFA

Internal immutable application AES-128 key (bootloader key)

#define
SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY 0xFC

Internal immutable application secure boot key.

#define
SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY 0xFE

Internal immutable application attestation key.

#define
SL_SE_KEY_SLOT_SE_ATTESTATION_KEY 0xFF

Internal immutable SE attestation key.

#define
SL_SE_KSU_ID_HOST 0x00

KSU IDs.

#define
SLI_SE_WRAPPED_KEY_OVERHEAD (12 + 16)

Size overhead for wrapped keys.

#define
SL_SE_PRF_AES_CMAC_128 SL_SE_HASH_NONE

Defines mapping the PBKDF2 PRFs to corresponding sl_se_hash_type_t values.

#define
SL_SE_PRF_HMAC_SHA1 SL_SE_HASH_SHA1

HMAC-SHA-1.

#define
SL_SE_PRF_HMAC_SHA224 SL_SE_HASH_SHA224

HMAC-SHA-224.

#define
SL_SE_PRF_HMAC_SHA256 SL_SE_HASH_SHA256

HMAC-SHA-256.

#define
SL_SE_PRF_HMAC_SHA384 SL_SE_HASH_SHA384

HMAC-SHA-384.

#define
SL_SE_PRF_HMAC_SHA512 SL_SE_HASH_SHA512

HMAC-SHA-512.

#define
SL_SE_CHALLENGE_SIZE 16

SE Challenge size.

#define
SL_SE_CERT_KEY_SIZE 64

Certificate key size.

#define
SL_SE_CERT_SIGN_SIZE 64

Certificate signature size.

#define
SL_SE_CERT_BATCH 0x01

Batch ID certificate.

#define
SL_SE_CERT_DEVICE_SE 0x02

SE ID certificate.

#define
SL_SE_CERT_DEVICE_HOST 0x03

Host ID certificate.

#define
SL_SE_TAMPER_LEVEL_IGNORE 0

No action taken.

#define
SL_SE_TAMPER_LEVEL_INTERRUPT 1

Generate interrupt.

#define
SL_SE_TAMPER_LEVEL_FILTER 2

Increment filter counter.

#define
SL_SE_TAMPER_LEVEL_RESET 4

System reset.

#define
SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP 7

Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!

#define
SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1

Filter counter exceeds threshold.

#define
SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2

SE watchdog timeout.

#define
SL_SE_TAMPER_SIGNAL_CRYPTO_ERROR 0x3

Crypto error detected.

#define
SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4

SE RAM 2-bit ECC error.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_2 0x5

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_SE_MAJOR_FAULT 0x6

SE major fault detected.

#define
SL_SE_TAMPER_SIGNAL_L2ICACHE 0x7

L2 instruction cache error.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_3 0x8

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9

Secure boot of user code failed.

#define
SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA

Unauthorised command received over the Mailbox interface.

#define
SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB

Unauthorised command received over the DCI interface.

#define
SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0xC

SE software triggers an assert.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE

Integrity error of internal storage is detected.

#define
SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF

TRNG monitor detected lack of entropy.

#define
SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10

Debug lock internal logic check failed.

#define
SL_SE_TAMPER_ATAMPDET 0x11

Any tamper detection.

#define
SL_SE_TAMPER_SIGNAL_OTP_ALARM 0x12

OTP alarm triggered.

#define
SL_SE_TAMPER_SE_ICACHE_ERROR 0x13

SE ICache RAM error.

#define
SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14

SE RAM 1-bit ECC error.

#define
SL_SE_TAMPER_SIGNAL_BOD 0x15

Brown-out-detector threshold alert.

#define
SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16

On-device temperature sensor.

#define
SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL 0x17

DPLL lock failure.

#define
SL_SE_TAMPER_SIGNAL_SOC_PLL_FAIL 0x18

SoC PLL failure.

#define
SL_SE_TAMPER_SIGNAL_ETAMPDET 0x19

External tamper detect.

#define
SL_SE_TAMPER_SIGNAL_KSU_ECC_1 0x1A

KSU ECC 1-bit error.

#define
SL_SE_TAMPER_SIGNAL_KSU_ECC_2 0x1B

KSU ECC 2-bit error.

#define
SL_SE_TAMPER_SIGNAL_QSPI_RESEED_ERR 0x1C

QSPI reseed error.

#define
SL_SE_TAMPER_SIGNAL_PRS0 0x1D

PRS channel 0 asserted.

#define
SL_SE_TAMPER_SIGNAL_PRS1 0x1E

PRS channel 1 asserted.

#define
SL_SE_TAMPER_SIGNAL_PRS2 0x1F

PRS channel 2 asserted.

#define
SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20

Number of tamper signals.

#define
SL_SE_TAMPER_FILTER_PERIOD_32MS 0x0

Timeout ~32ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_64MS 0x1

Timeout ~64ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_128MS 0x2

Timeout ~128ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_256MS 0x3

Timeout ~256ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_512MS 0x4

Timeout ~512ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_1S 0x5

Timeout ~1s.

#define
SL_SE_TAMPER_FILTER_PERIOD_2S 0x6

Timeout ~2s.

#define
SL_SE_TAMPER_FILTER_PERIOD_4S 0x7

Timeout ~4.1s.

#define
SL_SE_TAMPER_FILTER_PERIOD_8S 0x8

Timeout ~8.2s.

#define
SL_SE_TAMPER_FILTER_PERIOD_16S 0x9

Timeout ~16.4s.

#define
SL_SE_TAMPER_FILTER_PERIOD_33S 0xA

Timeout ~32.8s.

#define
SL_SE_TAMPER_FILTER_PERIOD_1MIN 0xB

Timeout ~1.1min.

#define
SL_SE_TAMPER_FILTER_PERIOD_2MIN 0xC

Timeout ~2.2min.

#define
SL_SE_TAMPER_FILTER_PERIOD_4MIN 0xD

Timeout ~4.4min.

#define
SL_SE_TAMPER_FILTER_PERIOD_9MIN 0xE

Timeout ~8.7min.

#define
SL_SE_TAMPER_FILTER_PERIOD_18MIN 0xF

Timeout ~17.5min.

#define
SL_SE_TAMPER_FILTER_PERIOD_35MIN 0x10

Timeout ~35min.

#define
SL_SE_TAMPER_FILTER_PERIOD_1H 0x11

Timeout ~1.2h.

#define
SL_SE_TAMPER_FILTER_PERIOD_2H 0x12

Timeout ~2.3h.

#define
SL_SE_TAMPER_FILTER_PERIOD_5H 0x13

Timeout ~4.7h.

#define
SL_SE_TAMPER_FILTER_PERIOD_9H 0x14

Timeout ~9.3h.

#define
SL_SE_TAMPER_FILTER_PERIOD_19H 0x15

Timeout ~18.6h.

#define
SL_SE_TAMPER_FILTER_PERIOD_2DAYS 0x16

Timeout ~1.6days.

#define
SL_SE_TAMPER_FILTER_PERIOD_3DAYS 0x17

Timeout ~3.1days.

#define
SL_SE_TAMPER_FILTER_PERIOD_6DAYS 0x18

Timeout ~6.2days.

#define
SL_SE_TAMPER_FILTER_PERIOD_12DAYS 0x19

Timeout ~12.4days.

#define
SL_SE_TAMPER_FILTER_PERIOD_25DAYS 0x1A

Timeout ~24.9days.

#define
SL_SE_TAMPER_FILTER_PERIOD_50DAYS 0x1B

Timeout ~49.7days.

#define
SL_SE_TAMPER_FILTER_PERIOD_100DAYS 0x1C

Timeout ~99.4days.

#define
SL_SE_TAMPER_FILTER_PERIOD_199DAYS 0x1D

Timeout ~198.8days.

#define
SL_SE_TAMPER_FILTER_PERIOD_398DAYS 0x1E

Timeout ~397.7days.

#define
SL_SE_TAMPER_FILTER_PERIOD_795DAYS 0x1F

Timeout ~795.4days.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_2 0x7

Counter threshold 2.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_4 0x6

Counter threshold 4.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_8 0x5

Counter threshold 8.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_16 0x4

Counter threshold 16.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_32 0x3

Counter threshold 32.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_64 0x2

Counter threshold 64.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_128 0x1

Counter threshold 128.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_256 0x0

Counter threshold 256.

#define
SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1)

Tamper flags.

#define
SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2)

Tamper is kept alive during sleep (down to EM3)

#define
SL_SE_AES_BLOCK_SIZE (16u)

Block size for the AES.

#define
SL_SE_HASH_STREAMING_INIT_DEFAULT { NULL, 0, 0, NULL }

Default streaming hash context.

#define
SL_SE_SHA1_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } }

SHA1 streaming hash context.

#define
SL_SE_SHA224_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } }

SHA224 streaming hash context.

#define
SL_SE_SHA256_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } }

SHA256 streaming hash context.

#define
SL_SE_SHA384_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } }

SHA384 streaming hash context.

#define
SL_SE_SHA512_STREAMING_INIT_DEFAULT { { 0 }, { 0 }, { 0 } }

SHA512 streaming hash context.

#define
SL_SE_MAX_CODE_REGIONS 8

The maximum number of code regions available on the device.

Macro Definition Documentation#

SL_SE_COMMAND_CONTEXT_INIT#

#define SL_SE_COMMAND_CONTEXT_INIT
Value:
{ SLI_SE_MAILBOX_COMMAND_DEFAULT(0), false, false }

Context initialization values.

Some of the context values are not fully initialized. The user will need to call the corresponding initialization function in order to fully initialize the context objects for further use in the SE Manager API. The purpose of these initialization values is to set the context objects to a known safe state initially when the context object is declared.


SL_SE_OTP_INIT_DEFAULT#

#define SL_SE_OTP_INIT_DEFAULT
Value:
{ \
.enable_secure_boot = false, \
.verify_secure_boot_certificate = false, \
.enable_anti_rollback = false, \
.tamper_levels = { 0 }, \
.tamper_filter_period = SL_SE_TAMPER_FILTER_PERIOD_2MIN, \
.tamper_filter_threshold = SL_SE_TAMPER_FILTER_THRESHOLD_4, \
.tamper_flags = 0, \
.tamper_reset_threshold = 5 \
}

Default configuration for OTP initialisation structure.


SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY#

#define SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY
Value:
(1UL << 10)

Flags that can be used with asymmetric keys Asymmetric key can only be used for signing (not key exchange)


SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN#

#define SL_SE_KEY_FLAG_ASYMMETRIC_USES_CUSTOM_DOMAIN
Value:
(1UL << 12)

Described key belongs to a custom ECC domain.


SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY#

#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PUBLIC_KEY
Value:
(1UL << 13)

Storage buffer contains public part of an asymmetric key.


SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY#

#define SL_SE_KEY_FLAG_ASYMMETRIC_BUFFER_HAS_PRIVATE_KEY
Value:
(1UL << 14)

Storage buffer contains private part of an asymmetric key.


SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS#

#define SL_SE_KEY_FLAG_ALLOW_ANY_ACCESS
Value:
(1UL << 15)

Allow usage of this key by other bus masters or TrustZone levels than the one which created/imported the key.


SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY#

#define SL_SE_KEY_FLAG_ASYMMMETRIC_SIGNING_ONLY
Value:
  (SL_SE_KEY_FLAG_ASYMMETRIC_SIGNING_ONLY)

Old definition. Retained for backwards compatibility.


SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DPA#

#define SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DPA
Value:
(1 << 9)

Flags that can be used with symmetric keys Usage of key requires DPA countermeasures.


SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DFA#

#define SL_SE_KEY_FLAG_SYMMETRIC_KEY_USAGE_REQUIRE_DFA
Value:
(1 << 8)

Usage of key requires DFA countermeasures.


SL_SE_KEY_FLAG_NON_EXPORTABLE#

#define SL_SE_KEY_FLAG_NON_EXPORTABLE
Value:
(1UL << 24)

Do not allow exporting the key to plaintext.


SL_SE_KEY_FLAG_IS_DEVICE_GENERATED#

#define SL_SE_KEY_FLAG_IS_DEVICE_GENERATED
Value:
(1UL << 25)

Indicate that the key has been generated by this device.

This flag is only valid when using the SE to generate a key and makes it non-exportable.


SL_SE_KEY_FLAG_IS_RESTRICTED#

#define SL_SE_KEY_FLAG_IS_RESTRICTED
Value:
(1UL << 25 | 1UL << 24)

Indicate that the key can only be used to sign SE generated content.

This flag is only valid when using the SE to generate a key and makes it non-exportable.


SL_SE_KEY_TYPE_ALGORITHM_MASK#

#define SL_SE_KEY_TYPE_ALGORITHM_MASK
Value:
0xf0000000

Mask for algorithm field in key type.


SL_SE_KEY_TYPE_ALGORITHM_OFFSET#

#define SL_SE_KEY_TYPE_ALGORITHM_OFFSET
Value:
28

Offset of algorithm field in key type.


SL_SE_KEY_TYPE_ATTRIBUTES_MASK#

#define SL_SE_KEY_TYPE_ATTRIBUTES_MASK
Value:
0x00007fff

Mask for attributes field in key type.


SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET#

#define SL_SE_KEY_TYPE_ATTRIBUTES_OFFSET
Value:
0

Offset of attributes field in key type.


SL_SE_KEY_TYPE_SYMMETRIC#

#define SL_SE_KEY_TYPE_SYMMETRIC
Value:
0x00000000

Symmetric key type.


SL_SE_KEY_TYPE_AES_128#

#define SL_SE_KEY_TYPE_AES_128
Value:
0x00000010

Symmetric key type for AES-128 (16 byte key)


SL_SE_KEY_TYPE_AES_192#

#define SL_SE_KEY_TYPE_AES_192
Value:
0x00000018

Symmetric key type for AES-192 (24 byte key)


SL_SE_KEY_TYPE_AES_256#

#define SL_SE_KEY_TYPE_AES_256
Value:
0x00000020

Symmetric key type for AES-256 (32 byte key)


SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM#

#define SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM
Value:
(0x8U << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

ECC Weierstrass Prime key type.


SL_SE_KEY_TYPE_ECC_MONTGOMERY#

#define SL_SE_KEY_TYPE_ECC_MONTGOMERY
Value:
(0xbU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

ECC Montgomery key type.


SL_SE_KEY_TYPE_ECC_EDDSA#

#define SL_SE_KEY_TYPE_ECC_EDDSA
Value:
(0xcU << SL_SE_KEY_TYPE_ALGORITHM_OFFSET)

EDDSA key type.


SL_SE_KEY_TYPE_ECC_P192#

#define SL_SE_KEY_TYPE_ECC_P192
Value:
(SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x18))

ECC NIST P-192.


SL_SE_KEY_TYPE_ECC_P224#

#define SL_SE_KEY_TYPE_ECC_P224
Value:
(SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x1C))

ECC NIST P-224.


SL_SE_KEY_TYPE_ECC_P256#

#define SL_SE_KEY_TYPE_ECC_P256
Value:
(SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x20))

ECC NIST P-256.


SL_SE_KEY_TYPE_ECC_ED25519#

#define SL_SE_KEY_TYPE_ECC_ED25519
Value:
(SL_SE_KEY_TYPE_ECC_EDDSA | (0x20))

ECC Ed25519 key for EdDSA.


SL_SE_KEY_TYPE_ECC_X25519#

#define SL_SE_KEY_TYPE_ECC_X25519
Value:
(SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x20))

ECC X25519 key for ECDH.


SL_SE_KEY_TYPE_CHACHA20#

#define SL_SE_KEY_TYPE_CHACHA20
Value:
0x00000020

Symmetric key type for ChaCha20.


SL_SE_KEY_TYPE_ECC_P384#

#define SL_SE_KEY_TYPE_ECC_P384
Value:
(SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x30))

ECC NIST P-384.


SL_SE_KEY_TYPE_ECC_P521#

#define SL_SE_KEY_TYPE_ECC_P521
Value:
(SL_SE_KEY_TYPE_ECC_WEIERSTRASS_PRIME_CUSTOM | (0x42))

ECC NIST P-521.


SL_SE_KEY_TYPE_ECC_X448#

#define SL_SE_KEY_TYPE_ECC_X448
Value:
(SL_SE_KEY_TYPE_ECC_MONTGOMERY | (0x38))

ECC X448 key for ECDH.


SL_SE_KEY_TYPE_ECC_ED448#

#define SL_SE_KEY_TYPE_ECC_ED448
Value:
(SL_SE_KEY_TYPE_ECC_EDDSA | (0x38))

ECC Ed448 key for EdDSA.


SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT#

#define SL_SE_KEY_STORAGE_EXTERNAL_PLAINTEXT
Value:
0x00

Key storage methods.

Key is stored in a plaintext buffer in application memory. Application can save its in-memory buffer to non-volatile memory as needed to provide key persistence.


SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED#

#define SL_SE_KEY_STORAGE_EXTERNAL_WRAPPED
Value:
0x01

Key is stored encrypted in application memory.

This ensures the key in wrapped form is only usable on a specific device. If the key additionally needs to be prevented from ever being output as plaintext, also set the corresponding permission bit. Application can save its in-memory buffer to non-volatile memory as needed to provide key persistence. Keys stored in this way should use the flag SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access the key value outside the SE.


SL_SE_KEY_STORAGE_INTERNAL_VOLATILE#

#define SL_SE_KEY_STORAGE_INTERNAL_VOLATILE
Value:
0x02

Key is stored inside the SE, and will persist until system reset or explicitly deleted.

Keys stored in this way should use the flag SL_SE_KEY_FLAG_NON_EXPORTABLE unless there is a specific need to access the key value outside the SE.


SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE#

#define SL_SE_KEY_STORAGE_INTERNAL_IMMUTABLE
Value:
0x03

Key is one of the pre-defined keys (pre-loaded or write-once) available in the SE.

See documentation for a list of available keys.


SL_SE_KEY_STORAGE_INTERNAL_KSU#

#define SL_SE_KEY_STORAGE_INTERNAL_KSU
Value:
0x04

Key is stored in the KSURAM, an internal Key Slot RAM.


SL_SE_KEY_SLOT_VOLATILE_0#

#define SL_SE_KEY_SLOT_VOLATILE_0
Value:
0x00

List of available internal SE key slots.

Internal volatile slot 0


SL_SE_KEY_SLOT_VOLATILE_1#

#define SL_SE_KEY_SLOT_VOLATILE_1
Value:
0x01

Internal volatile slot 1.


SL_SE_KEY_SLOT_VOLATILE_2#

#define SL_SE_KEY_SLOT_VOLATILE_2
Value:
0x02

Internal volatile slot 2.


SL_SE_KEY_SLOT_VOLATILE_3#

#define SL_SE_KEY_SLOT_VOLATILE_3
Value:
0x03

Internal volatile slot 3.


SL_SE_KEY_SLOT_INTERNAL_MIN#

#define SL_SE_KEY_SLOT_INTERNAL_MIN
Value:
0xF7

Minimum key slot value for internal keys.


SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY#

#define SL_SE_KEY_SLOT_TRUSTZONE_ROOT_KEY
Value:
0xF7

Internal TrustZone root key.


SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY#

#define SL_SE_KEY_SLOT_APPLICATION_SECURE_DEBUG_KEY
Value:
0xF8

Internal immutable application secure debug key.


SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY#

#define SL_SE_KEY_SLOT_APPLICATION_AES_128_KEY
Value:
0xFA

Internal immutable application AES-128 key (bootloader key)


SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY#

#define SL_SE_KEY_SLOT_APPLICATION_SECURE_BOOT_KEY
Value:
0xFC

Internal immutable application secure boot key.


SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY#

#define SL_SE_KEY_SLOT_APPLICATION_ATTESTATION_KEY
Value:
0xFE

Internal immutable application attestation key.


SL_SE_KEY_SLOT_SE_ATTESTATION_KEY#

#define SL_SE_KEY_SLOT_SE_ATTESTATION_KEY
Value:
0xFF

Internal immutable SE attestation key.


SL_SE_KSU_ID_HOST#

#define SL_SE_KSU_ID_HOST
Value:
0x00

KSU IDs.


SLI_SE_WRAPPED_KEY_OVERHEAD#

#define SLI_SE_WRAPPED_KEY_OVERHEAD
Value:
(12 + 16)

Size overhead for wrapped keys.


SL_SE_PRF_AES_CMAC_128#

#define SL_SE_PRF_AES_CMAC_128
Value:
SL_SE_HASH_NONE

Defines mapping the PBKDF2 PRFs to corresponding sl_se_hash_type_t values.

CMAC-AES-128


SL_SE_PRF_HMAC_SHA1#

#define SL_SE_PRF_HMAC_SHA1
Value:
SL_SE_HASH_SHA1

HMAC-SHA-1.


SL_SE_PRF_HMAC_SHA224#

#define SL_SE_PRF_HMAC_SHA224
Value:
SL_SE_HASH_SHA224

HMAC-SHA-224.


SL_SE_PRF_HMAC_SHA256#

#define SL_SE_PRF_HMAC_SHA256
Value:
SL_SE_HASH_SHA256

HMAC-SHA-256.


SL_SE_PRF_HMAC_SHA384#

#define SL_SE_PRF_HMAC_SHA384
Value:
SL_SE_HASH_SHA384

HMAC-SHA-384.


SL_SE_PRF_HMAC_SHA512#

#define SL_SE_PRF_HMAC_SHA512
Value:
SL_SE_HASH_SHA512

HMAC-SHA-512.


SL_SE_CHALLENGE_SIZE#

#define SL_SE_CHALLENGE_SIZE
Value:
16

SE Challenge size.


SL_SE_CERT_KEY_SIZE#

#define SL_SE_CERT_KEY_SIZE
Value:
64

Certificate key size.


SL_SE_CERT_SIGN_SIZE#

#define SL_SE_CERT_SIGN_SIZE
Value:
64

Certificate signature size.


SL_SE_CERT_BATCH#

#define SL_SE_CERT_BATCH
Value:
0x01

Batch ID certificate.


SL_SE_CERT_DEVICE_SE#

#define SL_SE_CERT_DEVICE_SE
Value:
0x02

SE ID certificate.


SL_SE_CERT_DEVICE_HOST#

#define SL_SE_CERT_DEVICE_HOST
Value:
0x03

Host ID certificate.


SL_SE_TAMPER_LEVEL_IGNORE#

#define SL_SE_TAMPER_LEVEL_IGNORE
Value:
0

No action taken.


SL_SE_TAMPER_LEVEL_INTERRUPT#

#define SL_SE_TAMPER_LEVEL_INTERRUPT
Value:
1

Generate interrupt.


SL_SE_TAMPER_LEVEL_FILTER#

#define SL_SE_TAMPER_LEVEL_FILTER
Value:
2

Increment filter counter.


SL_SE_TAMPER_LEVEL_RESET#

#define SL_SE_TAMPER_LEVEL_RESET
Value:
4

System reset.


SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP#

#define SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP
Value:
7

Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!


SL_SE_TAMPER_SIGNAL_RESERVED_1#

#define SL_SE_TAMPER_SIGNAL_RESERVED_1
Value:
0x0

Reserved tamper signal.


SL_SE_TAMPER_SIGNAL_FILTER_COUNTER#

#define SL_SE_TAMPER_SIGNAL_FILTER_COUNTER
Value:
0x1

Filter counter exceeds threshold.


SL_SE_TAMPER_SIGNAL_WATCHDOG#

#define SL_SE_TAMPER_SIGNAL_WATCHDOG
Value:
0x2

SE watchdog timeout.


SL_SE_TAMPER_SIGNAL_CRYPTO_ERROR#

#define SL_SE_TAMPER_SIGNAL_CRYPTO_ERROR
Value:
0x3

Crypto error detected.


SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2#

#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2
Value:
0x4

SE RAM 2-bit ECC error.


SL_SE_TAMPER_SIGNAL_RESERVED_2#

#define SL_SE_TAMPER_SIGNAL_RESERVED_2
Value:
0x5

Reserved tamper signal.


SL_SE_TAMPER_SIGNAL_SE_MAJOR_FAULT#

#define SL_SE_TAMPER_SIGNAL_SE_MAJOR_FAULT
Value:
0x6

SE major fault detected.


SL_SE_TAMPER_SIGNAL_L2ICACHE#

#define SL_SE_TAMPER_SIGNAL_L2ICACHE
Value:
0x7

L2 instruction cache error.


SL_SE_TAMPER_SIGNAL_RESERVED_3#

#define SL_SE_TAMPER_SIGNAL_RESERVED_3
Value:
0x8

Reserved tamper signal.


SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED#

#define SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED
Value:
0x9

Secure boot of user code failed.


SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR#

#define SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR
Value:
0xA

Unauthorised command received over the Mailbox interface.


SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR#

#define SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR
Value:
0xB

Unauthorised command received over the DCI interface.


SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION#

#define SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION
Value:
0xC

SE software triggers an assert.


SL_SE_TAMPER_SIGNAL_RESERVED_4#

#define SL_SE_TAMPER_SIGNAL_RESERVED_4
Value:
0xD

Reserved tamper signal.


SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED#

#define SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED
Value:
0xE

Integrity error of internal storage is detected.


SL_SE_TAMPER_SIGNAL_TRNG_MONITOR#

#define SL_SE_TAMPER_SIGNAL_TRNG_MONITOR
Value:
0xF

TRNG monitor detected lack of entropy.


SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR#

#define SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR
Value:
0x10

Debug lock internal logic check failed.


SL_SE_TAMPER_ATAMPDET#

#define SL_SE_TAMPER_ATAMPDET
Value:
0x11

Any tamper detection.


SL_SE_TAMPER_SIGNAL_OTP_ALARM#

#define SL_SE_TAMPER_SIGNAL_OTP_ALARM
Value:
0x12

OTP alarm triggered.


SL_SE_TAMPER_SE_ICACHE_ERROR#

#define SL_SE_TAMPER_SE_ICACHE_ERROR
Value:
0x13

SE ICache RAM error.


SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1#

#define SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1
Value:
0x14

SE RAM 1-bit ECC error.


SL_SE_TAMPER_SIGNAL_BOD#

#define SL_SE_TAMPER_SIGNAL_BOD
Value:
0x15

Brown-out-detector threshold alert.


SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR#

#define SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR
Value:
0x16

On-device temperature sensor.


SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL#

#define SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL
Value:
0x17

DPLL lock failure.


SL_SE_TAMPER_SIGNAL_SOC_PLL_FAIL#

#define SL_SE_TAMPER_SIGNAL_SOC_PLL_FAIL
Value:
0x18

SoC PLL failure.


SL_SE_TAMPER_SIGNAL_ETAMPDET#

#define SL_SE_TAMPER_SIGNAL_ETAMPDET
Value:
0x19

External tamper detect.


SL_SE_TAMPER_SIGNAL_KSU_ECC_1#

#define SL_SE_TAMPER_SIGNAL_KSU_ECC_1
Value:
0x1A

KSU ECC 1-bit error.


SL_SE_TAMPER_SIGNAL_KSU_ECC_2#

#define SL_SE_TAMPER_SIGNAL_KSU_ECC_2
Value:
0x1B

KSU ECC 2-bit error.


SL_SE_TAMPER_SIGNAL_QSPI_RESEED_ERR#

#define SL_SE_TAMPER_SIGNAL_QSPI_RESEED_ERR
Value:
0x1C

QSPI reseed error.


SL_SE_TAMPER_SIGNAL_PRS0#

#define SL_SE_TAMPER_SIGNAL_PRS0
Value:
0x1D

PRS channel 0 asserted.


SL_SE_TAMPER_SIGNAL_PRS1#

#define SL_SE_TAMPER_SIGNAL_PRS1
Value:
0x1E

PRS channel 1 asserted.


SL_SE_TAMPER_SIGNAL_PRS2#

#define SL_SE_TAMPER_SIGNAL_PRS2
Value:
0x1F

PRS channel 2 asserted.


SL_SE_TAMPER_SIGNAL_NUM_SIGNALS#

#define SL_SE_TAMPER_SIGNAL_NUM_SIGNALS
Value:
0x20

Number of tamper signals.


SL_SE_TAMPER_FILTER_PERIOD_32MS#

#define SL_SE_TAMPER_FILTER_PERIOD_32MS
Value:
0x0

Timeout ~32ms.


SL_SE_TAMPER_FILTER_PERIOD_64MS#

#define SL_SE_TAMPER_FILTER_PERIOD_64MS
Value:
0x1

Timeout ~64ms.


SL_SE_TAMPER_FILTER_PERIOD_128MS#

#define SL_SE_TAMPER_FILTER_PERIOD_128MS
Value:
0x2

Timeout ~128ms.


SL_SE_TAMPER_FILTER_PERIOD_256MS#

#define SL_SE_TAMPER_FILTER_PERIOD_256MS
Value:
0x3

Timeout ~256ms.


SL_SE_TAMPER_FILTER_PERIOD_512MS#

#define SL_SE_TAMPER_FILTER_PERIOD_512MS
Value:
0x4

Timeout ~512ms.


SL_SE_TAMPER_FILTER_PERIOD_1S#

#define SL_SE_TAMPER_FILTER_PERIOD_1S
Value:
0x5

Timeout ~1s.


SL_SE_TAMPER_FILTER_PERIOD_2S#

#define SL_SE_TAMPER_FILTER_PERIOD_2S
Value:
0x6

Timeout ~2s.


SL_SE_TAMPER_FILTER_PERIOD_4S#

#define SL_SE_TAMPER_FILTER_PERIOD_4S
Value:
0x7

Timeout ~4.1s.


SL_SE_TAMPER_FILTER_PERIOD_8S#

#define SL_SE_TAMPER_FILTER_PERIOD_8S
Value:
0x8

Timeout ~8.2s.


SL_SE_TAMPER_FILTER_PERIOD_16S#

#define SL_SE_TAMPER_FILTER_PERIOD_16S
Value:
0x9

Timeout ~16.4s.


SL_SE_TAMPER_FILTER_PERIOD_33S#

#define SL_SE_TAMPER_FILTER_PERIOD_33S
Value:
0xA

Timeout ~32.8s.


SL_SE_TAMPER_FILTER_PERIOD_1MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_1MIN
Value:
0xB

Timeout ~1.1min.


SL_SE_TAMPER_FILTER_PERIOD_2MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_2MIN
Value:
0xC

Timeout ~2.2min.


SL_SE_TAMPER_FILTER_PERIOD_4MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_4MIN
Value:
0xD

Timeout ~4.4min.


SL_SE_TAMPER_FILTER_PERIOD_9MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_9MIN
Value:
0xE

Timeout ~8.7min.


SL_SE_TAMPER_FILTER_PERIOD_18MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_18MIN
Value:
0xF

Timeout ~17.5min.


SL_SE_TAMPER_FILTER_PERIOD_35MIN#

#define SL_SE_TAMPER_FILTER_PERIOD_35MIN
Value:
0x10

Timeout ~35min.


SL_SE_TAMPER_FILTER_PERIOD_1H#

#define SL_SE_TAMPER_FILTER_PERIOD_1H
Value:
0x11

Timeout ~1.2h.


SL_SE_TAMPER_FILTER_PERIOD_2H#

#define SL_SE_TAMPER_FILTER_PERIOD_2H
Value:
0x12

Timeout ~2.3h.


SL_SE_TAMPER_FILTER_PERIOD_5H#

#define SL_SE_TAMPER_FILTER_PERIOD_5H
Value:
0x13

Timeout ~4.7h.


SL_SE_TAMPER_FILTER_PERIOD_9H#

#define SL_SE_TAMPER_FILTER_PERIOD_9H
Value:
0x14

Timeout ~9.3h.


SL_SE_TAMPER_FILTER_PERIOD_19H#

#define SL_SE_TAMPER_FILTER_PERIOD_19H
Value:
0x15

Timeout ~18.6h.


SL_SE_TAMPER_FILTER_PERIOD_2DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_2DAYS
Value:
0x16

Timeout ~1.6days.


SL_SE_TAMPER_FILTER_PERIOD_3DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_3DAYS
Value:
0x17

Timeout ~3.1days.


SL_SE_TAMPER_FILTER_PERIOD_6DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_6DAYS
Value:
0x18

Timeout ~6.2days.


SL_SE_TAMPER_FILTER_PERIOD_12DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_12DAYS
Value:
0x19

Timeout ~12.4days.


SL_SE_TAMPER_FILTER_PERIOD_25DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_25DAYS
Value:
0x1A

Timeout ~24.9days.


SL_SE_TAMPER_FILTER_PERIOD_50DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_50DAYS
Value:
0x1B

Timeout ~49.7days.


SL_SE_TAMPER_FILTER_PERIOD_100DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_100DAYS
Value:
0x1C

Timeout ~99.4days.


SL_SE_TAMPER_FILTER_PERIOD_199DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_199DAYS
Value:
0x1D

Timeout ~198.8days.


SL_SE_TAMPER_FILTER_PERIOD_398DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_398DAYS
Value:
0x1E

Timeout ~397.7days.


SL_SE_TAMPER_FILTER_PERIOD_795DAYS#

#define SL_SE_TAMPER_FILTER_PERIOD_795DAYS
Value:
0x1F

Timeout ~795.4days.


SL_SE_TAMPER_FILTER_THRESHOLD_2#

#define SL_SE_TAMPER_FILTER_THRESHOLD_2
Value:
0x7

Counter threshold 2.


SL_SE_TAMPER_FILTER_THRESHOLD_4#

#define SL_SE_TAMPER_FILTER_THRESHOLD_4
Value:
0x6

Counter threshold 4.


SL_SE_TAMPER_FILTER_THRESHOLD_8#

#define SL_SE_TAMPER_FILTER_THRESHOLD_8
Value:
0x5

Counter threshold 8.


SL_SE_TAMPER_FILTER_THRESHOLD_16#

#define SL_SE_TAMPER_FILTER_THRESHOLD_16
Value:
0x4

Counter threshold 16.


SL_SE_TAMPER_FILTER_THRESHOLD_32#

#define SL_SE_TAMPER_FILTER_THRESHOLD_32
Value:
0x3

Counter threshold 32.


SL_SE_TAMPER_FILTER_THRESHOLD_64#

#define SL_SE_TAMPER_FILTER_THRESHOLD_64
Value:
0x2

Counter threshold 64.


SL_SE_TAMPER_FILTER_THRESHOLD_128#

#define SL_SE_TAMPER_FILTER_THRESHOLD_128
Value:
0x1

Counter threshold 128.


SL_SE_TAMPER_FILTER_THRESHOLD_256#

#define SL_SE_TAMPER_FILTER_THRESHOLD_256
Value:
0x0

Counter threshold 256.


SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON#

#define SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON
Value:
(1UL << 1)

Tamper flags.

Digital glitch detector always on


SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP#

#define SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP
Value:
(1UL << 2)

Tamper is kept alive during sleep (down to EM3)


SL_SE_AES_BLOCK_SIZE#

#define SL_SE_AES_BLOCK_SIZE
Value:
(16u)

Block size for the AES.


SL_SE_HASH_STREAMING_INIT_DEFAULT#

#define SL_SE_HASH_STREAMING_INIT_DEFAULT
Value:
{ NULL, 0, 0, NULL }

Default streaming hash context.


SL_SE_SHA1_STREAMING_INIT_DEFAULT#

#define SL_SE_SHA1_STREAMING_INIT_DEFAULT
Value:
{ { 0 }, { 0 }, { 0 } }

SHA1 streaming hash context.


SL_SE_SHA224_STREAMING_INIT_DEFAULT#

#define SL_SE_SHA224_STREAMING_INIT_DEFAULT
Value:
{ { 0 }, { 0 }, { 0 } }

SHA224 streaming hash context.


SL_SE_SHA256_STREAMING_INIT_DEFAULT#

#define SL_SE_SHA256_STREAMING_INIT_DEFAULT
Value:
{ { 0 }, { 0 }, { 0 } }

SHA256 streaming hash context.


SL_SE_SHA384_STREAMING_INIT_DEFAULT#

#define SL_SE_SHA384_STREAMING_INIT_DEFAULT
Value:
{ { 0 }, { 0 }, { 0 } }

SHA384 streaming hash context.


SL_SE_SHA512_STREAMING_INIT_DEFAULT#

#define SL_SE_SHA512_STREAMING_INIT_DEFAULT
Value:
{ { 0 }, { 0 }, { 0 } }

SHA512 streaming hash context.


SL_SE_MAX_CODE_REGIONS#

#define SL_SE_MAX_CODE_REGIONS
Value:
8

The maximum number of code regions available on the device.

The number of available code regions may be different on future devices.