Device Manager DMA#
Portable (device independent) DMA configuration enums.
Overview#
This header provides abstract, device-agnostic enumerations for common DMA configuration parameters. They intentionally avoid binding their enumerator values to any specific device register encodings. A mapping layer (typically within the HAL or driver implementation) is expected to translate these portable values to device-specific register fields.
The goal is to allow higher-level components, code generators and configuration tooling to reference DMA attributes without pulling in device headers or conditional compilation based on device series.
The enums defined here SHOULD NOT be assumed to match any hardware bit patterns. Only their relative meaning is guaranteed.
DMA Signal Defines#
Those defines can be used as constant of type sl_dma_signal_t The values of those defines are device specific.
Define for No Signal.
Define for LDMAXBAR0_PRSREQ0 DMA Signal.
Define for LDMAXBAR0_PRSREQ1 DMA Signal.
Define for TIMER0 CC0 DMA Signal.
Define for TIMER0 CC1 DMA Signal.
Define for TIMER0 CC2 DMA Signal.
Define for TIMER0 UFOF DMA Signal.
Define for TIMER0 CC3 DMA Signal.
Define for TIMER0 CC4 DMA Signal.
Define for TIMER0 CC5 DMA Signal.
Define for TIMER0 CC6 DMA Signal.
Define for TIMER1 CC0 DMA Signal.
Define for TIMER1 CC1 DMA Signal.
Define for TIMER1 CC2 DMA Signal.
Define for TIMER1 UFOF DMA Signal.
Define for TIMER1 CC3 DMA Signal.
Define for TIMER1 CC4 DMA Signal.
Define for TIMER1 CC5 DMA Signal.
Define for TIMER1 CC6 DMA Signal.
Define for TIMER2 CC0 DMA Signal.
Define for TIMER2 CC1 DMA Signal.
Define for TIMER2 CC2 DMA Signal.
Define for TIMER2 UFOF DMA Signal.
Define for TIMER2 CC3 DMA Signal.
Define for TIMER2 CC4 DMA Signal.
Define for TIMER2 CC5 DMA Signal.
Define for TIMER2 CC6 DMA Signal.
Define for TIMER3 CC0 DMA Signal.
Define for TIMER3 CC1 DMA Signal.
Define for TIMER3 CC2 DMA Signal.
Define for TIMER3 UFOF DMA Signal.
Define for TIMER3 CC3 DMA Signal.
Define for TIMER3 CC4 DMA Signal.
Define for TIMER3 CC5 DMA Signal.
Define for TIMER3 CC6 DMA Signal.
Define for TIMER4 CC0 DMA Signal.
Define for TIMER4 CC1 DMA Signal.
Define for TIMER4 CC2 DMA Signal.
Define for TIMER4 UFOF DMA Signal.
Define for TIMER5 CC0 DMA Signal.
Define for TIMER5 CC1 DMA Signal.
Define for TIMER5 CC2 DMA Signal.
Define for TIMER5 UFOF DMA Signal.
Define for TIMER6 CC0 DMA Signal.
Define for TIMER6 CC1 DMA Signal.
Define for TIMER6 CC2 DMA Signal.
Define for TIMER6 UFOF DMA Signal.
Define for TIMER6 CC3 DMA Signal.
Define for TIMER6 CC4 DMA Signal.
Define for TIMER6 CC5 DMA Signal.
Define for TIMER6 CC6 DMA Signal.
Define for TIMER7 CC0 DMA Signal.
Define for TIMER7 CC1 DMA Signal.
Define for TIMER7 CC2 DMA Signal.
Define for TIMER7 UFOF DMA Signal.
Define for TIMER7 CC3 DMA Signal.
Define for TIMER7 CC4 DMA Signal.
Define for TIMER7 CC5 DMA Signal.
Define for TIMER7 CC6 DMA Signal.
Define for TIMER8 CC0 DMA Signal.
Define for TIMER8 CC1 DMA Signal.
Define for TIMER8 CC2 DMA Signal.
Define for TIMER8 UFOF DMA Signal.
Define for TIMER9 CC0 DMA Signal.
Define for TIMER9 CC1 DMA Signal.
Define for TIMER9 CC2 DMA Signal.
Define for TIMER9 UFOF DMA Signal.
Define for PROTIMER BOF DMA Signal.
Define for PROTIMER CC0 DMA Signal.
Define for PROTIMER CC1 DMA Signal.
Define for PROTIMER CC2 DMA Signal.
Define for PROTIMER CC3 DMA Signal.
Define for PROTIMER POF DMA Signal.
Define for PROTIMER WOF DMA Signal.
Define for I2C0 RXDATAV DMA Signal.
Define for I2C0 TXBL DMA Signal.
Define for I2C1 RXDATAV DMA Signal.
Define for I2C1 TXBL DMA Signal.
Define for I2C2 RXDATAV DMA Signal.
Define for I2C2 TXBL DMA Signal.
Define for I2C3 RXDATAV DMA Signal.
Define for I2C3 TXBL DMA Signal.
Define for ADC0 SCAN DMA Signal.
Define for ADC1 SCAN DMA Signal.
Define for ADC2 SCAN DMA Signal.
Define for ADC3 SCAN DMA Signal.
Define for IADC0 SCAN DMA Signal.
Define for IADC0 SINGLE DMA Signal.
Define for EUSART0 RXFL DMA Signal.
Define for EUSART0 TXFL DMA Signal.
Define for EUSART1 RXFL DMA Signal.
Define for EUSART1 TXFL DMA Signal.
Define for EUSART2 RXFL DMA Signal.
Define for EUSART2 TXFL DMA Signal.
Define for EUSART3 RXFL DMA Signal.
Define for EUSART3 TXFL DMA Signal.
Define for EUSART4 RXFL DMA Signal.
Define for EUSART4 TXFL DMA Signal.
Define for EUSART5 RXFL DMA Signal.
Define for EUSART5 TXFL DMA Signal.
Define for EUSART6 RXFL DMA Signal.
Define for EUSART6 TXFL DMA Signal.
Define for EUSART7 RXFL DMA Signal.
Define for EUSART7 TXFL DMA Signal.
Define for USART0 RXDATAV DMA Signal.
Define for USART0 RXDATAVRIGHT DMA Signal.
Define for USART0 TXBL DMA Signal.
Define for USART0 TXBLRIGHT DMA Signal.
Define for USART0 TXEMPTY DMA Signal.
Define for USART1 RXDATAV DMA Signal.
Define for USART1 RXDATAVRIGHT DMA Signal.
Define for USART1 TXBL DMA Signal.
Define for USART1 TXBLRIGHT DMA Signal.
Define for USART1 TXEMPTY DMA Signal.
Define for USART2 RXDATAV DMA Signal.
Define for USART2 RXDATAVRIGHT DMA Signal.
Define for USART2 TXBL DMA Signal.
Define for USART2 TXBLRIGHT DMA Signal.
Define for USART2 TXEMPTY DMA Signal.
Define for EUART0 RXFL DMA Signal.
Define for EUART0 TXFL DMA Signal.
Define for MSC WDATA DMA Signal.
Define for MVP REQ DMA Signal.
Define for PIXELRZ0REQ TXF DMA Signal.
Define for PIXELRZ1REQ TXF DMA Signal.
Define for PDM RXDATAV DMA Signal.
Define for PDM0 RXDATA DMA Signal.
Define for LCD DMA Signal.
Define for LESENSE FIFO Signal.
Define for VDAC0 CH0 REQ Signal.
Define for VDAC0 CH1 REQ Signal.
Define for VDAC1 CH0 REQ Signal.
Define for VDAC1 CH1 REQ Signal.
Define for CAN0 RXFL0 DMA Signal.
Define for CAN0 RXFL1 DMA Signal.
Define for CAN0 TXFL0 DMA Signal.
Define for CAN0 TXFL1 DMA Signal.
Define for CAN1 RXFL0 DMA Signal.
Define for CAN1 RXFL1 DMA Signal.
Define for CAN1 TXFL0 DMA Signal.
Define for CAN1 TXFL1 DMA Signal.
Enumerations#
DMA transfer unit size (portable semantic values)
Number of unit transfers granted per arbitration opportunity.
Typedefs#
The DMA signal typedef.
Macros#
Validate transfer unit size value.
Validate block size enum value.
Validate peripheral signal selection (excluding COUNT sentinel).
DMA Signal Defines Documentation#
SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ0#
#define SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ0Value:
(&SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ0_VALUE)
Define for LDMAXBAR0_PRSREQ0 DMA Signal.
SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ1#
#define SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ1Value:
(&SL_DMA_SIGNAL_LDMAXBAR0_PRSREQ1_VALUE)
Define for LDMAXBAR0_PRSREQ1 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC0#
#define SL_DMA_SIGNAL_TIMER0_CC0Value:
(&SL_DMA_SIGNAL_TIMER0_CC0_VALUE)
Define for TIMER0 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC1#
#define SL_DMA_SIGNAL_TIMER0_CC1Value:
(&SL_DMA_SIGNAL_TIMER0_CC1_VALUE)
Define for TIMER0 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC2#
#define SL_DMA_SIGNAL_TIMER0_CC2Value:
(&SL_DMA_SIGNAL_TIMER0_CC2_VALUE)
Define for TIMER0 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER0_UFOF#
#define SL_DMA_SIGNAL_TIMER0_UFOFValue:
(&SL_DMA_SIGNAL_TIMER0_UFOF_VALUE)
Define for TIMER0 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC3#
#define SL_DMA_SIGNAL_TIMER0_CC3Value:
(&SL_DMA_SIGNAL_TIMER0_CC3_VALUE)
Define for TIMER0 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC4#
#define SL_DMA_SIGNAL_TIMER0_CC4Value:
(&SL_DMA_SIGNAL_TIMER0_CC4_VALUE)
Define for TIMER0 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC5#
#define SL_DMA_SIGNAL_TIMER0_CC5Value:
(&SL_DMA_SIGNAL_TIMER0_CC5_VALUE)
Define for TIMER0 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER0_CC6#
#define SL_DMA_SIGNAL_TIMER0_CC6Value:
(&SL_DMA_SIGNAL_TIMER0_CC6_VALUE)
Define for TIMER0 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC0#
#define SL_DMA_SIGNAL_TIMER1_CC0Value:
(&SL_DMA_SIGNAL_TIMER1_CC0_VALUE)
Define for TIMER1 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC1#
#define SL_DMA_SIGNAL_TIMER1_CC1Value:
(&SL_DMA_SIGNAL_TIMER1_CC1_VALUE)
Define for TIMER1 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC2#
#define SL_DMA_SIGNAL_TIMER1_CC2Value:
(&SL_DMA_SIGNAL_TIMER1_CC2_VALUE)
Define for TIMER1 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER1_UFOF#
#define SL_DMA_SIGNAL_TIMER1_UFOFValue:
(&SL_DMA_SIGNAL_TIMER1_UFOF_VALUE)
Define for TIMER1 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC3#
#define SL_DMA_SIGNAL_TIMER1_CC3Value:
(&SL_DMA_SIGNAL_TIMER1_CC3_VALUE)
Define for TIMER1 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC4#
#define SL_DMA_SIGNAL_TIMER1_CC4Value:
(&SL_DMA_SIGNAL_TIMER1_CC4_VALUE)
Define for TIMER1 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC5#
#define SL_DMA_SIGNAL_TIMER1_CC5Value:
(&SL_DMA_SIGNAL_TIMER1_CC5_VALUE)
Define for TIMER1 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER1_CC6#
#define SL_DMA_SIGNAL_TIMER1_CC6Value:
(&SL_DMA_SIGNAL_TIMER1_CC6_VALUE)
Define for TIMER1 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC0#
#define SL_DMA_SIGNAL_TIMER2_CC0Value:
(&SL_DMA_SIGNAL_TIMER2_CC0_VALUE)
Define for TIMER2 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC1#
#define SL_DMA_SIGNAL_TIMER2_CC1Value:
(&SL_DMA_SIGNAL_TIMER2_CC1_VALUE)
Define for TIMER2 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC2#
#define SL_DMA_SIGNAL_TIMER2_CC2Value:
(&SL_DMA_SIGNAL_TIMER2_CC2_VALUE)
Define for TIMER2 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER2_UFOF#
#define SL_DMA_SIGNAL_TIMER2_UFOFValue:
(&SL_DMA_SIGNAL_TIMER2_UFOF_VALUE)
Define for TIMER2 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC3#
#define SL_DMA_SIGNAL_TIMER2_CC3Value:
(&SL_DMA_SIGNAL_TIMER2_CC3_VALUE)
Define for TIMER2 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC4#
#define SL_DMA_SIGNAL_TIMER2_CC4Value:
(&SL_DMA_SIGNAL_TIMER2_CC4_VALUE)
Define for TIMER2 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC5#
#define SL_DMA_SIGNAL_TIMER2_CC5Value:
(&SL_DMA_SIGNAL_TIMER2_CC5_VALUE)
Define for TIMER2 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER2_CC6#
#define SL_DMA_SIGNAL_TIMER2_CC6Value:
(&SL_DMA_SIGNAL_TIMER2_CC6_VALUE)
Define for TIMER2 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC0#
#define SL_DMA_SIGNAL_TIMER3_CC0Value:
(&SL_DMA_SIGNAL_TIMER3_CC0_VALUE)
Define for TIMER3 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC1#
#define SL_DMA_SIGNAL_TIMER3_CC1Value:
(&SL_DMA_SIGNAL_TIMER3_CC1_VALUE)
Define for TIMER3 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC2#
#define SL_DMA_SIGNAL_TIMER3_CC2Value:
(&SL_DMA_SIGNAL_TIMER3_CC2_VALUE)
Define for TIMER3 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER3_UFOF#
#define SL_DMA_SIGNAL_TIMER3_UFOFValue:
(&SL_DMA_SIGNAL_TIMER3_UFOF_VALUE)
Define for TIMER3 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC3#
#define SL_DMA_SIGNAL_TIMER3_CC3Value:
(&SL_DMA_SIGNAL_TIMER3_CC3_VALUE)
Define for TIMER3 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC4#
#define SL_DMA_SIGNAL_TIMER3_CC4Value:
(&SL_DMA_SIGNAL_TIMER3_CC4_VALUE)
Define for TIMER3 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC5#
#define SL_DMA_SIGNAL_TIMER3_CC5Value:
(&SL_DMA_SIGNAL_TIMER3_CC5_VALUE)
Define for TIMER3 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER3_CC6#
#define SL_DMA_SIGNAL_TIMER3_CC6Value:
(&SL_DMA_SIGNAL_TIMER3_CC6_VALUE)
Define for TIMER3 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER4_CC0#
#define SL_DMA_SIGNAL_TIMER4_CC0Value:
(&SL_DMA_SIGNAL_TIMER4_CC0_VALUE)
Define for TIMER4 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER4_CC1#
#define SL_DMA_SIGNAL_TIMER4_CC1Value:
(&SL_DMA_SIGNAL_TIMER4_CC1_VALUE)
Define for TIMER4 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER4_CC2#
#define SL_DMA_SIGNAL_TIMER4_CC2Value:
(&SL_DMA_SIGNAL_TIMER4_CC2_VALUE)
Define for TIMER4 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER4_UFOF#
#define SL_DMA_SIGNAL_TIMER4_UFOFValue:
(&SL_DMA_SIGNAL_TIMER4_UFOF_VALUE)
Define for TIMER4 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER5_CC0#
#define SL_DMA_SIGNAL_TIMER5_CC0Value:
(&SL_DMA_SIGNAL_TIMER5_CC0_VALUE)
Define for TIMER5 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER5_CC1#
#define SL_DMA_SIGNAL_TIMER5_CC1Value:
(&SL_DMA_SIGNAL_TIMER5_CC1_VALUE)
Define for TIMER5 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER5_CC2#
#define SL_DMA_SIGNAL_TIMER5_CC2Value:
(&SL_DMA_SIGNAL_TIMER5_CC2_VALUE)
Define for TIMER5 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER5_UFOF#
#define SL_DMA_SIGNAL_TIMER5_UFOFValue:
(&SL_DMA_SIGNAL_TIMER5_UFOF_VALUE)
Define for TIMER5 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC0#
#define SL_DMA_SIGNAL_TIMER6_CC0Value:
(&SL_DMA_SIGNAL_TIMER6_CC0_VALUE)
Define for TIMER6 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC1#
#define SL_DMA_SIGNAL_TIMER6_CC1Value:
(&SL_DMA_SIGNAL_TIMER6_CC1_VALUE)
Define for TIMER6 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC2#
#define SL_DMA_SIGNAL_TIMER6_CC2Value:
(&SL_DMA_SIGNAL_TIMER6_CC2_VALUE)
Define for TIMER6 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER6_UFOF#
#define SL_DMA_SIGNAL_TIMER6_UFOFValue:
(&SL_DMA_SIGNAL_TIMER6_UFOF_VALUE)
Define for TIMER6 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC3#
#define SL_DMA_SIGNAL_TIMER6_CC3Value:
(&SL_DMA_SIGNAL_TIMER6_CC3_VALUE)
Define for TIMER6 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC4#
#define SL_DMA_SIGNAL_TIMER6_CC4Value:
(&SL_DMA_SIGNAL_TIMER6_CC4_VALUE)
Define for TIMER6 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC5#
#define SL_DMA_SIGNAL_TIMER6_CC5Value:
(&SL_DMA_SIGNAL_TIMER6_CC5_VALUE)
Define for TIMER6 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER6_CC6#
#define SL_DMA_SIGNAL_TIMER6_CC6Value:
(&SL_DMA_SIGNAL_TIMER6_CC6_VALUE)
Define for TIMER6 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC0#
#define SL_DMA_SIGNAL_TIMER7_CC0Value:
(&SL_DMA_SIGNAL_TIMER7_CC0_VALUE)
Define for TIMER7 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC1#
#define SL_DMA_SIGNAL_TIMER7_CC1Value:
(&SL_DMA_SIGNAL_TIMER7_CC1_VALUE)
Define for TIMER7 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC2#
#define SL_DMA_SIGNAL_TIMER7_CC2Value:
(&SL_DMA_SIGNAL_TIMER7_CC2_VALUE)
Define for TIMER7 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER7_UFOF#
#define SL_DMA_SIGNAL_TIMER7_UFOFValue:
(&SL_DMA_SIGNAL_TIMER7_UFOF_VALUE)
Define for TIMER7 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC3#
#define SL_DMA_SIGNAL_TIMER7_CC3Value:
(&SL_DMA_SIGNAL_TIMER7_CC3_VALUE)
Define for TIMER7 CC3 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC4#
#define SL_DMA_SIGNAL_TIMER7_CC4Value:
(&SL_DMA_SIGNAL_TIMER7_CC4_VALUE)
Define for TIMER7 CC4 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC5#
#define SL_DMA_SIGNAL_TIMER7_CC5Value:
(&SL_DMA_SIGNAL_TIMER7_CC5_VALUE)
Define for TIMER7 CC5 DMA Signal.
SL_DMA_SIGNAL_TIMER7_CC6#
#define SL_DMA_SIGNAL_TIMER7_CC6Value:
(&SL_DMA_SIGNAL_TIMER7_CC6_VALUE)
Define for TIMER7 CC6 DMA Signal.
SL_DMA_SIGNAL_TIMER8_CC0#
#define SL_DMA_SIGNAL_TIMER8_CC0Value:
(&SL_DMA_SIGNAL_TIMER8_CC0_VALUE)
Define for TIMER8 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER8_CC1#
#define SL_DMA_SIGNAL_TIMER8_CC1Value:
(&SL_DMA_SIGNAL_TIMER8_CC1_VALUE)
Define for TIMER8 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER8_CC2#
#define SL_DMA_SIGNAL_TIMER8_CC2Value:
(&SL_DMA_SIGNAL_TIMER8_CC2_VALUE)
Define for TIMER8 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER8_UFOF#
#define SL_DMA_SIGNAL_TIMER8_UFOFValue:
(&SL_DMA_SIGNAL_TIMER8_UFOF_VALUE)
Define for TIMER8 UFOF DMA Signal.
SL_DMA_SIGNAL_TIMER9_CC0#
#define SL_DMA_SIGNAL_TIMER9_CC0Value:
(&SL_DMA_SIGNAL_TIMER9_CC0_VALUE)
Define for TIMER9 CC0 DMA Signal.
SL_DMA_SIGNAL_TIMER9_CC1#
#define SL_DMA_SIGNAL_TIMER9_CC1Value:
(&SL_DMA_SIGNAL_TIMER9_CC1_VALUE)
Define for TIMER9 CC1 DMA Signal.
SL_DMA_SIGNAL_TIMER9_CC2#
#define SL_DMA_SIGNAL_TIMER9_CC2Value:
(&SL_DMA_SIGNAL_TIMER9_CC2_VALUE)
Define for TIMER9 CC2 DMA Signal.
SL_DMA_SIGNAL_TIMER9_UFOF#
#define SL_DMA_SIGNAL_TIMER9_UFOFValue:
(&SL_DMA_SIGNAL_TIMER9_UFOF_VALUE)
Define for TIMER9 UFOF DMA Signal.
SL_DMA_SIGNAL_PROTIMER_BOF#
#define SL_DMA_SIGNAL_PROTIMER_BOFValue:
(&SL_DMA_SIGNAL_PROTIMER_BOF_VALUE)
Define for PROTIMER BOF DMA Signal.
SL_DMA_SIGNAL_PROTIMER_CC0#
#define SL_DMA_SIGNAL_PROTIMER_CC0Value:
(&SL_DMA_SIGNAL_PROTIMER_CC0_VALUE)
Define for PROTIMER CC0 DMA Signal.
SL_DMA_SIGNAL_PROTIMER_CC1#
#define SL_DMA_SIGNAL_PROTIMER_CC1Value:
(&SL_DMA_SIGNAL_PROTIMER_CC1_VALUE)
Define for PROTIMER CC1 DMA Signal.
SL_DMA_SIGNAL_PROTIMER_CC2#
#define SL_DMA_SIGNAL_PROTIMER_CC2Value:
(&SL_DMA_SIGNAL_PROTIMER_CC2_VALUE)
Define for PROTIMER CC2 DMA Signal.
SL_DMA_SIGNAL_PROTIMER_CC3#
#define SL_DMA_SIGNAL_PROTIMER_CC3Value:
(&SL_DMA_SIGNAL_PROTIMER_CC3_VALUE)
Define for PROTIMER CC3 DMA Signal.
SL_DMA_SIGNAL_PROTIMER_POF#
#define SL_DMA_SIGNAL_PROTIMER_POFValue:
(&SL_DMA_SIGNAL_PROTIMER_POF_VALUE)
Define for PROTIMER POF DMA Signal.
SL_DMA_SIGNAL_PROTIMER_WOF#
#define SL_DMA_SIGNAL_PROTIMER_WOFValue:
(&SL_DMA_SIGNAL_PROTIMER_WOF_VALUE)
Define for PROTIMER WOF DMA Signal.
SL_DMA_SIGNAL_I2C0_RXDATAV#
#define SL_DMA_SIGNAL_I2C0_RXDATAVValue:
(&SL_DMA_SIGNAL_I2C0_RXDATAV_VALUE)
Define for I2C0 RXDATAV DMA Signal.
SL_DMA_SIGNAL_I2C0_TXBL#
#define SL_DMA_SIGNAL_I2C0_TXBLValue:
(&SL_DMA_SIGNAL_I2C0_TXBL_VALUE)
Define for I2C0 TXBL DMA Signal.
SL_DMA_SIGNAL_I2C1_RXDATAV#
#define SL_DMA_SIGNAL_I2C1_RXDATAVValue:
(&SL_DMA_SIGNAL_I2C1_RXDATAV_VALUE)
Define for I2C1 RXDATAV DMA Signal.
SL_DMA_SIGNAL_I2C1_TXBL#
#define SL_DMA_SIGNAL_I2C1_TXBLValue:
(&SL_DMA_SIGNAL_I2C1_TXBL_VALUE)
Define for I2C1 TXBL DMA Signal.
SL_DMA_SIGNAL_I2C2_RXDATAV#
#define SL_DMA_SIGNAL_I2C2_RXDATAVValue:
(&SL_DMA_SIGNAL_I2C2_RXDATAV_VALUE)
Define for I2C2 RXDATAV DMA Signal.
SL_DMA_SIGNAL_I2C2_TXBL#
#define SL_DMA_SIGNAL_I2C2_TXBLValue:
(&SL_DMA_SIGNAL_I2C2_TXBL_VALUE)
Define for I2C2 TXBL DMA Signal.
SL_DMA_SIGNAL_I2C3_RXDATAV#
#define SL_DMA_SIGNAL_I2C3_RXDATAVValue:
(&SL_DMA_SIGNAL_I2C3_RXDATAV_VALUE)
Define for I2C3 RXDATAV DMA Signal.
SL_DMA_SIGNAL_I2C3_TXBL#
#define SL_DMA_SIGNAL_I2C3_TXBLValue:
(&SL_DMA_SIGNAL_I2C3_TXBL_VALUE)
Define for I2C3 TXBL DMA Signal.
SL_DMA_SIGNAL_ADC0_SCAN#
#define SL_DMA_SIGNAL_ADC0_SCANValue:
(&SL_DMA_SIGNAL_ADC0_SCAN_VALUE)
Define for ADC0 SCAN DMA Signal.
SL_DMA_SIGNAL_ADC1_SCAN#
#define SL_DMA_SIGNAL_ADC1_SCANValue:
(&SL_DMA_SIGNAL_ADC1_SCAN_VALUE)
Define for ADC1 SCAN DMA Signal.
SL_DMA_SIGNAL_ADC2_SCAN#
#define SL_DMA_SIGNAL_ADC2_SCANValue:
(&SL_DMA_SIGNAL_ADC2_SCAN_VALUE)
Define for ADC2 SCAN DMA Signal.
SL_DMA_SIGNAL_ADC3_SCAN#
#define SL_DMA_SIGNAL_ADC3_SCANValue:
(&SL_DMA_SIGNAL_ADC3_SCAN_VALUE)
Define for ADC3 SCAN DMA Signal.
SL_DMA_SIGNAL_IADC0_SCAN#
#define SL_DMA_SIGNAL_IADC0_SCANValue:
(&SL_DMA_SIGNAL_IADC0_SCAN_VALUE)
Define for IADC0 SCAN DMA Signal.
SL_DMA_SIGNAL_IADC0_SINGLE#
#define SL_DMA_SIGNAL_IADC0_SINGLEValue:
(&SL_DMA_SIGNAL_IADC0_SINGLE_VALUE)
Define for IADC0 SINGLE DMA Signal.
SL_DMA_SIGNAL_EUSART0_RXFL#
#define SL_DMA_SIGNAL_EUSART0_RXFLValue:
(&SL_DMA_SIGNAL_EUSART0_RXFL_VALUE)
Define for EUSART0 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART0_TXFL#
#define SL_DMA_SIGNAL_EUSART0_TXFLValue:
(&SL_DMA_SIGNAL_EUSART0_TXFL_VALUE)
Define for EUSART0 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART1_RXFL#
#define SL_DMA_SIGNAL_EUSART1_RXFLValue:
(&SL_DMA_SIGNAL_EUSART1_RXFL_VALUE)
Define for EUSART1 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART1_TXFL#
#define SL_DMA_SIGNAL_EUSART1_TXFLValue:
(&SL_DMA_SIGNAL_EUSART1_TXFL_VALUE)
Define for EUSART1 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART2_RXFL#
#define SL_DMA_SIGNAL_EUSART2_RXFLValue:
(&SL_DMA_SIGNAL_EUSART2_RXFL_VALUE)
Define for EUSART2 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART2_TXFL#
#define SL_DMA_SIGNAL_EUSART2_TXFLValue:
(&SL_DMA_SIGNAL_EUSART2_TXFL_VALUE)
Define for EUSART2 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART3_RXFL#
#define SL_DMA_SIGNAL_EUSART3_RXFLValue:
(&SL_DMA_SIGNAL_EUSART3_RXFL_VALUE)
Define for EUSART3 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART3_TXFL#
#define SL_DMA_SIGNAL_EUSART3_TXFLValue:
(&SL_DMA_SIGNAL_EUSART3_TXFL_VALUE)
Define for EUSART3 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART4_RXFL#
#define SL_DMA_SIGNAL_EUSART4_RXFLValue:
(&SL_DMA_SIGNAL_EUSART4_RXFL_VALUE)
Define for EUSART4 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART4_TXFL#
#define SL_DMA_SIGNAL_EUSART4_TXFLValue:
(&SL_DMA_SIGNAL_EUSART4_TXFL_VALUE)
Define for EUSART4 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART5_RXFL#
#define SL_DMA_SIGNAL_EUSART5_RXFLValue:
(&SL_DMA_SIGNAL_EUSART5_RXFL_VALUE)
Define for EUSART5 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART5_TXFL#
#define SL_DMA_SIGNAL_EUSART5_TXFLValue:
(&SL_DMA_SIGNAL_EUSART5_TXFL_VALUE)
Define for EUSART5 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART6_RXFL#
#define SL_DMA_SIGNAL_EUSART6_RXFLValue:
(&SL_DMA_SIGNAL_EUSART6_RXFL_VALUE)
Define for EUSART6 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART6_TXFL#
#define SL_DMA_SIGNAL_EUSART6_TXFLValue:
(&SL_DMA_SIGNAL_EUSART6_TXFL_VALUE)
Define for EUSART6 TXFL DMA Signal.
SL_DMA_SIGNAL_EUSART7_RXFL#
#define SL_DMA_SIGNAL_EUSART7_RXFLValue:
(&SL_DMA_SIGNAL_EUSART7_RXFL_VALUE)
Define for EUSART7 RXFL DMA Signal.
SL_DMA_SIGNAL_EUSART7_TXFL#
#define SL_DMA_SIGNAL_EUSART7_TXFLValue:
(&SL_DMA_SIGNAL_EUSART7_TXFL_VALUE)
Define for EUSART7 TXFL DMA Signal.
SL_DMA_SIGNAL_USART0_RXDATAV#
#define SL_DMA_SIGNAL_USART0_RXDATAVValue:
(&SL_DMA_SIGNAL_USART0_RXDATAV_VALUE)
Define for USART0 RXDATAV DMA Signal.
SL_DMA_SIGNAL_USART0_RXDATAVRIGHT#
#define SL_DMA_SIGNAL_USART0_RXDATAVRIGHTValue:
(&SL_DMA_SIGNAL_USART0_RXDATAVRIGHT_VALUE)
Define for USART0 RXDATAVRIGHT DMA Signal.
SL_DMA_SIGNAL_USART0_TXBL#
#define SL_DMA_SIGNAL_USART0_TXBLValue:
(&SL_DMA_SIGNAL_USART0_TXBL_VALUE)
Define for USART0 TXBL DMA Signal.
SL_DMA_SIGNAL_USART0_TXBLRIGHT#
#define SL_DMA_SIGNAL_USART0_TXBLRIGHTValue:
(&SL_DMA_SIGNAL_USART0_TXBLRIGHT_VALUE)
Define for USART0 TXBLRIGHT DMA Signal.
SL_DMA_SIGNAL_USART0_TXEMPTY#
#define SL_DMA_SIGNAL_USART0_TXEMPTYValue:
(&SL_DMA_SIGNAL_USART0_TXEMPTY_VALUE)
Define for USART0 TXEMPTY DMA Signal.
SL_DMA_SIGNAL_USART1_RXDATAV#
#define SL_DMA_SIGNAL_USART1_RXDATAVValue:
(&SL_DMA_SIGNAL_USART1_RXDATAV_VALUE)
Define for USART1 RXDATAV DMA Signal.
SL_DMA_SIGNAL_USART1_RXDATAVRIGHT#
#define SL_DMA_SIGNAL_USART1_RXDATAVRIGHTValue:
(&SL_DMA_SIGNAL_USART1_RXDATAVRIGHT_VALUE)
Define for USART1 RXDATAVRIGHT DMA Signal.
SL_DMA_SIGNAL_USART1_TXBL#
#define SL_DMA_SIGNAL_USART1_TXBLValue:
(&SL_DMA_SIGNAL_USART1_TXBL_VALUE)
Define for USART1 TXBL DMA Signal.
SL_DMA_SIGNAL_USART1_TXBLRIGHT#
#define SL_DMA_SIGNAL_USART1_TXBLRIGHTValue:
(&SL_DMA_SIGNAL_USART1_TXBLRIGHT_VALUE)
Define for USART1 TXBLRIGHT DMA Signal.
SL_DMA_SIGNAL_USART1_TXEMPTY#
#define SL_DMA_SIGNAL_USART1_TXEMPTYValue:
(&SL_DMA_SIGNAL_USART1_TXEMPTY_VALUE)
Define for USART1 TXEMPTY DMA Signal.
SL_DMA_SIGNAL_USART2_RXDATAV#
#define SL_DMA_SIGNAL_USART2_RXDATAVValue:
(&SL_DMA_SIGNAL_USART2_RXDATAV_VALUE)
Define for USART2 RXDATAV DMA Signal.
SL_DMA_SIGNAL_USART2_RXDATAVRIGHT#
#define SL_DMA_SIGNAL_USART2_RXDATAVRIGHTValue:
(&SL_DMA_SIGNAL_USART2_RXDATAVRIGHT_VALUE)
Define for USART2 RXDATAVRIGHT DMA Signal.
SL_DMA_SIGNAL_USART2_TXBL#
#define SL_DMA_SIGNAL_USART2_TXBLValue:
(&SL_DMA_SIGNAL_USART2_TXBL_VALUE)
Define for USART2 TXBL DMA Signal.
SL_DMA_SIGNAL_USART2_TXBLRIGHT#
#define SL_DMA_SIGNAL_USART2_TXBLRIGHTValue:
(&SL_DMA_SIGNAL_USART2_TXBLRIGHT_VALUE)
Define for USART2 TXBLRIGHT DMA Signal.
SL_DMA_SIGNAL_USART2_TXEMPTY#
#define SL_DMA_SIGNAL_USART2_TXEMPTYValue:
(&SL_DMA_SIGNAL_USART2_TXEMPTY_VALUE)
Define for USART2 TXEMPTY DMA Signal.
SL_DMA_SIGNAL_EUART0_RXFL#
#define SL_DMA_SIGNAL_EUART0_RXFLValue:
(&SL_DMA_SIGNAL_EUART0_RXFL_VALUE)
Define for EUART0 RXFL DMA Signal.
SL_DMA_SIGNAL_EUART0_TXFL#
#define SL_DMA_SIGNAL_EUART0_TXFLValue:
(&SL_DMA_SIGNAL_EUART0_TXFL_VALUE)
Define for EUART0 TXFL DMA Signal.
SL_DMA_SIGNAL_MSC_WDATA#
#define SL_DMA_SIGNAL_MSC_WDATAValue:
(&SL_DMA_SIGNAL_MSC_WDATA_VALUE)
Define for MSC WDATA DMA Signal.
SL_DMA_SIGNAL_MVP_REQ#
#define SL_DMA_SIGNAL_MVP_REQValue:
(&SL_DMA_SIGNAL_MVP_REQ_VALUE)
Define for MVP REQ DMA Signal.
SL_DMA_SIGNAL_PIXELRZ0REQ_TXF#
#define SL_DMA_SIGNAL_PIXELRZ0REQ_TXFValue:
(&SL_DMA_SIGNAL_PIXELRZ0REQ_TXF_VALUE)
Define for PIXELRZ0REQ TXF DMA Signal.
SL_DMA_SIGNAL_PIXELRZ1REQ_TXF#
#define SL_DMA_SIGNAL_PIXELRZ1REQ_TXFValue:
(&SL_DMA_SIGNAL_PIXELRZ1REQ_TXF_VALUE)
Define for PIXELRZ1REQ TXF DMA Signal.
SL_DMA_SIGNAL_PDM_RXDATAV#
#define SL_DMA_SIGNAL_PDM_RXDATAVValue:
(&SL_DMA_SIGNAL_PDM_RXDATAV_VALUE)
Define for PDM RXDATAV DMA Signal.
SL_DMA_SIGNAL_PDM0_RXDATA#
#define SL_DMA_SIGNAL_PDM0_RXDATAValue:
(&SL_DMA_SIGNAL_PDM0_RXDATA_VALUE)
Define for PDM0 RXDATA DMA Signal.
SL_DMA_SIGNAL_LCD#
#define SL_DMA_SIGNAL_LCDValue:
(&SL_DMA_SIGNAL_LCD_VALUE)
Define for LCD DMA Signal.
SL_DMA_SIGNAL_LESENSE_FIFO#
#define SL_DMA_SIGNAL_LESENSE_FIFOValue:
(&SL_DMA_SIGNAL_LESENSE_FIFO_VALUE)
Define for LESENSE FIFO Signal.
SL_DMA_SIGNAL_VDAC0_CH0REQ#
#define SL_DMA_SIGNAL_VDAC0_CH0REQValue:
(&SL_DMA_SIGNAL_VDAC0_CH0REQ_VALUE)
Define for VDAC0 CH0 REQ Signal.
SL_DMA_SIGNAL_VDAC0_CH1REQ#
#define SL_DMA_SIGNAL_VDAC0_CH1REQValue:
(&SL_DMA_SIGNAL_VDAC0_CH1REQ_VALUE)
Define for VDAC0 CH1 REQ Signal.
SL_DMA_SIGNAL_VDAC1_CH0REQ#
#define SL_DMA_SIGNAL_VDAC1_CH0REQValue:
(&SL_DMA_SIGNAL_VDAC1_CH0REQ_VALUE)
Define for VDAC1 CH0 REQ Signal.
SL_DMA_SIGNAL_VDAC1_CH1REQ#
#define SL_DMA_SIGNAL_VDAC1_CH1REQValue:
(&SL_DMA_SIGNAL_VDAC1_CH1REQ_VALUE)
Define for VDAC1 CH1 REQ Signal.
SL_DMA_SIGNAL_CAN0_RXFL0#
#define SL_DMA_SIGNAL_CAN0_RXFL0Value:
(&SL_DMA_SIGNAL_CAN0_RXFL0_VALUE)
Define for CAN0 RXFL0 DMA Signal.
SL_DMA_SIGNAL_CAN0_RXFL1#
#define SL_DMA_SIGNAL_CAN0_RXFL1Value:
(&SL_DMA_SIGNAL_CAN0_RXFL1_VALUE)
Define for CAN0 RXFL1 DMA Signal.
SL_DMA_SIGNAL_CAN0_TXFL0#
#define SL_DMA_SIGNAL_CAN0_TXFL0Value:
(&SL_DMA_SIGNAL_CAN0_TXFL0_VALUE)
Define for CAN0 TXFL0 DMA Signal.
SL_DMA_SIGNAL_CAN0_TXFL1#
#define SL_DMA_SIGNAL_CAN0_TXFL1Value:
(&SL_DMA_SIGNAL_CAN0_TXFL1_VALUE)
Define for CAN0 TXFL1 DMA Signal.
SL_DMA_SIGNAL_CAN1_RXFL0#
#define SL_DMA_SIGNAL_CAN1_RXFL0Value:
(&SL_DMA_SIGNAL_CAN1_RXFL0_VALUE)
Define for CAN1 RXFL0 DMA Signal.
SL_DMA_SIGNAL_CAN1_RXFL1#
#define SL_DMA_SIGNAL_CAN1_RXFL1Value:
(&SL_DMA_SIGNAL_CAN1_RXFL1_VALUE)
Define for CAN1 RXFL1 DMA Signal.
SL_DMA_SIGNAL_CAN1_TXFL0#
#define SL_DMA_SIGNAL_CAN1_TXFL0Value:
(&SL_DMA_SIGNAL_CAN1_TXFL0_VALUE)
Define for CAN1 TXFL0 DMA Signal.
SL_DMA_SIGNAL_CAN1_TXFL1#
#define SL_DMA_SIGNAL_CAN1_TXFL1Value:
(&SL_DMA_SIGNAL_CAN1_TXFL1_VALUE)
Define for CAN1 TXFL1 DMA Signal.
Enumeration Documentation#
sl_dma_ctrl_size_t#
sl_dma_ctrl_size_t
DMA transfer unit size (portable semantic values)
| Enumerator | |
|---|---|
| SL_DMA_CTRL_SIZE_BYTE | Unit transfer size is 1 byte. |
| SL_DMA_CTRL_SIZE_HALF | Unit transfer size is 2 bytes (half-word). |
| SL_DMA_CTRL_SIZE_WORD | Unit transfer size is 4 bytes (word). |
sl_dma_ctrl_block_size_t#
sl_dma_ctrl_block_size_t
Number of unit transfers granted per arbitration opportunity.
Values are semantic ordering indices; NOT literal hardware encodings.
| Enumerator | |
|---|---|
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_1 | One unit transfer per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_2 | Two unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_3 | Three unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_4 | Four unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_6 | Six unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_8 | Eight unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_16 | 16 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_32 | 32 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_64 | 64 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_128 | 128 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_256 | 256 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_512 | 512 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_UNIT_1024 | 1024 unit transfers per arbitration. |
| SL_DMA_CTRL_BLOCK_SIZE_ALL | Entire remaining transfer (locks arbitration) if supported. |
Typedef Documentation#
Macro Definition Documentation#
SL_DMA_CTRL_SIZE_IS_VALID#
#define SL_DMA_CTRL_SIZE_IS_VALIDValue:
(v)
Validate transfer unit size value.
SL_DMA_CTRL_BLOCK_SIZE_IS_VALID#
#define SL_DMA_CTRL_BLOCK_SIZE_IS_VALIDValue:
(v)
Validate block size enum value.
SL_DMA_PERIPHERAL_SIGNAL_IS_VALID#
#define SL_DMA_PERIPHERAL_SIGNAL_IS_VALIDValue:
(v)
Validate peripheral signal selection (excluding COUNT sentinel).