SYSTEM CONFIGURATION#

sl_hal_syscfg_read_chip_rev#

uint32_t sl_hal_syscfg_read_chip_rev (void )

Reads CHIPREV register.

Returns

• The current value of the CHIPREV register, containing chip revision information.

sl_hal_syscfg_set_systicextclken_cfgsystic#

void sl_hal_syscfg_set_systicextclken_cfgsystic (void )

Enables the external clock for the SysTick timer.

sl_hal_syscfg_clear_systicextclken_cfgsystic#

void sl_hal_syscfg_clear_systicextclken_cfgsystic (void )

Disables the external clock source for the SysTick timer.

sl_hal_syscfg_ecc_set_config#

void sl_hal_syscfg_ecc_set_config (const sl_hal_syscfg_ecc_config_t * ecc_config)

Configure Error Correcting Code (ECC).

This function configures ECC support according to the configuration input parameter. If the user requests enabling ECC for a given RAM bank this function will initialize ECC memory (syndromes) for the bank by reading and writing the existing values in memory. I.e. all data is preserved. The initialization process runs in a critical section disallowing interrupts and thread scheduling, and will consume a considerable amount of clock cycles. Therefore the user should carefully assess where to call this function. The user can consider to increase the clock frequency in order to reduce the execution time. This function makes use of 2 DMA channels to move data to/from RAM in an efficient way. The user can select which 2 DMA channels to use in order to avoid conflicts with the application. However the user must make sure that no other DMA operations takes place while this function is executing. If the application has been using the DMA controller prior to calling this function, the application will need to reinitialize DMA registers after this function has completed.

Note

• This function protects the ECC initialization procedure from interrupts and other threads by using a critical section (defined by sl_core.h) When running on RTOS the user may need to override CORE_EnterCritical CORE_ExitCritical.

sl_hal_syscfg_set_dmem0ramctrl_ramwsen_bit#

void sl_hal_syscfg_set_dmem0ramctrl_ramwsen_bit (void )

Enables the RAM wait state feature for DMEM0.

This function sets the RAMWSEN bit in the DMEM0RAMCTRL register to 1, enabling the RAM wait state feature for DMEM0. This feature is used to configure the memory access timing for DMEM0.

sl_hal_syscfg_clear_dmem0ramctrl_ramwsen_bit#

void sl_hal_syscfg_clear_dmem0ramctrl_ramwsen_bit (void )

Disables the RAM wait state feature for DMEM0.

This function clears the RAMWSEN bit in the DMEM0RAMCTRL register to 0,disabling the RAM wait state feature for DMEM0. This ensures that memory access timing for DMEM0 operates without additional wait states.

sl_hal_syscfg_get_dmem0ramctrl_ramwsen_bit#

uint32_t sl_hal_syscfg_get_dmem0ramctrl_ramwsen_bit (void )

Reads the RAMWSEN bit from the DMEM0RAMCTRL register.

Returns

• The value of the RAMWSEN bit (1 if enabled, 0 if disabled).

This function retrieves the value of the RAMWSEN bit in the DMEM0RAMCTRL register. The RAMWSEN bit indicates whether the RAM wait state feature for DMEM0 is enabled (1) or disabled (0).

sl_hal_syscfg_read_dmem0retnctrl#

uint32_t sl_hal_syscfg_read_dmem0retnctrl (void )

Reads the DMEM0RETNCTRL register.

Returns

• The current value of the DMEM0RETNCTRL register.

This function retrieves the current value of the DMEM0RETNCTRL register, which is used to control the retention settings for DMEM0 memory blocks.

sl_hal_syscfg_mask_dmem0retnctrl#

void sl_hal_syscfg_mask_dmem0retnctrl (uint32_t mask)

Applies a mask to the DMEM0RETNCTRL register.

This function performs a bitwise OR operation between the current value of the DMEM0RETNCTRL register and the provided mask, setting specific bits in the register.

sl_hal_syscfg_zero_dmem0retnctrl#

void sl_hal_syscfg_zero_dmem0retnctrl (void )

Sets the DMEM0RETNCTRL register to zero.

This function clears all bits in the DMEM0RETNCTRL register by setting its value to 0. This effectively disables all retention settings for DMEM0 memory blocks.