Peripheral DeclarationsDevices > EFM32TG11B520F128GM80

Macros

#define ACMP0   ((ACMP_TypeDef *) ACMP0_BASE)
 
#define ACMP1   ((ACMP_TypeDef *) ACMP1_BASE)
 
#define ADC0   ((ADC_TypeDef *) ADC0_BASE)
 
#define CAN0   ((CAN_TypeDef *) CAN0_BASE)
 
#define CMU   ((CMU_TypeDef *) CMU_BASE)
 
#define CRYOTIMER   ((CRYOTIMER_TypeDef *) CRYOTIMER_BASE)
 
#define CRYPTO0   ((CRYPTO_TypeDef *) CRYPTO0_BASE)
 
#define CSEN   ((CSEN_TypeDef *) CSEN_BASE)
 
#define DEVINFO   ((DEVINFO_TypeDef *) DEVINFO_BASE)
 
#define EMU   ((EMU_TypeDef *) EMU_BASE)
 
#define GPCRC   ((GPCRC_TypeDef *) GPCRC_BASE)
 
#define GPIO   ((GPIO_TypeDef *) GPIO_BASE)
 
#define I2C0   ((I2C_TypeDef *) I2C0_BASE)
 
#define I2C1   ((I2C_TypeDef *) I2C1_BASE)
 
#define LCD   ((LCD_TypeDef *) LCD_BASE)
 
#define LDMA   ((LDMA_TypeDef *) LDMA_BASE)
 
#define LESENSE   ((LESENSE_TypeDef *) LESENSE_BASE)
 
#define LETIMER0   ((LETIMER_TypeDef *) LETIMER0_BASE)
 
#define LEUART0   ((LEUART_TypeDef *) LEUART0_BASE)
 
#define MSC   ((MSC_TypeDef *) MSC_BASE)
 
#define MTB   ((MTB_TypeDef *) MTB_BASE)
 
#define PCNT0   ((PCNT_TypeDef *) PCNT0_BASE)
 
#define PRS   ((PRS_TypeDef *) PRS_BASE)
 
#define RMU   ((RMU_TypeDef *) RMU_BASE)
 
#define ROMTABLE   ((ROMTABLE_TypeDef *) ROMTABLE_BASE)
 
#define RTCC   ((RTCC_TypeDef *) RTCC_BASE)
 
#define SMU   ((SMU_TypeDef *) SMU_BASE)
 
#define TIMER0   ((TIMER_TypeDef *) TIMER0_BASE)
 
#define TIMER1   ((TIMER_TypeDef *) TIMER1_BASE)
 
#define TRNG0   ((TRNG_TypeDef *) TRNG0_BASE)
 
#define UART0   ((USART_TypeDef *) UART0_BASE)
 
#define USART0   ((USART_TypeDef *) USART0_BASE)
 
#define USART1   ((USART_TypeDef *) USART1_BASE)
 
#define USART2   ((USART_TypeDef *) USART2_BASE)
 
#define USART3   ((USART_TypeDef *) USART3_BASE)
 
#define VDAC0   ((VDAC_TypeDef *) VDAC0_BASE)
 
#define WDOG0   ((WDOG_TypeDef *) WDOG0_BASE)
 
#define WTIMER0   ((TIMER_TypeDef *) WTIMER0_BASE)
 
#define WTIMER1   ((TIMER_TypeDef *) WTIMER1_BASE)
 

Macro Definition Documentation

#define ACMP0   ((ACMP_TypeDef *) ACMP0_BASE)

ACMP0 base pointer

Definition at line 425 of file efm32tg11b520f128gm80.h.

Referenced by CAPLESENSE_setupACMP().

#define ACMP1   ((ACMP_TypeDef *) ACMP1_BASE)

ACMP1 base pointer

Definition at line 426 of file efm32tg11b520f128gm80.h.

Referenced by CAPLESENSE_setupACMP().

#define ADC0   ((ADC_TypeDef *) ADC0_BASE)

ADC0 base pointer

Definition at line 424 of file efm32tg11b520f128gm80.h.

Referenced by ADC0_IRQHandler(), ADC_Init(), adcInit(), getAdcSample(), MIC_init(), MIC_start(), TOUCH_GetPos(), and TOUCH_Init().

#define CAN0   ((CAN_TypeDef *) CAN0_BASE)

CAN0 base pointer

Definition at line 408 of file efm32tg11b520f128gm80.h.

Referenced by CAN_GetClockFrequency().

#define CRYPTO0   ((CRYPTO_TypeDef *) CRYPTO0_BASE)

CRYPTO0 base pointer

Definition at line 402 of file efm32tg11b520f128gm80.h.

#define CSEN   ((CSEN_TypeDef *) CSEN_BASE)

CSEN base pointer

Definition at line 428 of file efm32tg11b520f128gm80.h.

#define GPCRC   ((GPCRC_TypeDef *) GPCRC_BASE)

GPCRC base pointer

Definition at line 407 of file efm32tg11b520f128gm80.h.

#define I2C0   ((I2C_TypeDef *) I2C0_BASE)

I2C0 base pointer

Definition at line 422 of file efm32tg11b520f128gm80.h.

Referenced by I2C_BusFreqGet(), I2C_BusFreqSet(), I2C_Transfer(), I2C_TransferInit(), I2CSPM_Init(), and sl_efpdrv_init().

#define I2C1   ((I2C_TypeDef *) I2C1_BASE)

I2C1 base pointer

Definition at line 423 of file efm32tg11b520f128gm80.h.

Referenced by BOARD_i2cBusSelect(), BOARD_init(), I2C_BusFreqGet(), I2C_BusFreqSet(), I2C_Transfer(), I2C_TransferInit(), I2CSPM_Init(), and sl_efpdrv_init().

#define LETIMER0   ((LETIMER_TypeDef *) LETIMER0_BASE)

LETIMER0 base pointer

Definition at line 419 of file efm32tg11b520f128gm80.h.

#define LEUART0   ((LEUART_TypeDef *) LEUART0_BASE)

LEUART0 base pointer

Definition at line 418 of file efm32tg11b520f128gm80.h.

Referenced by LEUART_BaudrateGet(), LEUART_BaudrateSet(), and UARTDRV_InitLeuart().

#define MTB   ((MTB_TypeDef *) MTB_BASE)

MTB base pointer

Definition at line 434 of file efm32tg11b520f128gm80.h.

#define PCNT0   ((PCNT_TypeDef *) PCNT0_BASE)

PCNT0 base pointer

Definition at line 421 of file efm32tg11b520f128gm80.h.

Referenced by PCNT_CounterTopSet(), PCNT_Init(), and PCNT_TopSet().

#define RMU   ((RMU_TypeDef *) RMU_BASE)

RMU base pointer

Definition at line 400 of file efm32tg11b520f128gm80.h.

Referenced by BSP_initDevice(), RMU_ResetCauseClear(), RMU_ResetCauseGet(), RMU_ResetControl(), RMU_UserResetStateGet(), and RMU_UserResetStateSet().

#define ROMTABLE   ((ROMTABLE_TypeDef *) ROMTABLE_BASE)

ROMTABLE base pointer

Definition at line 436 of file efm32tg11b520f128gm80.h.

Referenced by SYSTEM_ChipRevisionGet().

#define SMU   ((SMU_TypeDef *) SMU_BASE)

SMU base pointer

Definition at line 432 of file efm32tg11b520f128gm80.h.

Referenced by SMU_EnablePPU(), SMU_GetFaultingPeripheral(), SMU_Init(), SMU_IntClear(), SMU_IntDisable(), SMU_IntEnable(), SMU_IntGet(), SMU_IntGetEnabled(), SMU_IntSet(), and SMU_SetPrivilegedAccess().

#define TIMER0   ((TIMER_TypeDef *) TIMER0_BASE)

TIMER0 base pointer

Definition at line 409 of file efm32tg11b520f128gm80.h.

Referenced by CAPSENSE_Init(), CAPSENSE_Measure(), TIMER0_IRQHandler(), TIMER_ClearDTIFault(), TIMER_EnableDTI(), TIMER_GetDTIFault(), TIMER_InitDTI(), TIMER_Lock(), TIMER_Unlock(), and TIMER_Valid().

#define TIMER1   ((TIMER_TypeDef *) TIMER1_BASE)

TIMER1 base pointer

Definition at line 410 of file efm32tg11b520f128gm80.h.

Referenced by CAPSENSE_Init(), CAPSENSE_Measure(), TIMER0_IRQHandler(), and TIMER_Valid().

#define TRNG0   ((TRNG_TypeDef *) TRNG0_BASE)

TRNG0 base pointer

Definition at line 433 of file efm32tg11b520f128gm80.h.

#define UART0   ((USART_TypeDef *) UART0_BASE)

UART0 base pointer

Definition at line 417 of file efm32tg11b520f128gm80.h.

Referenced by UARTDRV_InitUart().

#define USART0   ((USART_TypeDef *) USART0_BASE)

USART0 base pointer

Definition at line 413 of file efm32tg11b520f128gm80.h.

Referenced by prsIrInput(), prsRxInput(), prsTriggerInput(), SPIDRV_Init(), UARTDRV_InitUart(), and USART_InitIrDA().

#define USART1   ((USART_TypeDef *) USART1_BASE)

USART1 base pointer

Definition at line 414 of file efm32tg11b520f128gm80.h.

Referenced by prsIrInput(), prsRxInput(), prsTriggerInput(), SPI_TFT_Init(), SPI_TFT_WriteRegister(), SPIDRV_Init(), UARTDRV_InitUart(), and USART_InitIrDA().

#define USART2   ((USART_TypeDef *) USART2_BASE)

USART2 base pointer

Definition at line 415 of file efm32tg11b520f128gm80.h.

Referenced by prsIrInput(), prsRxInput(), prsTriggerInput(), SPIDRV_Init(), UARTDRV_InitUart(), USART_BaudrateAsyncSet(), USART_BaudrateGet(), and USART_BaudrateSyncSet().

#define USART3   ((USART_TypeDef *) USART3_BASE)

USART3 base pointer

Definition at line 416 of file efm32tg11b520f128gm80.h.

Referenced by SPIDRV_Init(), and UARTDRV_InitUart().

#define VDAC0   ((VDAC_TypeDef *) VDAC0_BASE)

VDAC0 base pointer

Definition at line 427 of file efm32tg11b520f128gm80.h.

#define WDOG0   ((WDOG_TypeDef *) WDOG0_BASE)

WDOG0 base pointer

Definition at line 431 of file efm32tg11b520f128gm80.h.

#define WTIMER0   ((TIMER_TypeDef *) WTIMER0_BASE)

WTIMER0 base pointer

Definition at line 411 of file efm32tg11b520f128gm80.h.

Referenced by TIMER_MaxCount(), and TIMER_Valid().

#define WTIMER1   ((TIMER_TypeDef *) WTIMER1_BASE)

WTIMER1 base pointer

Definition at line 412 of file efm32tg11b520f128gm80.h.

Referenced by TIMER_MaxCount(), and TIMER_Valid().