CMU_TypeDef Struct ReferenceDevices > EFM32WG_CMU

Definition at line 48 of file efm32wg_cmu.h.

Data Fields

__IOM uint32_t AUXHFRCOCTRL
 
__IOM uint32_t CALCNT
 
__IOM uint32_t CALCTRL
 
__IOM uint32_t CMD
 
__IOM uint32_t CTRL
 
__IOM uint32_t FREEZE
 
__IOM uint32_t HFCORECLKDIV
 
__IOM uint32_t HFCORECLKEN0
 
__IOM uint32_t HFPERCLKDIV
 
__IOM uint32_t HFPERCLKEN0
 
__IOM uint32_t HFRCOCTRL
 
__IOM uint32_t IEN
 
__IM uint32_t IF
 
__IOM uint32_t IFC
 
__IOM uint32_t IFS
 
__IOM uint32_t LCDCTRL
 
__IOM uint32_t LFACLKEN0
 
__IOM uint32_t LFAPRESC0
 
__IOM uint32_t LFBCLKEN0
 
__IOM uint32_t LFBPRESC0
 
__IOM uint32_t LFCLKSEL
 
__IOM uint32_t LFRCOCTRL
 
__IOM uint32_t LOCK
 
__IOM uint32_t OSCENCMD
 
__IOM uint32_t PCNTCTRL
 
uint32_t RESERVED0 [2U]
 
uint32_t RESERVED1 [1U]
 
uint32_t RESERVED2 [1U]
 
uint32_t RESERVED3 [1U]
 
uint32_t RESERVED4 [1U]
 
__IOM uint32_t ROUTE
 
__IM uint32_t STATUS
 
__IM uint32_t SYNCBUSY
 

Field Documentation

__IOM uint32_t CMU_TypeDef::AUXHFRCOCTRL

AUXHFRCO Control Register

Definition at line 54 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::CALCNT

Calibration Counter Register

Definition at line 56 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::CALCTRL

Calibration Control Register

Definition at line 55 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::CMD

Command Register

Definition at line 58 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::CTRL

CMU Control Register

Definition at line 49 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::FREEZE

Freeze Register

Definition at line 69 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::HFCORECLKDIV

High Frequency Core Clock Division Register

Definition at line 50 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::HFCORECLKEN0

High Frequency Core Clock Enable Register 0

Definition at line 65 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::HFPERCLKDIV

High Frequency Peripheral Clock Division Register

Definition at line 51 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::HFPERCLKEN0

High Frequency Peripheral Clock Enable Register 0

Definition at line 66 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::HFRCOCTRL

HFRCO Control Register

Definition at line 52 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::IEN

Interrupt Enable Register

Definition at line 64 of file efm32wg_cmu.h.

__IM uint32_t CMU_TypeDef::IF

Interrupt Flag Register

Definition at line 61 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::IFC

Interrupt Flag Clear Register

Definition at line 63 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::IFS

Interrupt Flag Set Register

Definition at line 62 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LCDCTRL

LCD Control Register

Definition at line 80 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFACLKEN0

Low Frequency A Clock Enable Register 0 (Async Reg)

Definition at line 70 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFAPRESC0

Low Frequency A Prescaler Register 0 (Async Reg)

Definition at line 75 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFBCLKEN0

Low Frequency B Clock Enable Register 0 (Async Reg)

Definition at line 72 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFBPRESC0

Low Frequency B Prescaler Register 0 (Async Reg)

Definition at line 77 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFCLKSEL

Low Frequency Clock Select Register

Definition at line 59 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LFRCOCTRL

LFRCO Control Register

Definition at line 53 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::LOCK

Configuration Lock Register

Definition at line 82 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::OSCENCMD

Oscillator Enable/Disable Command Register

Definition at line 57 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::PCNTCTRL

PCNT Control Register

Definition at line 79 of file efm32wg_cmu.h.

uint32_t CMU_TypeDef::RESERVED0[2U]

Reserved for future use

Definition at line 67 of file efm32wg_cmu.h.

uint32_t CMU_TypeDef::RESERVED1[1U]

Reserved for future use

Definition at line 71 of file efm32wg_cmu.h.

uint32_t CMU_TypeDef::RESERVED2[1U]

Reserved for future use

Definition at line 74 of file efm32wg_cmu.h.

uint32_t CMU_TypeDef::RESERVED3[1U]

Reserved for future use

Definition at line 76 of file efm32wg_cmu.h.

uint32_t CMU_TypeDef::RESERVED4[1U]

Reserved for future use

Definition at line 78 of file efm32wg_cmu.h.

__IOM uint32_t CMU_TypeDef::ROUTE

I/O Routing Register

Definition at line 81 of file efm32wg_cmu.h.

__IM uint32_t CMU_TypeDef::STATUS

Status Register

Definition at line 60 of file efm32wg_cmu.h.

__IM uint32_t CMU_TypeDef::SYNCBUSY

Synchronization Busy Register

Definition at line 68 of file efm32wg_cmu.h.


The documentation for this struct was generated from the following file:
  • C:/repos/embsw_super_h1/platform/Device/SiliconLabs/EFM32WG/Include/efm32wg_cmu.h