This file contains the type definitions for efr32xg2x chip-specific aspects of RAIL.
License#
Copyright 2020 Silicon Laboratories Inc. www.silabs.com
SPDX-License-Identifier: Zlib
The licensor of this software is Silicon Laboratories Inc.
This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software.
Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:
The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required.
Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.
This notice may not be removed or altered from any source distribution.
Modules#
Macros#
SLI_LIBRARY_BUILD.
The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.
This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.
Time it takes to take care of protocol switching.
Indicates the number of 2.4 GHz RF Paths suppported.
Indicates the number of sub-GHz RF Paths supported.
Indicates the number of RF Paths supported.
Indicates this version of RAIL supports IR calibration on multiple RF paths Needed for backwards compatibility.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_HP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_HP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_MP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_MP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when using a SUBGHZ PA mode.
The minimum valid value for the RAIL_TxPowerLevel_t when using a SUBGHZ PA mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_HP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_HP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_MP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_MP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LP mode.
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
Backwards compatability define.
The number of PA's on this chip.
The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.
Default PRS channel to use when configuring sleep.
Default RTCC channel to use when configuring sleep.
The minimum value for a consistent RAIL transition.
The maximum value for a consistent RAIL transition.
Macro Definition Documentation#
__RAIL_CHIP_SPECIFIC_H_#
#define __RAIL_CHIP_SPECIFIC_H_
SLI_LIBRARY_BUILD.
Include guard
44 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_ENUM#
#define RAIL_ENUMValue:
(name)
The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.
Instead, uint8_t typedefs are used in compiled code for all enumerations. For documentation purposes, this is converted to an actual enumeration since it's much easier to read in Doxygen.
58 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_ENUM_GENERIC#
#define RAIL_ENUM_GENERICValue:
(name, type)
This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.
See RAIL_ENUM() for more information.
62 of file chip/efr32/efr32xg2x/rail_chip_specific.hTRANSITION_TIME_US#
#define TRANSITION_TIME_USValue:
500
Time it takes to take care of protocol switching.
514 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_RF_PATHS_2P4GIG#
#define RAIL_RF_PATHS_2P4GIGValue:
0
Indicates the number of 2.4 GHz RF Paths suppported.
541 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_RF_PATHS_SUBGIG#
#define RAIL_RF_PATHS_SUBGIGValue:
0
Indicates the number of sub-GHz RF Paths supported.
557 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_RF_PATHS#
#define RAIL_RF_PATHSValue:
(RAIL_RF_PATHS_SUBGIG + RAIL_RF_PATHS_2P4GIG)
Indicates the number of RF Paths supported.
565 of file chip/efr32/efr32xg2x/rail_chip_specific.hRADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHS#
#define RADIO_CONFIG_ENABLE_IRCAL_MULTIPLE_RF_PATHSValue:
0
Indicates this version of RAIL supports IR calibration on multiple RF paths Needed for backwards compatibility.
580 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_HP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_HP_MAXValue:
(240)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_HP mode.
709 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_HP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_HP_MINValue:
(1U)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_HP mode.
714 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_MP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_MP_MAXValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_MP mode.
719 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_MP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_MP_MINValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_MP mode.
724 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_LP_MAXValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LP mode.
729 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_LP_MINValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LP mode.
734 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LLP_MAX#
#define RAIL_TX_POWER_LEVEL_2P4_LLP_MAXValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
739 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_2P4_LLP_MIN#
#define RAIL_TX_POWER_LEVEL_2P4_LLP_MINValue:
(RAIL_TX_POWER_LEVEL_2P4_HP_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4GIG_LLP mode.
744 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_SUBGIG_MAX#
#define RAIL_SUBGIG_MAXValue:
0U
The maximum valid value for the RAIL_TxPowerLevel_t when using a SUBGHZ PA mode.
759 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_SUBGIG_MIN#
#define RAIL_SUBGIG_MINValue:
1U
The minimum valid value for the RAIL_TxPowerLevel_t when using a SUBGHZ PA mode.
767 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAXValue:
(RAIL_SUBGIG_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_HP mode.
773 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MINValue:
(RAIL_SUBGIG_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_HP mode.
778 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MP_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MAXValue:
(RAIL_SUBGIG_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_MP mode.
783 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MP_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MP_MINValue:
(RAIL_SUBGIG_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_MP mode.
788 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_LP_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MAXValue:
(RAIL_SUBGIG_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LP mode.
793 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_LP_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_LP_MINValue:
(RAIL_SUBGIG_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LP mode.
798 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MAXValue:
(RAIL_SUBGIG_MAX)
The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
803 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_LLP_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_LLP_MINValue:
(RAIL_SUBGIG_MIN)
The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG_LLP mode.
808 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_HP_MAX#
#define RAIL_TX_POWER_LEVEL_HP_MAXValue:
RAIL_TX_POWER_LEVEL_2P4_HP_MAX
Backwards compatability define.
830 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_HP_MIN#
#define RAIL_TX_POWER_LEVEL_HP_MINValue:
RAIL_TX_POWER_LEVEL_2P4_HP_MIN
Backwards compatability define.
832 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_MP_MAX#
#define RAIL_TX_POWER_LEVEL_MP_MAXValue:
RAIL_TX_POWER_LEVEL_2P4_MP_MAX
Backwards compatability define.
834 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_MP_MIN#
#define RAIL_TX_POWER_LEVEL_MP_MINValue:
RAIL_TX_POWER_LEVEL_2P4_MP_MIN
Backwards compatability define.
836 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_LP_MAX#
#define RAIL_TX_POWER_LEVEL_LP_MAXValue:
RAIL_TX_POWER_LEVEL_2P4_LP_MAX
Backwards compatability define.
838 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_LP_MIN#
#define RAIL_TX_POWER_LEVEL_LP_MINValue:
RAIL_TX_POWER_LEVEL_2P4_LP_MIN
Backwards compatability define.
840 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MAX#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MAXValue:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
Backwards compatability define.
842 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TX_POWER_LEVEL_SUBGIG_MIN#
#define RAIL_TX_POWER_LEVEL_SUBGIG_MINValue:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
Backwards compatability define.
844 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_NUM_PA#
#define RAIL_NUM_PAValue:
(3U)
The number of PA's on this chip.
(Including Virtual PAs)
862 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL#
#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNELValue:
(56U)
The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.
929 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT#
#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULTValue:
(7U)
Default PRS channel to use when configuring sleep.
950 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT#
#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULTValue:
(0U)
Default RTCC channel to use when configuring sleep.
957 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_MINIMUM_TRANSITION_US#
#define RAIL_MINIMUM_TRANSITION_USValue:
(100U)
The minimum value for a consistent RAIL transition.
Note
Transitions may need to be slower than this when using longer RAIL_TxPowerConfig_t::rampTime values
977 of file chip/efr32/efr32xg2x/rail_chip_specific.hRAIL_MAXIMUM_TRANSITION_US#
#define RAIL_MAXIMUM_TRANSITION_USValue:
(1000000U)
The maximum value for a consistent RAIL transition.
983 of file chip/efr32/efr32xg2x/rail_chip_specific.h