WiSeConnect 3 - SiWx91x Platform SDK Version 3.5.0 (June 18 2025) - Release Notes#

Wi-Fi 6 + BLE (WiSeConnect 3) SDK Version 3.5.0

Simplicity SDK Version 2025.6.0

The SiWx91x Platform software development kit (SDK) provides platform features on Silicon Labs SiWx91x microcontrollers, including peripherals, drivers, and services.

Click here for earlier releases.

Release Summary#

Key Features | API Changes | Bug Fixes | Chip Enablement

Key Features#

Driver support for BOD, GPDMA, HSPI Secondary, and OPAMP peripherals
Additional driver features for existing peripherals
Sleep stability improvements

API Changes#

APIs for newly introduced peripherals
Low-power GPIO interrupt API changes with deprecation

Bug Fixes#

Stability and functional fixes for DMA, QEI, SSI, and RHT sensors
Configuration fixes for PSRAM, ULP I2S, and PWM

Chip Enablement#

None

Key Features#

New Features | Enhancements | Removed Features | Deprecated Features

Note: See Feature Matrix for a list of any appliable APIs, examples, software variants, modes, hardware, and host interfaces applicable for each feature.

New Features#

Added support for LittleFS on common flash devices.
Added support for GCC link-time optimization (LTO).
Implemented driver support for new peripherals:
- Brown-Out Detection (BOD)
- General Purpose Direct Memory Access (GPDMA)
- High-speed Peripheral Interface (HSPI) Secondary
- Operational Amplifier (OPAMP)
Added support for an alternative way to reset the SiWx91x device after an application processor firmware update in ISP mode.

Enhancements#

Enhanced driver support for existing peripherals:
- Inter-IC Sound (I2S) Pulse Code Modulation (PCM)
- Universal Asynchronous Receiver/Transmitter (UART) RS485
Added Pin Tool support for SoC ULP peripherals on SoC high-power (HP) GPIO pins and vice versa.
Added an initial check in the connectivity (network processor) firmware for the anti-rollback feature before initiating the firmware download.
Enhanced peripheral drivers for configuring the ULP peripheral on SoC high-power (HP) GPIO pins and vice versa.
Adding support for overriding the default Calendar callback handler with a custom implementation.
Introduced new APIs in GPIO driver to ensure consistency in the configuration of UULP GPIO pins.
Added I/O Stream support for multiple stream types, including RTT, SWO, Debug, and VUART.
Enhanced the ULP UART peripheral with support for hardware flow control and 9-bit data mode.
Added a new PM PS2 Component to the Power Manager, enabling execution of required files from RAM and providing PS2 power state-specific features and dependencies.
Implemented the 32 KHz RC calibration framework for both the Calendar and deep sleep timer peripherals.
Improvements made in the stability of the sleep/wake-up sequence, by fixing a lock-up issue on cold boot.

Removed Features#


Removed Feature	Was Deprecated?
Capacitive Touch Sensor (CTS)	No
32-bit mode in Config Timer	No
Support in I2S peripheral for 12-bit and 20-bit resolutions	No

Deprecated Features#

Mote: The Watchdog Manager service replaces the Watchdog Timer peripheral mentioned below. See Impact Statements.


Deprecated Feature	Planned Removal Date
Watchdog Timer peripheral	2026-12

API Changes#

New APIs | Modified APIs | Removed APIs | Deprecated APIs

New APIs#


New API Signature	Deprecated API replaced by this (if any)
`sl_status_t` sl_si91x_gpio_driver_mask_set_uulp_npss_interrupt`(uint8_t npssgpio_interrupt)`	sl_si91x_gpio_driver_mask_uulp_npss_interrupt
`sl_status_t` sl_si91x_gpio_driver_mask_clear_uulp_npss_interrupt`(uint8_t npssgpio_interrupt)`	sl_si91x_gpio_driver_unmask_uulp_npss_interrupt
`sl_status_t` sl_si91x_gpio_driver_clear_uulp_npss_interrupt`(uint8_t npssgpio_interrupt)`	sl_si91x_gpio_driver_clear_uulp_interrupt
`void` sl_si91x_bod_unregister_callback`(void)`	None
`sl_status_t` sl_si91x_bod_get_battery_status`(float *battery_status)`	None
`sl_status_t` sl_si91x_bod_set_threshold`(float threshold)`	None
`void` sl_si91x_bod_enable_interrupt`(void)`	None
`void` sl_si91x_bod_disable_interrupt`(void)`	None
`void` sl_si91x_bod_clear_interrupt`(void)`	None
`sl_status_t` sl_si91x_bod_battery_percentage`(float voltage, float *vbat_per)`	None
`void` sl_si91x_bod_black_out_reset`(en_t enable)`	None
`void` sl_si91x_bod_button_interrupt_clear`(void)`	None
`void` sl_si91x_bod_enable_blackout_in_sleep_mode`(void)`	None
`void` sl_si91x_bod_disable_blackout_in_sleep_mode`(void)`	None
`sl_status_t` sl_si91x_uart_rs485_init`(usart_peripheral_t uart_instance)`	None
`sl_status_t` sl_si91x_uart_rs485_set_configuration`(usart_peripheral_t uart_instance)`	None
`void` sl_si91x_get_uart_rs485_configure`(usart_rs485_config_t *uart_rs485_configs)`	None
`sl_status_t` sl_si91x_uart_rs485_de_enable`(usart_peripheral_t uart_instance, bool enable)`	None
`sl_status_t` sl_si91x_uart_rs485_re_enable`(usart_peripheral_t uart_instance, bool enable)`	None
`sl_status_t` sl_si91x_uart_rs485_transfer_hardware_address`(usart_peripheral_t uart_instance, uint8_t *tx_address)`	None
`sl_status_t` sl_si91x_uart_rs485_address_received`(usart_peripheral_t uart_instance)`	None
`sl_status_t` sl_si91x_uart_rs485_rx_hardware_address_set`(usart_peripheral_t uart_instance, uint8_t *rx_addr)`	None
`sl_status_t` sl_si91x_uart_rs485_resume_tx`(usart_peripheral_t uart_instance, bool enable)`	None
`sl_status_t` sl_si91x_uart_rs485_control_send_address`(usart_peripheral_t uart_instance, bool send_addr_ctrl)`	None
`sl_status_t` sl_si91x_uart_rs485_control_address_match`(usart_peripheral_t uart_instance, bool addr_match_ctrl)`	None
`void` sl_si91x_ssi_per_instance_unregister_event_callback`(sl_ssi_handle_t ssi_handle)`	None
`sl_status_t` sl_si91x_opamp_init`(void)`	None
`void` sl_si91x_opamp_deinit`(void)`	None
`sl_status_t` sl_si91x_opamp_pin_init`(sl_opamp_pin_config_t *opamp_config_ptr)`	None
`sl_status_t` sl_si91x_opamp_set_configuration`(sl_opamp_config_t *opamp_config)`	None
`sl_status_t` sl_si91x_gpdma_init`(void)`	None
`sl_status_t` sl_si91x_gpdma_allocate_channel`(uint32_t *channel_no, uint32_t priority, uint32_t max_transfer_size)`	None
`sl_status_t` sl_si91x_gpdma_deallocate_channel`(uint32_t channel_no)`	None
`sl_status_t` sl_si91x_gpdma_register_callbacks`(uint32_t channel_no, sl_gpdma_callback_pointer_t *callback_t)`	None
`sl_status_t` sl_si91x_gpdma_unregister_callbacks`(uint32_t channel_no, uint8_t callback_type)`	None
`sl_status_t` sl_si91x_gpdma_transfer`(uint32_t channel, void src, void dest)`	None
`sl_status_t` sl_si91x_gpdma_stop_transfer`(uint32_t channel_no)`	None
`sl_status_t` sl_si91x_gpdma_allocate_descriptor`(sl_si91x_gpdma_descriptor_t *pDesc_memory, uint32_t transfer_size, uint32_t channel_number)`	None
`sl_status_t` sl_Si91x_gpdma_deallocate_descriptor`(uint32_t channel_number)`	None
`sl_status_t` sl_si91x_gpdma_build_descriptor`(sl_si91x_gpdma_descriptor_t pDescriptor_memory, sl_si91x_gpdma_descriptor_config_t pDesc_config, uint32_t transfer_size, uint32_t channel_number)`	None
`sl_status_t` sl_si91x_gpdma_allocate_fifo`(uint32_t channel_no, uint32_t fifo_size)`	None
`sl_status_t` sl_si91x_get_channel_fifo_size`(uint32_t channel_no, uint32_t *fifo_size)`	None
`sl_status_t` sl_si91x_gpdma_get_channel_status`(uint32_t channel_number)`	None
`sl_status_t` sl_si91x_button_deinit`(const sl_button_t *handle)`	None
`sl_status_t` sl_si91x_gpio_driver_set_soc_peri_on_ulp_pin_mode`(sl_gpio_t *gpio, sl_gpio_mode_t mode)`	None
`sl_status_t` sl_si91x_gpio_driver_set_ulp_peri_on_soc_pin_mode`(sl_gpio_t *gpio, sl_gpio_mode_t mode)`	None
`sl_status_t` sl_si91x_hspi_secondary_init`(void)`	None
`sl_status_t` sl_si91x_hspi_secondary_send_non_blocking`(void *data_buf)`	None
`sl_status_t` sl_si91x_hspi_secondary_receive_non_blocking`(void *data_buf)`	None
`uint32_t` sl_si91x_hspi_secondary_send_blocking`(const void *data)`	None
`uint32_t` sl_si91x_hspi_secondary_receive_blocking`(void *data)`	None
`sl_status_t` sl_si91x_hspi_secondary_register_event_callback`(sl_hspi_secondary_callback_t callback_event)`	None
`void` sl_si91x_hspi_secondary_unregister_event_callback`(uint32_t flag)`	None
`sl_hspi_secondary_version_t` sl_si91x_hspi_secondary_get_version`(void)`	None

Modified APIs#

None

Removed APIs#

None

Deprecated APIs#


Deprecated API Name	Planned Removal Date
sl_si91x_gpio_driver_mask_uulp_npss_interrupt	2026-12
sl_si91x_gpio_driver_unmask_uulp_npss_interrupt	2026-12
sl_si91x_gpio_driver_clear_uulp_interrupt	2026-12
sl_si91x_button_state_get	2026-12
sl_si91x_button_pin_state	2026-12
sl_si91x_button_state_toggle	2026-12
sl_si91x_button_state_set	2026-12
sl_si91x_rgb_led_init	2026-12
sl_si91x_rgb_led_on	2026-12
sl_si91x_rgb_led_off	2026-12
sl_si91x_rgb_led_get_current_state	2026-12
sl_si91x_rgb_led_toggle	2026-12

Bug Fixes#

Note: See the Feature Matrix section for a list of all hardware parts that work with the WiSeConnect 3 SDK.

ID	Issue Description	GitHub / Salesforce Reference (if any)	Affected Software Variants, Hardware, Modes, Host Interfaces
1436051	Issue in DMA de-init API with improper de-allocation of DMA channels.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1424712	Corrected the DMA transfer count in the ADC driver to use only the sample length value.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1414543	PSRAM device configuration files do not reflect the installed PSRAM device components.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1406552	ULP I2S component UC configuration is missing the GPIOs specified in the SiWG917 data sheet v1.0.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1379979	Addressed potential manual errors in PWM configuration by enforcing a build error if "All channels" is selected for the base timer without a `channel_0` instance.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1413169	Hard fault occurs in QEI de-init API due to a `NULL` pointer access, causing the program to enter the default handler.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1430079	QEI index and position values fail to reset in the QEI de-init API.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1448261	Eliminated the dependency on the FreeRTOS configuration file from the platform code.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1445491	Un-registering a single SSI instance in the SSI un-register callback results in all instances being un-registered, rather than just the specified SSI instance.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1401741	RHT sensor "No Hold Master" mode for temperature and humidity measurement does not work, and the API returns an error code.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1416569	Button 1 does not work after sleep due to the GPIO driver not re-initializing. This issue was fixed by adding the `sl_si91x_button_deinit` API to allow proper de-initialization and re-initialization of the button after sleep.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1435484	Sleep/wakeup failures occur when SDIO is used with both application processor and network processor set to power save mode with RAM retention.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1339252	Lack of thread safety in `malloc` leads to infinite loops during multi-threaded execution.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC, NCP. Host interfaces: SPI, UART
1424184	Added validation in the ADC init API to ensure that the number of channels selected in the common configuration matches the number of channels/instances added.	None	Firmware variants: Standard and Lite OPNs: All Boards: All Modes: SoC Host interfaces: N/A

Chip Enablement#

None

Application Example Changes#

New Examples | Modified Examples | Removed Examples | Deprecated Examples

Note: See the Feature Matrix section for a list of all hardware parts that work with the WiSeConnect 3 SDK.

New Examples#

Example Name	Description	Supported Software Variants (if applicable)	Supported Modes	Supported OPNs / Boards / OPN Combinations	Supported Host Interfaces
SL Si91x - BOD See README	Demonstrates the configuration of the threshold value for BOD and monitoring the voltage levels on VMCU. When the voltage drops below the configured threshold, a BOD interrupt is triggered, and the application handles the event accordingly.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - UART RS485 See README	Demonstrates the configuration of UART0/1 to use in RS485 multidrop mode and to send and receive data.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - OPAMP See README	Demonstrates the initialization, configuration, and operation of the OPAMP peripheral by giving input on the non-inverting terminal and inverting terminal of the OPAMP and checking the output. This application example configures the OPAMP instances for various use cases, including integration with DAC for external voltage comparison.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - GPDMA See README	Demonstrates memory-to-memory DMA transfers of various sizes. Users can change the DMA transfer size by updating `TRANSFER_LENGTH`. This application example performs a generic DMA transfer using either a pre-defined configuration or a user-defined descriptor.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - HSPI Secondary See README	Demonstrates the SoC clock configuration and HSPI secondary initialization with GPDMA, ensuring smooth communication with the SPI primary and efficient callback management for HSPI operations.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - PCM Loopback See README	Demonstrates the PCM loopback functionality.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - PCM Primary See README	Demonstrates the PCM primary device data transfer using the I2S interface.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - PCM Secondary See README	Demonstrates the PCM secondary device transfer using the I2S interface.	Standard and Lite	SoC	OPNs: All Boards: All	N/A

Modified Examples#

Example Name	Changes	Supported Software Variants if applicable	Supported Modes	Supported OPNs / Boards / OPN Combinations	Supported Host Interfaces
SL Si91x - RTOS Message Queue See README	Updated with I2C driver code for data communication.	Standard and Lite	SoC	OPNs: All Boards: All	N/A
SL Si91x - Config Timer See README	Initialized a local variable to prevent un-intended output.	Standard and Lite	SoC	OPNs: All Boards: All	N/A

Example Name

Changes

Supported Software Variants if applicable

Supported Modes

Supported OPNs / Boards / OPN Combinations

Supported Host Interfaces

SL Si91x - RTOS Message Queue

See README

Updated with I2C driver code for data communication.

Standard and Lite

SoC

OPNs: All
Boards: All

N/A

SL Si91x - Config Timer

See README

Initialized a local variable to prevent un-intended output.

Standard and Lite

SoC

OPNs: All
Boards: All

N/A

Removed Examples#


Removed Example Name	Was Deprecated?
Si91x - CPC SDIO Secondary FreeRTOS with Security	No

Deprecated Examples#

None

Known Issues and Limitations#

Note: See the Feature Matrix section for a list of all hardware parts that work with the WiSeConnect 3 SDK.

ID	Issue or Limitation Description	GitHub / Salesforce Reference (if any)	Workaround (if any)	Affected Software Variants, Hardware, Modes, Host Interfaces
1455245	Blackout reset fails to occur on module board SiW917Y-RB4343A Rev. A07.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1437906	According to the HRM for BOD, the minimum threshold voltage is 1.75 V, but the hardware triggers an interrupt at 1.9 V or below.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1438016	BOD does not function in ULP power state PS2.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1417168	While mbedTLS components and SI91X-PSA driver components are visible in the Simplicity Studio GUI, the PSA components themselves are not displayed. This causes project compilation failures when security modules are manually added to the project.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
1364360	For peripherals that support multiple instances, Simplicity Studio's "Add New Instance" feature suggests default instance names (e.g., `inst0`, `inst1`) which might differ from the instance names supported in the reference documentation and application examples. Users should refer to peripheral-specific documentation for the officially supported instance naming conventions.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
N/A	The ULP Timer may experience timer drifts due to the inaccuracy of the clock source (RC oscillator).	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
N/A	FreeRTOS tick-less idle mode is currently not supported in the Sensor Hub example application.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
N/A	Only a few wakeup sources (ULP GPIO, ULP Timer, ULP ADC, ULP Comparator, ULP UART) are currently supported for the PS1 state in the Power Manager.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
N/A	Peripheral clock sources are currently fixed and cannot be configured by the user.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A
N/A	GPDMA driver currently supports only memory-to-memory transfers.	None	None	OPNs: All Boards: All Modes: SoC Host interfaces: N/A