Ultra-Low-Power (ULP) Timer Developer Guide#
The Ultra-Low-Power (ULP) Timer in the SiWx917 device provides four independent timers designed for efficient operation during low-power and sleep modes. Each timer can generate interrupts to wake the microcontroller (MCU) when required.
You can configure each timer for one-shot or periodic operation, select the desired clock source, and adjust resolution and direction based on your timing needs.
This guide explains how to configure ULP Timers using Simplicity Studio’s Universal Configurator (UC), integrate timers with low-power states, and debug common issues.
By following these steps, you can reliably implement ULP Timers for power-sensitive applications.
What Is a ULP Timer?#
A ULP Timer acts as a precise hardware stopwatch that continues to run even when the MCU is in sleep or low-power mode. It enables timekeeping and scheduling functions without keeping the CPU active, improving energy efficiency.
ULP Timers are especially useful for:
Scheduled wake-ups: Periodically wake the MCU to perform routine tasks (for example, sensor data collection).
Accurate timing: Measure intervals or sensor response durations with microsecond precision.
Periodic events: Generate recurring events autonomously without software timers.
Battery optimization: Extend device runtime by eliminating unnecessary CPU activity.
Tip: ULP Timers are ideal for Internet of Things (IoT) devices, wearables, and remote sensors that need precise timing while maintaining long battery life.
About This Guide#
This guide provides end-to-end implementation guidance for ULP Timers on SiWx917 devices.
Section | Purpose |
|---|---|
Use case | Periodically wake the system to sample sensors, handle timeouts, or perform maintenance while minimizing energy usage. |
Audience | Firmware developers and system engineers integrating low-power timing into SiWx917-based designs. |
Scope | Covers ULP hardware timers (4 × 32-bit), UC configuration, driver APIs ( |
Real-World Example#
A smart environmental sensor wakes every 30 seconds to take a reading and then returns to sleep to conserve energy.
Without a ULP Timer, the MCU would require a running software timer, consuming power continuously.
With a ULP Timer, the MCU remains asleep until precisely awakened by the hardware timer, ensuring efficient operation and accurate timing.
Key Features#
The ULP Timer block in SiWx917 includes these key capabilities:
Feature | Description |
|---|---|
Four independent timers | Operate multiple timers simultaneously for different tasks such as LED blinking, sensor sampling, and housekeeping. |
Flexible clock options | Choose from low-frequency (32 kHz) or high-frequency (32 MHz) sources depending on accuracy and energy requirements. |
Clock division | Use dividers to balance timing resolution and power efficiency. |
One-shot and periodic modes | Configure timers for single or continuous operation. |
Interrupts on timeout | Automatically trigger an interrupt when a timer expires. |
Wake-up capability | Wake the MCU from low-power states using timer events. |
Note: ULP Timers are part of the ULP Subsystem (ULPSS) and are optimized for power-aware designs.
Power State Reference#
The table below describes how ULP Timers operate across different power states.
Power State | Description | ULP Timer Status | Clock Domain | Typical Use Cases |
|---|---|---|---|---|
PS4 | High-power mode | Fully operational | Active | Full functionality |
PS2 | Ultra-low-power mode | Fully operational | Active | Sleep mode timing and wake scheduling |
PS1 | Sleep mode | Wake source only | Limited | Wake source configuration required |
PS0 | Deep-sleep mode | Not available | Gated | Timer disabled |
Note: The ULP Timer operates in PS4 and PS2, functions as a wake source in PS1, and is disabled in PS0.
Technical Specifications#
The ULP Timer supports multiple clock sources, flexible timing resolution, and direct integration with the SiWx917 power management system.
Clock Sources#
Clock Source | Description | Power Usage | Accuracy |
|---|---|---|---|
Reference Clock (REF, 32 MHz) | High-speed reference for precise timing. | High | ±0.1% |
32 kHz Crystal (XTAL) | Ultra-low power, high accuracy. | Very low | ±0.1% |
32 kHz RC Oscillator | Low power, moderate accuracy. | Low | ±1% |
MHz RC Oscillator | Medium power, balanced performance. | Medium | ±0.5% |
System-on-Chip (SoC) Clock | Derived from main system clock. | Varies | Matches system source |
Timer Capabilities#
Parameter | Specification |
|---|---|
Resolution | From 31.25 ns (32 MHz) to 31.25 µs (32 kHz) |
Range | Up to ~49 days at 32 kHz |
Accuracy | ±1% to ±0.1% depending on clock source |
Power consumption | 0.5 µA to 2 mA depending on mode and clock |
System Integration#
The ULP Timer interfaces directly with the ULP Subsystem (ULPSS), the Power Manager, and system interrupts.
Component | Integration Role |
|---|---|
ULPSS | Operates in a dedicated low-power domain, ensuring independent timing from the main MCU. |
Power Manager | Manages timer wake-up configuration during sleep and deep sleep transitions. |
Nested Vector Interrupt Controller (NVIC) | Handles interrupt delivery for timer expiration events. |
General-Purpose Input/Output (GPIO) | Routes timer events to external pins when required for hardware coordination. |
Tip: Configure the ULP Timer through UC for automatic code generation, or initialize it programmatically using the ULP Timer driver APIs for flexible runtime control.