Synchronous Serial Interface (SSI) Architecture#

Peripheral Overview#

The Synchronous Serial Interface (SSI) on SiWx917 is a flexible, full-duplex synchronous serial controller.

It supports Serial Peripheral Interface (SPI), Synchronous Serial Protocol (SSP), and Microwire (µWire) standards, with optional dual and quad data lines for higher throughput. SSI integrates with DMA for offloading the CPU, and supports low-power operation depending on the selected instance and power state.

SSI scales from high-bandwidth use cases, such as external flash memory and display controllers, to energy-efficient transfers where DMA minimizes CPU activity and allows the core to sleep.

General Description#

The SiWx917 device includes multiple configurable SSI controllers that support common synchronous serial protocols (SPI, SSP, Microwire).
Each instance can operate as either a primary that initiates communication or as a secondary that responds to an external controller.

On this SoC:

• Two SSI instances support primary operation.

• One SSI instance supports secondary operation.

Key Features and Capabilities#

The SSI peripheral on SiWx917 is a high-performance, flexible serial controller that provides the following capabilities:

• Protocol support: Operates as primary or secondary using SPI, SSP, or Microwire (µWire) protocols.

• Dual/Quad support (primary): The HP SSI primary supports single, dual, and quad data lines. The ULP SSI primary supports single-bit operation.

• Data frame size: Programmable 4–16-bit frame length. Microwire control-word length is also configurable (1–16 bits).

• DMA and FIFO integration: Supports DMA handshake signals with programmable FIFO thresholds. Each FIFO is 16 words deep.

• Interrupts: Maskable interrupts for TX empty/overflow, RX full/underflow/overflow, and multi-primary contention (if applicable).

• Programmable RX sample delay: Adjusts sampling at high-speed operation to improve reliability.

• Chip-select fan-out (primary): Up to four chip-select outputs from the HP SSI primary instance (enabled via SER).

• ULP SSI primary: The ULP SSI instance supports only one secondary device.

• Clock configuration: Programmable CPOL and CPHA for SPI mode control.

• High-speed operation:

  • HP SSI (Primary): Up to 40 MHz in high-speed mode or 20 MHz in full-speed mode.

  • SSI Secondary: Up to 20 MHz

  • ULP SSI Primary: Up to 10 MHz

SSI Architecture (High-Level)#

The SiWx917 SSI uses a programmable synchronous-serial engine with FIFO buffering, DMA handshakes, and interrupt control to achieve high throughput with minimal CPU overhead.

Figure: High-level SSI architecture.

Functional Blocks#

Why It Matters#

• High performance: DMA and FIFOs reduce CPU involvement, allowing for continuous data streaming.

• Deterministic timing: The prescaler and shift logic guarantee protocol-compliant edge control.

• Simplified debugging: Status registers and interrupts streamline validation and troubleshooting.

Software Architecture#

This section describes the SSI software stack and how the software layers interact during configuration and data transfer.

Figure: SSI software layering showing control and data paths.

Software Layering Overview#

Directory Structure in WiSeConnect SDK#

wiseconnect/
├── components/
│   └── device/
│       └── silabs/
│           └── si91x/
│               └── mcu/
│                   └── drivers/
│                       ├── cmsis_driver/
│                       │   ├── CMSIS/Include/Driver_SPI.h
│                       │   ├── SPI.c
│                       │   └── SPI.h
│                       ├── peripheral_drivers/
│                       │   ├── inc/rsi_spi.h
│                       │   └── src/rsi_spi.c
│                       └── unified_api/s
│                           ├── inc/sl_si91x_ssi.h
│                           └── src/sl_si91x_ssi.c
└── examples/
    └── si91x_soc/
        └── peripheral/
            ├── sl_si91x_ssi_master
            ├── sl_si91x_ssi_slave
            └── sl_si91x_ulp_ssi_master

Core Components#

SSI Primary (High-performance Primary)#

• Purpose: Supports high-speed communication in the HP domain.

• Features: Single, dual, and quad SPI modes.

• Capabilities: Connects to up to four secondary devices.

• Performance: Operates up to 40 MHz.

• Typical Use Cases: External flash access, display interfaces, and high-rate sensor communication.

SSI ULP Primary (Ultra-low-power Primary)#

• Purpose: Enables low-power communication in the ULP domain.

• Features: Single-bit SPI mode.

• Capabilities: Connects to one secondary device.

• Performance: Operates up to 10 MHz.

• Power Benefits: Supports DMA-based transfers while the MCU remains in a low-power (PS2) state.

• Typical Use Cases: Battery-powered systems requiring background or sleep-mode data exchange.

SSI Secondary#

• Purpose: Operates as a programmable secondary peripheral.

• Features: Supports all SPI modes and framing protocols.

• Capabilities: Provides full-duplex communication.

• Typical Use Cases: Device-to-device communication and multi-primary networked systems.

Clock Architecture and Timing#

The SSI clock system manages synchronization between the SSI input clock (ssi_clk), peripheral clock (pclk), and serial clock output (sclk_out).

Clock Domain Relationships#

• The SSI input clock (ssi_clk) must not exceed the APB clock (pclk) for reliable synchronization.

• When pclk and ssi_clk are asynchronous, synchronization logic is automatically enabled.

• In primary mode, the maximum frequency of the serial clock output (sclk_out) is one-half the frequency of ssi_clk.The shift logic samples data on one edge and drives it on the opposite edge.

Fsclk_out = Fssi_clk / SCKDV

Parameters#

Frequency Restrictions#

• Primary Mode: Fssi_clk ≥ 2 × (max Fsclk_out)

• Secondary Mode: Fssi_clk ≤ 4 × (max Fsclk_in)

Operation Modes#

This section describes the operation modes of the SSI on the SiWx917.

Primary Mode#

In primary mode, the SSI peripheral initiates and controls all data transfers.

The primary generates the clock and manages communication with connected secondary devices.

Figure: SSI primary device configuration.

SPI Frame Format#

A SPI frame asserts the selected chip-select line, shifts a programmed 4–16-bit word MSB first (CTRLR0.DFS_32), and maintains continuous clocking if configured for back-to-back frames.

The chip-select (SS) is de-asserted after the final bit unless configured otherwise.

Internally, clk_driv launches transmit data (txd) and clk_cap samples received data (rxd).
The clock stops automatically when idle.

Frame Format for Motorola SPI with SCPH = 0

Frame Format for Motorola SPI with SCPH = 1

Clock polarity (CPOL) and phase (CPHA) define the SPI mode (0–3):

Dual and Quad SPI Modes#

The SSI supports dual and quad SPI operation to increase data throughput by transferring multiple bits per clock cycle.

Quad SPI Frame Format#

A quad SPI transaction is divided into four configurable phases:

1. Instruction Phase – Sends the command to the target device (length and width configurable).

2. Address Phase – Sends the target address using one, two, or four lines.

3. Wait-Cycle Phase – Inserts programmable wait cycles for timing at high frequencies.

4. Data Phase – Transfers data to or from memory using one, two, or four lines.

Table: Data Phase Configuration vs. Quad-SPI Functional Modes

Instruction and Address Phase Formats in Dual/Quad SPI Modes#

The transfer format is controlled by the TRANS_TYPE field.

Write Operation (Dual/Quad Modes)#

A write transaction includes:

1. Instruction phase

2. Address phase

3. Data phase

Configuration Fields:

• CTRLR0.SPI_FRF — Selects data-line width (standard/dual/quad)

• SPI_CTRLR0.INST_L and SPI_CTRLR0.ADDR_L — Define instruction and address lengths

• CTRLR0.DFS_32 — Sets the data-frame size (4–16 bits)

Read Operation (Dual/Quad Modes)#

A read transaction includes:

1. Instruction phase

2. Address phase

3. Wait cycles (SPI_CTRLR0.WAIT_CYCLES)

4. Data phase

Configuration Fields:

• CTRLR0.SPI_FRF — Selects data-line width (standard/dual/quad).

• SPI_CTRLR0.TRANS_TYPE — Sets instruction and address transfer types.

• SPI_CTRLR0.WAIT_CYCLES — Defines dummy cycles between address and data.

• CTRLR1.NDF — Specifies number of data frames to receive.

• CTRLR0.DFS_32 — Sets data-frame size (4–16 bits).

Dependencies#

Hardware Dependencies#

• GPIO Controller: Configures SCLK, chip-select lines, and up to four data lines (D0–D3).

• DMA Controller: Enables high-throughput, non-blocking data transfers.

Software Dependencies#

• sl_si91x_ssi – Core driver for initialization, configuration, and transfer operations.

• sl_si91x_gpio – Manages pin configuration and routing.

• sl_si91x_dma – Provides DMA support for continuous or high-speed transfers.

The Simplicity Studio Project Configurator manages all dependencies, including clock, power, GPIO, and DMA components automatically.