Extended Custom Feature Bitmap#

SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT#

#define SL_SI91X_EXT_FEAT_RSA_KEY_WITH_4096_SUPPORT

BIT(1)

Supports 4096 size RSA KEY certificate.

Enabling this bit allows the device to support 4096-bit RSA keys. Recommended only if 4096-bit keys are required.

Note

• Bit 0 is reserved.

SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT#

#define SL_SI91X_EXT_FEAT_SSL_CERT_WITH_4096_KEY_SUPPORT

BIT(3)

Supports 4096 size KEY SSL certificate.

Enabling this bit allows the device to support SSL certificates with 4096-bit keys. Recommended only if 4096-bit keys are required.

Note

• Bit 2 is reserved.

SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_BEFORE_DTIM#

#define SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_BEFORE_DTIM

BIT(4)

Extended custom bitmap for AP broadcast customization.

Enabling this bit configures the Access Point to send broadcast packets before the Delivery Traffic Indication Message (DTIM) interval.

Note

• If this bit is enabled, the clients connected in power save mode might miss the packets.

SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM#

#define SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM

SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_BEFORE_DTIM

Extended custom bitmap for AP broadcast customization.

Enabling this bit configures the Access Point to send broadcast packets before the DTIM (Delivery Traffic Indication Message) interval.

Note

• If this bit is enabled, the clients connected in power save mode might miss the packets.

• The macro SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_B4_DTIM is being deprecated and will be removed in the future. Use SL_SI91X_EXT_FEAT_AP_BROADCAST_PKT_SND_BEFORE_DTIM instead.

SL_SI91X_EXT_FEAT_FCC_LOW_PWR#

#define SL_SI91X_EXT_FEAT_FCC_LOW_PWR

BIT(5)

Extended custom bitmap to support FCC (currently not supported).

Enabling this bit allows the device to operate in a mode that complies with Federal Communications Commission (FCC) regulations for low power operation.

SL_SI91X_EXT_FEAT_PUF#

#define SL_SI91X_EXT_FEAT_PUF

BIT(7)

To enable Physical Unclonable Function (PUF).

Enabling this bit activates the Physical Unclonable Function feature, which provides a unique identifier for each device based on its physical characteristics.

Note

• Bit 6 is reserved.

SL_SI91X_EXT_FEAT_NWP_QSPI_80MHZ_CLK_ENABLE#

#define SL_SI91X_EXT_FEAT_NWP_QSPI_80MHZ_CLK_ENABLE

BIT(8)

To switch NWP QSPI clock to 80 MHz.

Enabling this bit switches the NWP QSPI clock from the default 40 MHz to 80 MHz. By increasing the QSPI clock speed, flash execution accelerates, resulting in improved throughput (in cases where flash execution is involved).

SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER#

#define SL_SI91X_EXT_HTTP_SKIP_DEFAULT_LEADING_CHARACTER

BIT(9)

Extended feature bitmap to skip default leading character '\' in HTTP header.

Enabling this bit configures the device to omit the default leading character '\' in HTTP headers, allows for custom header formatting.

SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY#

#define SL_SI91X_EXT_FEAT_PUF_PRIVATE_KEY

BIT(10)

To enable PUF (Physical Unclonable Function) private key.

Enabling this bit activates the use of a private key associated with the PUF feature for enhanced security.

SL_SI91X_EXT_FEAT_ENABLE_11R_OTA#

#define SL_SI91X_EXT_FEAT_ENABLE_11R_OTA

BIT(11)

To enable 802.11R Over The Air Roaming (currently not supported).

Enabling this bit activates support for 802.11R (Fast BSS Transition) Over The Air Roaming, which improves the handoff experience between access points.

Note

• Resource Request Support is not present.

• If both BIT[11] and BIT[16] are not enabled, the device would default to Legacy Roaming.

SL_SI91X_EXT_FEAT_IEEE_80211J#

#define SL_SI91X_EXT_FEAT_IEEE_80211J

BIT(12)

To enable 802.11J protocol (currently not supported).

Enabling this bit activates support for the 802.11J protocol, which is used for wireless communication in Japan.

Note

• If this bit is enabled, the set region command is mandatory with the region set to Japan and the band value must be 1.

SL_SI91X_EXT_FEAT_IEEE_80211W#

#define SL_SI91X_EXT_FEAT_IEEE_80211W

BIT(13)

To enable 802.11W protocol.

Enabling this bit activates support for the 802.11W protocol, which provides management frame protection.

Note

• This bit must be set to enable WPA3 Personal Mode and WPA3 Personal Transition mode.

SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT#

#define SL_SI91X_EXT_FEAT_SSL_VERSIONS_SUPPORT

BIT(14)

To enable the Multi-version TCP over SSL support.

Enabling this bit allows the device to support multiple versions of SSL/TLS over TCP, providing flexibility in handling different SSL/TLS versions.

SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE#

#define SL_SI91X_EXT_FEAT_16th_STATION_IN_AP_MODE

BIT(15)

To enable 16 client support in Access Point (AP) mode.

Enabling this bit allows up to 16 stations to connect to the device when it is operating in AP mode.

Note

• If this bit is enabled, up to 16 stations can connect; otherwise, a maximum of 8 stations can connect.

SL_SI91X_EXT_FEAT_ENABLE_11R_ODS#

#define SL_SI91X_EXT_FEAT_ENABLE_11R_ODS

BIT(16)

To enable 802.11R Over the Distribution System Roaming.

Enabling this bit activates support for 802.11R (Fast BSS Transition) Over the Distribution System Roaming, which enhances roaming performance across different access points in the distribution system.

Note

• 1. Resource Request Support is not present.

• 2. If both BIT[11] and BIT[16] are not enabled, the device would default to Legacy Roaming.

SL_SI91X_EXT_FEAT_WOWLAN_DISABLE#

#define SL_SI91X_EXT_FEAT_WOWLAN_DISABLE

BIT(17)

To disable the WoWLAN (Wake-on-Wireless-LAN) feature.

Enabling this bit disables the WoWLAN feature, which is used for waking the device from a low-power state through wireless network activity. By default WOW LAN Is enabled to maintain backward compatibility. So given option to disable this feature.

Note

• This only valid in NCP mode.

SL_SI91X_EXT_FEAT_DISABLE_XTAL_CORRECTION#

#define SL_SI91X_EXT_FEAT_DISABLE_XTAL_CORRECTION

BIT(18)

To disable auto correction of XTAL (40 MHz crystal)

Enabling this bit would disable the automatic compensation for frequency offsets, ensuring error-free calibration.

Note

• This bit should be enabled in the following cases:

• 1. Always enable it in the Calibration application.

• 2. Enable it for all applications for the customer hardware with an XTAL part number other than 8Y40070013.

SL_SI91X_EXT_FEAT_LOW_POWER_MODE#

#define SL_SI91X_EXT_FEAT_LOW_POWER_MODE

BIT(19)

To enable low power mode in WLAN.

Enabling this bit activates low power mode for WLAN, Active current would also be reduced. As most of the code which is needed to maintain connection is kept in RAM. There would be minimal execution of code from Flash which in turn results in low average current.

SL_SI91X_EXT_FEAT_352K_M4SS_320K#

#define SL_SI91X_EXT_FEAT_352K_M4SS_320K

0

To enable 352K memory for NWP and 320K memory for M4.

Enable 352K memory for NWP.

This configuration allocates 352K memory to the Network Processor (NWP) and 320K memory to the M4 core.

The remaining memory will be unused. This macro is applicable for NCP mode only.

SL_SI91X_EXT_FEAT_352K_M4SS_320K#

#define SL_SI91X_EXT_FEAT_352K_M4SS_320K

SL_SI91X_EXT_FEAT_352K

To enable 352K memory for NWP and 320K memory for M4.

Enable 352K memory for NWP.

This configuration allocates 352K memory to the Network Processor (NWP) and 320K memory to the M4 core.

The remaining memory will be unused. This macro is applicable for NCP mode only.

SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV

SL_SI91X_EXT_FEAT_352K_M4SS_320K

To enable basic NWP and advanced MCU RAM level configuration.

To enable basic NWP RAM level configuration.

This setting configures the NWP with a basic memory level while providing the MCU with an advanced memory configuration.

Note

• This configuration uses SL_SI91X_EXT_FEAT_352K_M4SS_320K.

This macro is applicable for NCP mode only.

This setting configures the Network Processor (NWP) with 352K of memory in NCP mode.

Note

• This setting is suitable for low-power examples that do not require significant memory for the NWP.

SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC_MCU_ADV

SL_SI91X_EXT_FEAT_352K

To enable basic NWP and advanced MCU RAM level configuration.

To enable basic NWP RAM level configuration.

This setting configures the NWP with a basic memory level while providing the MCU with an advanced memory configuration.

Note

• This configuration uses SL_SI91X_EXT_FEAT_352K_M4SS_320K.

This macro is applicable for NCP mode only.

This setting configures the Network Processor (NWP) with 352K of memory in NCP mode.

Note

• This setting is suitable for low-power examples that do not require significant memory for the NWP.

SL_SI91X_EXT_FEAT_416K_M4SS_256K#

#define SL_SI91X_EXT_FEAT_416K_M4SS_256K

BIT(21)

To enable 416K memory for NWP and 256K memory for M4.

This macro is applicable only for SoC mode.

This configuration allocates 416K memory to the Network Processor (NWP) and 256K memory to the M4 core.

Note

• Ensure that RAM bank 9 remains powered ON in the M4 for low power application use cases.

SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM#

#define SL_SI91X_RAM_LEVEL_NWP_MEDIUM_MCU_MEDIUM

SL_SI91X_EXT_FEAT_416K_M4SS_256K

To enable medium NWP and medium MCU RAM level configuration.

This setting configures both the NWP and the MCU with medium memory levels.

Note

• This configuration uses SL_SI91X_EXT_FEAT_416K_M4SS_256K.

SL_SI91X_EXT_FEAT_480K_M4SS_192K#

#define SL_SI91X_EXT_FEAT_480K_M4SS_192K

BIT(20)

To enable 480K memory for NWP and 192K memory for M4.

This macro is applicable only for SoC mode.

This configuration allocates 480K memory to the Network Processor (NWP) and 192K memory to the M4 core.

Note

• Ensure that RAM banks 8, and 9 remain powered ON in the M4 for low power application use cases.

SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC#

#define SL_SI91X_RAM_LEVEL_NWP_ADV_MCU_BASIC

SL_SI91X_EXT_FEAT_480K_M4SS_192K

To enable advanced NWP and basic MCU RAM level configuration.

This setting configures the NWP with an advanced memory level while providing the MCU with a basic memory configuration.

Note

• This configuration uses SL_SI91X_EXT_FEAT_480K_M4SS_192K.

SL_SI91X_EXT_FEAT_352K#

#define SL_SI91X_EXT_FEAT_352K

0

To enable 352K memory for NWP.

SL_SI91X_RAM_LEVEL_NWP_BASIC#

#define SL_SI91X_RAM_LEVEL_NWP_BASIC

SL_SI91X_EXT_FEAT_352K

To enable basic NWP RAM level configuration.

This setting configures the Network Processor (NWP) with 352K of memory.

SL_SI91X_EXT_FEAT_672K#

#define SL_SI91X_EXT_FEAT_672K

(BIT(20) | BIT(21))

To enable 672K memory for NWP.

This macro is applicable for NCP mode only.

SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_AVAILABLE

SL_SI91X_EXT_FEAT_672K

To enable full NWP RAM level configuration.

This setting configures the NWP with 672K of memory.

SL_SI91X_EXT_FEAT_672K_M4SS_0K#

#define SL_SI91X_EXT_FEAT_672K_M4SS_0K

SL_SI91X_EXT_FEAT_672K

To enable 672K memory for NWP and 0K memory for M4.

This macro is applicable for NCP mode only.

This setting configures the Network Processor (NWP) with 672K of memory and allocates no memory to the M4 core in NCP mode.

SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO#

#define SL_SI91X_RAM_LEVEL_NWP_ALL_MCU_ZERO

SL_SI91X_EXT_FEAT_672K

To enable full NWP RAM level configuration.

This macro is applicable for NCP mode only.

This setting configures the NWP with 672K of memory and allocates no memory to the M4 core in NCP mode.

SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE#

#define SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE

(xtal_clk_enable)

To enable crystal clock for NWP.

This macro configures the sleep clock source selection for the NWP. Following are the options:

Note

• For 917 radio boards, set SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE to 1. For other variants, a value of 2 is recommended.

SL_SI91X_EXT_FEAT_XTAL_CLK#

#define SL_SI91X_EXT_FEAT_XTAL_CLK

SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE(2)

Define to enable 32 KHz crystal clock using the external XTAL OSCILLATOR.

This macro sets the SL_SI91X_EXT_FEAT_XTAL_CLK_ENABLE with a value of 2, which configures the sleep clock source to use the 32 KHz clock from the external XTAL OSCILLATOR.

SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED#

#define SL_SI91X_EXT_FEAT_HOMEKIT_WAC_ENABLED

BIT(24)

To inform firmware not to modify mDNS text records.

Enabling this bit indicates that the firmware should not alter mDNS (Multicast DNS) text records.

SL_SI91X_EXT_FEAT_1P8V_SUPPORT#

#define SL_SI91X_EXT_FEAT_1P8V_SUPPORT

BIT(25)

To enable 1.8V support for NWP.

Enabling this bit activates support for 1.8 V operation.

SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS#

#define SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS

BIT(27)

To select UART for debug prints pin selection.

If BIT(27) is enabled, debug prints are supported on UART1. If BIT(27) is disabled, debug prints are supported on UART2.

Note

• Bit 26 is reserved.

• By default, all debug prints from the device network processor would be sent to UART2 if this bit is not enabled. UART1 pins are mapped as follows:

  • UART1-TX: GPIO_9

  • UART1-RX: GPIO_8

  • UART2-TX: GPIO_6

  • UART2-RX: GPIO_10

Ensure these pins are not used in MCU applications in SoC mode to avoid pin usage conflicts. This bit is valid only if BIT[28] in the ext_custom_feature_bit_map is set to 0. There is no functionality on RX pins for debug prints.

SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS#

#define SL_SI91X_EXT_FEAT_DISABLE_DEBUG_PRINTS

BIT(28)

To disable debug prints support in NWP.

By default the prints would be coming on UART2. If this bit is enabled, disable debug prints. To enable prints on UART 1 SL_SI91X_EXT_FEAT_UART_SEL_FOR_DEBUG_PRINTS bit needs to set.

SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0#

#define SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0

BIT(29)

To configure frontend with selection BIT[30:29] for 917B0.

This bit configures the frontend switch pins based on the following table:

Note

• SiWx917 has an integrated on-chip Transmit/Receive (T/R) switch. This internal RF switch configuration uses internal logic present in the IC, and GPIOs are not needed. RF_BLE_TX (8 dBm) mode is not supported in this configuration.

• VC1, VC2, and VC3 are control voltage pins of the RF switch.

SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH#

#define SL_SI91X_EXT_FEAT_FRONT_END_INTERNAL_SWITCH

BIT(30)

To enable the internal front-end switch configuration.

Enabling this bit selects the internal front-end switch configuration for the frontend. This configuration uses internal logic present in the IC, eliminating the need for external GPIOs.

SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE#

#define SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE

BIT(31)

To enable Bluetooth custom features.

Enabling this bit activates Bluetooth custom features. If this bit is enabled then only, the features present in the Bluetooth custom feature can be used.