CMU - Clock Management Unit#

CMU_HFRCOFreq_TypeDef#

CMU_HFRCOFreq_TypeDef

High-frequency system RCO bands.

CMU_AUXHFRCOFreq_TypeDef#

CMU_AUXHFRCOFreq_TypeDef

AUX high-frequency RCO bands.

CMU_Clock_TypeDef#

CMU_Clock_TypeDef

Clock points in CMU.

See CMU overview in the reference manual.

CMU_Osc_TypeDef#

CMU_Osc_TypeDef

Oscillator types.

CMU_OscMode_TypeDef#

CMU_OscMode_TypeDef

Oscillator modes.

CMU_Select_TypeDef#

CMU_Select_TypeDef

Selectable clock sources.

CMU_HFXOTuningMode_TypeDef#

CMU_HFXOTuningMode_TypeDef

HFXO tuning modes.

CMU_DPLLClkSel_TypeDef#

CMU_DPLLClkSel_TypeDef

DPLL reference clock selector.

CMU_DPLLEdgeSel_TypeDef#

CMU_DPLLEdgeSel_TypeDef

DPLL reference clock edge detect selector.

CMU_DPLLLockMode_TypeDef#

CMU_DPLLLockMode_TypeDef

DPLL lock mode selector.

CMU_ClkDiv_TypeDef#

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.

CMU_ClkPresc_TypeDef#

typedef uint32_t CMU_ClkPresc_TypeDef

Clockprescaler configuration.

CMU_AUXHFRCOBandGet#

CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet (void )

Get the current AUXHFRCO frequency.

Returns

• AUXHFRCO frequency.

CMU_AUXHFRCOBandSet#

void CMU_AUXHFRCOBandSet (CMU_AUXHFRCOFreq_TypeDef setFreq)

Set AUXHFRCO calibration for the selected target frequency.

CMU_Calibrate#

uint32_t CMU_Calibrate (uint32_t HFCycles, CMU_Osc_TypeDef reference)

Calibrate the clock.

Run a calibration for HFCLK against a selectable reference clock. See the reference manual, CMU chapter, for more details.

Note

• This function will not return until the calibration measurement is completed.

Returns

• The number of ticks the reference clock after HFCycles ticks on the HF clock.

CMU_CalibrateConfig#

void CMU_CalibrateConfig (uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)

Configure the clock calibration.

Configure a calibration for a selectable clock source against another selectable reference clock. See the reference manual, CMU chapter, for more details.

Note

• After configuration, a call to CMU_CalibrateStart() is required and the resulting calibration value can be read out with the CMU_CalibrateCountGet() function call.

CMU_CalibrateCountGet#

uint32_t CMU_CalibrateCountGet (void )

Get the calibration count register.

Note

• If continuous calibration mode is active, calibration busy will almost always be off and only the value needs to be read. In a normal case, this function call is triggered by the CALRDY interrupt flag.

Returns

• The calibration count, the number of UPSEL clocks in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.

CMU_ClockEnable#

void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

In general, module clocking is disabled after a reset. If a module clock is disabled, the registers of that module are not accessible and reading from such registers may return undefined values. Writing to registers of clock-disabled modules has no effect. Avoid accessing module registers of a module with a disabled clock.

Note

• If enabling/disabling an LF clock, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

CMU_ClockDivGet#

CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)

Get the clock divisor/prescaler.

Returns

• The current clock point divisor/prescaler. 1 is returned if clock specifies a clock point without a divisor/prescaler.

CMU_ClockDivSet#

void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set the clock divisor/prescaler.

Note

• If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

CMU_ClockFreqGet#

uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)

Get the clock frequency for a clock point.

Returns

• The current frequency in Hz.

CMU_ClockPrescSet#

void CMU_ClockPrescSet (CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)

Set the clock prescaler.

Note

• If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

CMU_ClockPrescGet#

uint32_t CMU_ClockPrescGet (CMU_Clock_TypeDef clock)

Get the clock prescaler.

Returns

• The prescaler value of the current clock point. 0 is returned if clock specifies a clock point without a prescaler.

CMU_ClockSelectSet#

void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select the reference clock/oscillator used for a clock branch.

Notice that if a selected reference is not enabled prior to selecting its use, it will be enabled and this function will wait for the selected oscillator to be stable. It will however NOT be disabled if another reference clock is selected later.

This feature is particularly important if selecting a new reference clock for the clock branch clocking the core. Otherwise, the system may halt.

Note

• HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.

CMU_ClockSelectGet#

CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)

Get the currently selected reference clock used for a clock branch.

Returns

• The reference clock used for clocking the selected branch, cmuSelect_Error if invalid clock provided.

CMU_LF_ClockPrecisionGet#

uint16_t CMU_LF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

Returns

• Precision, in PPM, of the specified clock branch.

Note

• This function is only for internal usage.

• The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

CMU_HF_ClockPrecisionGet#

uint16_t CMU_HF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

Returns

• Precision, in PPM, of the specified clock branch.

Note

• This function is only for internal usage.

• The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.

CMU_DPLLLock#

bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef * init)

Lock the DPLL to a given frequency.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note

• This function does not check if the given N & M values will actually produce the desired target frequency.
  N & M limitations:
  300 < N <= 4095
  0 <= M <= 4095
  Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to calling this function to avoid over-clocking.

HFCLKLE prescaler is automatically modified before updating HFRCO based on the maximum HFLE frequency allowed.

Returns

• Returns false on invalid target frequency or DPLL locking error.

CMU_FreezeEnable#

void CMU_FreezeEnable (bool enable)

CMU low frequency register synchronization freeze control.

Some CMU registers require synchronization into the low-frequency (LF) domain. The freeze feature allows for several such registers to be modified before passing them to the LF domain simultaneously (which takes place when the freeze mode is disabled).

Another use case for this feature is using an API (such as the CMU API) for modifying several bit fields consecutively in the same register. If freeze mode is enabled during this sequence, stalling can be avoided.

Note

• When enabling freeze mode, this function will wait for all current ongoing CMU synchronization to LF domain to complete (normally synchronization will not be in progress.) However, for this reason, when using freeze mode, modifications of registers requiring LF synchronization should be done within one freeze enable/disable block to avoid unnecessary stalling.

CMU_HFRCOBandGet#

CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet (void )

Get the current HFRCO frequency.

Returns

• HFRCO frequency.

CMU_HFRCOBandSet#

void CMU_HFRCOBandSet (CMU_HFRCOFreq_TypeDef setFreq)

Set the HFRCO calibration for the selected target frequency.

Note

• HFCLKLE prescaler is automatically modified based on the maximum HFLE frequency allowed.

CMU_HFXOAutostartEnable#

void CMU_HFXOAutostartEnable (uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)

Enable or disable HFXO autostart.

CMU_HFXOInit#

void CMU_HFXOInit (const CMU_HFXOInit_TypeDef * hfxoInit)

Set HFXO control registers.

Note

• HFXO configuration should be obtained from a configuration tool, app note, or crystal data sheet. This function disables the HFXO to ensure a valid state before update.

CMU_LCDClkFDIVGet#

uint32_t CMU_LCDClkFDIVGet (void )

Get the LCD framerate divisor (FDIV) setting.

Returns

• The LCD framerate divisor.

CMU_LCDClkFDIVSet#

void CMU_LCDClkFDIVSet (uint32_t div)

Set the LCD framerate divisor (FDIV) setting.

Note

• The FDIV field (CMU LCDCTRL register) should only be modified while the LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function will NOT modify FDIV if the LCD module clock is enabled. See CMU_ClockEnable() for disabling/enabling LCD clock.

CMU_LFXOInit#

void CMU_LFXOInit (const CMU_LFXOInit_TypeDef * lfxoInit)

Set LFXO control registers.

Note

• LFXO configuration should be obtained from a configuration tool, app note, or crystal data sheet. This function disables the LFXO when necessary to ensure a valid state before update.

CMU_LFXOPrecisionSet#

void CMU_LFXOPrecisionSet (uint16_t precision)

Sets LFXO's crystal precision, in PPM.

Note

• LFXO precision should be obtained from a crystal datasheet.

CMU_LFXOPrecisionGet#

uint16_t CMU_LFXOPrecisionGet (void )

Gets LFXO's crystal precision, in PPM.

CMU_HFXOPrecisionSet#

void CMU_HFXOPrecisionSet (uint16_t precision)

Sets HFXO's crystal precision, in PPM.

Note

• HFXO precision should be obtained from a crystal datasheet.

CMU_HFXOPrecisionGet#

uint16_t CMU_HFXOPrecisionGet (void )

Gets HFXO's crystal precision, in PPM.

CMU_OscillatorEnable#

void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

Note

• WARNING: When this function is called to disable either cmuOsc_LFXO or cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register are reset to the reset value. In other words, if external clock sources are selected in either LFXOMODE or HFXOMODE fields, the configuration will be cleared and needs to be reconfigured if needed later.

CMU_OscillatorTuningGet#

uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)

Get the oscillator frequency tuning setting.

Returns

• The oscillator frequency tuning setting in use.

CMU_OscillatorTuningSet#

void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

Note

• Oscillator tuning is done during production and the tuning value is automatically loaded after reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.

CMU_OscillatorTuningWait#

bool CMU_OscillatorTuningWait (CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)

Wait for the oscillator tuning optimization.

Returns

• Returns false on invalid parameters or oscillator error status.

CMU_OscillatorTuningOptimize#

bool CMU_OscillatorTuningOptimize (CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)

Start and optionally wait for the oscillator tuning optimization.

Returns

• Returns false on invalid parameters or oscillator error status.

CMU_PCNTClockExternalSet#

void CMU_PCNTClockExternalSet (unsigned int instance, bool external)

Select the PCNTn clock.

CMU_PCNTClockExternalGet#

bool CMU_PCNTClockExternalGet (unsigned int instance)

Determine if the currently selected PCNTn clock used is external or LFBCLK.

Returns

• • true - selected clock is external clock.

  • false - selected clock is LFBCLK.

CMU_UpdateWaitStates#

void CMU_UpdateWaitStates (uint32_t freq, int vscale)

Configure various wait states to switch to a certain frequency and a certain voltage scale.

This function will set up the necessary flash, bus, and RAM wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

• 0 = 1.2 V (VSCALE2)

• 2 = 1.0 V (VSCALE0)

CMU_CalibrateCont#

void CMU_CalibrateCont (bool enable)

Configure continuous calibration mode.

CMU_CalibrateStart#

void CMU_CalibrateStart (void )

Start calibration.

Note

• This call is usually invoked after CMU_CalibrateConfig() and possibly CMU_CalibrateCont().

CMU_CalibrateStop#

void CMU_CalibrateStop (void )

Stop the calibration counters.

CMU_DivToLog2#

uint32_t CMU_DivToLog2 (CMU_ClkDiv_TypeDef div)

Convert divider to logarithmic value.

It only works for even numbers equal to 2^n.

Returns

• Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.

CMU_DPLLUnlock#

void CMU_DPLLUnlock (void )

Unlock DPLL.

Note

• HFRCO is not turned off.

CMU_IntClear#

void CMU_IntClear (uint32_t flags)

Clear one or more pending CMU interrupts.

CMU_IntDisable#

void CMU_IntDisable (uint32_t flags)

Disable one or more CMU interrupts.

CMU_IntEnable#

void CMU_IntEnable (uint32_t flags)

Enable one or more CMU interrupts.

Note

• Depending on use case, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if the pending interrupt should be ignored.

CMU_IntGet#

uint32_t CMU_IntGet (void )

Get pending CMU interrupts.

Returns

• CMU interrupt sources pending.

CMU_IntGetEnabled#

uint32_t CMU_IntGetEnabled (void )

Get enabled and pending CMU interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note

• This function does not clear event bits.

Returns

• Pending and enabled CMU interrupt sources. The return value is the bitwise AND of

  • the enabled interrupt sources in CMU_IEN and

  • the pending interrupt flags CMU_IF

CMU_IntSet#

void CMU_IntSet (uint32_t flags)

Set one or more pending CMU interrupts.

CMU_Lock#

void CMU_Lock (void )

Lock the CMU to protect some of its registers against unintended modification.

See the reference manual for CMU registers that will be locked.

Note

• If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.

CMU_Unlock#

void CMU_Unlock (void )

Unlock the CMU so that writing to locked registers again is possible.

CMU_PrescToLog2#

uint32_t CMU_PrescToLog2 (uint32_t presc)

Convert prescaler divider to a logarithmic value.

It only works for even numbers equal to 2^n.

Returns

• Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.

auxClkGet#

static uint32_t auxClkGet (void )

Get the AUX clock frequency.

Used by MSC flash programming and LESENSE, by default also as a debug clock.

Returns

• AUX Frequency in Hz.

hfSrcClkGet#

static uint32_t hfSrcClkGet (void )

Get the HFSRCCLK frequency.

Returns

• HFSRCCLK Frequency in Hz.

dbgClkGet#

static uint32_t dbgClkGet (void )

Get the Debug Trace clock frequency.

Returns

• Debug Trace frequency in Hz.

adcAsyncClkGet#

static uint32_t adcAsyncClkGet (uint32_t adc)

Get the ADC n asynchronous clock frequency.

Returns

• ADC n asynchronous frequency in Hz.

flashWaitStateControl#

static void flashWaitStateControl (uint32_t coreFreq, int vscale)

Configure flash access wait states to support the given core clock frequency.

flashWaitStateMax#

static void flashWaitStateMax (void )

Configure flash access wait states to the most conservative setting for this target.

Retain SCBTP (Suppressed Conditional Branch Target Prefetch) setting.

getRegIshUpperVal#

static uint32_t getRegIshUpperVal (uint32_t steadyStateRegIsh)

Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH.

getHfxoTuningMode#

uint32_t getHfxoTuningMode (void )

Get the HFXO tuning mode.

Returns

• The current HFXO tuning mode from the HFXOCTRL register.

setHfxoTuningMode#

void setHfxoTuningMode (uint32_t mode)

Set the HFXO tuning mode.

lfClkGet#

static uint32_t lfClkGet (CMU_Clock_TypeDef lfClkBranch)

Get the LFnCLK frequency based on the current configuration.

Returns

• The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is returned.

syncReg#

void syncReg (uint32_t mask)

Wait for an ongoing sync of register(s) to low-frequency domain to complete.

hfperClkSafePrescaler#

static void hfperClkSafePrescaler (void )

Set HFPER clock tree prescalers to safe values.

Note

• This function applies to EFM32GG11B. There are 3 HFPER clock trees with these frequency limits: HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode.

hfperClkOptimizedPrescaler#

static void hfperClkOptimizedPrescaler (void )

Set HFPER clock tree prescalers to give highest possible clock node frequency while still beeing within spec.

Note

• This function applies to EFM32GG11B. There are 3 HFPER clock trees with these frequency limits: HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode.

CMU_AUXHFRCODevinfoGet#

static uint32_t CMU_AUXHFRCODevinfoGet (CMU_AUXHFRCOFreq_TypeDef freq)

Get the AUXHFRCO frequency calibration word in DEVINFO.

Returns

• AUXHFRCO calibration word for a given frequency.

CMU_HFRCODevinfoGet#

static uint32_t CMU_HFRCODevinfoGet (CMU_HFRCOFreq_TypeDef freq)

Get the HFRCO frequency calibration word in DEVINFO.

Returns

• HFRCO calibration word for a given frequency.

CMU_CLOCK_SELECT_SET#

#define CMU_CLOCK_SELECT_SET

(clock, sel)

Macro to set clock sources in the clock tree.

cmuClkDiv_1#

#define cmuClkDiv_1

1

Clock divisors.

These values are valid for prescalers. Divide clock by 1.

cmuClkDiv_2#

#define cmuClkDiv_2

2

Divide clock by 2.

cmuClkDiv_4#

#define cmuClkDiv_4

4

Divide clock by 4.

cmuClkDiv_8#

#define cmuClkDiv_8

8

Divide clock by 8.

cmuClkDiv_16#

#define cmuClkDiv_16

16

Divide clock by 16.

cmuClkDiv_32#

#define cmuClkDiv_32

32

Divide clock by 32.

cmuClkDiv_64#

#define cmuClkDiv_64

64

Divide clock by 64.

cmuClkDiv_128#

#define cmuClkDiv_128

128

Divide clock by 128.

cmuClkDiv_256#

#define cmuClkDiv_256

256

Divide clock by 256.

cmuClkDiv_512#

#define cmuClkDiv_512

512

Divide clock by 512.

cmuClkDiv_1024#

#define cmuClkDiv_1024

1024

Divide clock by 1024.

cmuClkDiv_2048#

#define cmuClkDiv_2048

2048

Divide clock by 2048.

cmuClkDiv_4096#

#define cmuClkDiv_4096

4096

Divide clock by 4096.

cmuClkDiv_8192#

#define cmuClkDiv_8192

8192

Divide clock by 8192.

cmuClkDiv_16384#

#define cmuClkDiv_16384

16384

Divide clock by 16384.

cmuClkDiv_32768#

#define cmuClkDiv_32768

32768

Divide clock by 32768.

CMU_HFRCO_MIN#

#define CMU_HFRCO_MIN

cmuHFRCOFreq_1M0Hz

HFRCO minimum frequency.

CMU_HFRCO_MAX#

#define CMU_HFRCO_MAX

cmuHFRCOFreq_38M0Hz

HFRCO maximum frequency.

CMU_AUXHFRCO_MIN#

#define CMU_AUXHFRCO_MIN

cmuAUXHFRCOFreq_1M0Hz

AUXHFRCO minimum frequency.

CMU_AUXHFRCO_MAX#

#define CMU_AUXHFRCO_MAX

cmuAUXHFRCOFreq_38M0Hz

AUXHFRCO maximum frequency.

CMU_LFXOINIT_DEFAULT#

#define CMU_LFXOINIT_DEFAULT

Default LFXO initialization values.

CMU_LFXOINIT_EXTERNAL_CLOCK#

#define CMU_LFXOINIT_EXTERNAL_CLOCK

Default LFXO initialization for external clock.

CMU_HFXOINIT_DEFAULT#

#define CMU_HFXOINIT_DEFAULT

Default HFXO initialization values for Platform 2 devices, which contain a separate HFXOCTRL register.

CMU_HFXOINIT_EXTERNAL_CLOCK#

#define CMU_HFXOINIT_EXTERNAL_CLOCK

Init of HFXO with external clock.

CMU_DPLL_LFXO_TO_40MHZ#

#define CMU_DPLL_LFXO_TO_40MHZ

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.