VDAC initialization structure, common for both channels.
Public Attributes#
Selects between main and alternate output path calibration values.
Selects clock from asynchronous or synchronous (with respect to peripheral clock) source.
Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.
Channel refresh period.
Prescaler for VDAC clock.
Reference voltage to use.
Enable/disable reset of prescaler on CH 0 start.
Enable/disable output enable control by CH1 PRS signal.
Enable/disable sine mode.
Select if single ended or differential output mode.
Public Attribute Documentation#
mainCalibration#
bool VDAC_Init_TypeDef::mainCalibration
Selects between main and alternate output path calibration values.
163 of file platform/emlib/inc/em_vdac.hasyncClockMode#
bool VDAC_Init_TypeDef::asyncClockMode
Selects clock from asynchronous or synchronous (with respect to peripheral clock) source.
167 of file platform/emlib/inc/em_vdac.hwarmupKeepOn#
bool VDAC_Init_TypeDef::warmupKeepOn
Warm-up mode, keep VDAC on (in idle) - or shutdown between conversions.
170 of file platform/emlib/inc/em_vdac.hrefresh#
VDAC_Refresh_TypeDef VDAC_Init_TypeDef::refresh
Channel refresh period.
173 of file platform/emlib/inc/em_vdac.hprescaler#
uint32_t VDAC_Init_TypeDef::prescaler
Prescaler for VDAC clock.
Clock is source clock divided by prescaler+1.
176 of file platform/emlib/inc/em_vdac.hreference#
VDAC_Ref_TypeDef VDAC_Init_TypeDef::reference
Reference voltage to use.
179 of file platform/emlib/inc/em_vdac.hch0ResetPre#
bool VDAC_Init_TypeDef::ch0ResetPre
Enable/disable reset of prescaler on CH 0 start.
182 of file platform/emlib/inc/em_vdac.houtEnablePRS#
bool VDAC_Init_TypeDef::outEnablePRS
Enable/disable output enable control by CH1 PRS signal.
185 of file platform/emlib/inc/em_vdac.hsineEnable#
bool VDAC_Init_TypeDef::sineEnable
Enable/disable sine mode.
188 of file platform/emlib/inc/em_vdac.hdiff#
bool VDAC_Init_TypeDef::diff
Select if single ended or differential output mode.
191 of file platform/emlib/inc/em_vdac.h