LDMA - Linked DMA

Description

Linked Direct Memory Access (LDMA) Peripheral API.

LDMA API functions provide full support for the LDMA peripheral.

LDMA supports these DMA transfer types:

  • Memory to memory.
  • Memory to peripheral.
  • Peripheral to memory.
  • Peripheral to peripheral.
  • Constant value to memory.

LDMA supports linked lists of DMA descriptors allowing:

  • Circular and ping-pong buffer transfers.
  • Scatter-gather transfers.
  • Looped transfers.

LDMA has some advanced features:

  • Intra-channel synchronization (SYNC), allowing hardware events to pause and restart a DMA sequence.
  • Immediate-write (WRI), allowing DMA to write a constant anywhere in the memory map.
  • Complex flow control allowing if-else constructs.

Basic understanding of LDMA controller is assumed. Please refer to the reference manual for further details. The LDMA examples described in the reference manual are particularly helpful in understanding LDMA operations.

In order to use the DMA controller, the initialization function LDMA_Init() must have been executed once (normally during system initialization).

DMA transfers are initiated by a call to LDMA_StartTransfer(), transfer properties are controlled by the contents of LDMA_TransferCfg_t and LDMA_Descriptor_t structure parameters. The LDMA_Descriptor_t structure parameter may be a pointer to an array of descriptors, descriptors in array should be linked together as needed.

Transfer and descriptor initialization macros are provided for the most common transfer types. Due to the flexibility of LDMA peripheral, only a small subset of all possible initializer macros are provided, users should create new ones when needed.

Examples of LDMA usage:

A simple memory to memory transfer:

/* A single transfer of 4 half words. */
static const LDMA_TransferCfg_t transferCfg = LDMA_TRANSFER_CFG_MEMORY();
static const LDMA_Descriptor_t desc = LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dst, 4);
void ldmaTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the memory transfer */
LDMA_StartTransfer(0, &transferCfg, &desc);
}


A linked list of three memory to memory transfers:

/* A transfer consisting of 3 descriptors linked together and each descriptor
* transfers 4 words from the source to the destination. */
static const LDMA_TransferCfg_t transferCfg1 = LDMA_TRANSFER_CFG_MEMORY();
static const LDMA_Descriptor_t descList[] =
{
LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dst, 4, 1),
LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src + 4, dst + 4, 4, 1),
LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src + 8, dst + 8, 4)
};
void ldmaLinkedTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the linked memory transfer */
LDMA_StartTransfer(0, &transferCfg1, &descList[0]);
}


DMA from serial port peripheral to memory:

#if !defined(USART1) && defined(USART0)
/* The LDMA transfer should be triggered by the USART0 RX data available signal. */
static const LDMA_TransferCfg_t usart0RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_USART0_RXDATAV);
/* Transfer 4 bytes from the USART0 RX FIFO to memory. */
static const LDMA_Descriptor_t usart0RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(&USART0->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the USART0
* peripheral RXDATAV signal. */
LDMA_StartTransfer(0, &usart0RxTransfer, &usart0RxDesc);
}
#elif defined(USART1)
/* The LDMA transfer should be triggered by the USART1 RX data available signal. */
static const LDMA_TransferCfg_t usart1RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_USART1_RXDATAV);
/* Transfer 4 bytes from the USART1 RX FIFO to memory. */
static const LDMA_Descriptor_t usart1RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(&USART1->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the USART1
* peripheral RXDATAV signal. */
LDMA_StartTransfer(0, &usart1RxTransfer, &usart1RxDesc);
}
#elif defined(EUSART0)
/* The LDMA transfer should be triggered by the EUSART0 RX data available signal. */
static const LDMA_TransferCfg_t eusart0RxTransfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_EUSART0_RXFL);
/* Transfer 4 bytes from the EUSART0 RX FIFO to memory. */
static const LDMA_Descriptor_t eusart0RxDesc =
LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(&EUSART0->RXDATA, // Peripheral address
dst, // Destination (SRAM)
4); // Number of byte transfers
void ldmaPeripheralTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the EUSART0
* peripheral RXFL signal. */
LDMA_StartTransfer(0, &eusart0RxTransfer, &eusart0RxDesc);
}
#endif


Ping-pong DMA from serial port peripheral to memory:

#if !defined(USART1) && defined(USART0)
/* Two buffers used in the ping-pong transfer from USART0. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the USART0 RX data available signal. */
static const LDMA_TransferCfg_t usart0Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_USART0_RXDATAV);
/* Both descriptors transfer 5 bytes from the USART0 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&USART0->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&USART0->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the USART0
* peripheral RXDATAV signal. */
LDMA_StartTransfer(0, &usart0Transfer, &rxLoop[0]);
}
#elif defined(USART1)
/* Two buffers used in the ping-pong transfer from USART1. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the USART1 RX data available signal. */
static const LDMA_TransferCfg_t usart1Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_USART1_RXDATAV);
/* Both descriptors transfer 5 bytes from the USART1 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&USART1->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&USART1->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the USART1
* peripheral RXDATAV signal. */
LDMA_StartTransfer(0, &usart1Transfer, &rxLoop[0]);
}
#elif defined(EUSART0)
/* Two buffers used in the ping-pong transfer from EUSART0. */
static volatile uint8_t buffer0[5];
static volatile uint8_t buffer1[5];
/* The LDMA transfer should be triggered by the EUSART0 RX data available signal. */
static const LDMA_TransferCfg_t eusart0Transfer =
LDMA_TRANSFER_CFG_PERIPHERAL(ldmaPeripheralSignal_EUSART0_RXFL);
/* Both descriptors transfer 5 bytes from the EUSART0 rx data register into
* one of the buffers. Note that the first descriptor uses a relative address
* of 1 to link to the next descriptor, while the last descriptor uses a
* relative address of -1 to link to the first descriptor. */
static const LDMA_Descriptor_t rxLoop[] =
{
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&EUSART0->RXDATA, buffer0, 5, 1),
LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(&EUSART0->RXDATA, buffer1, 5, -1)
};
void ldmaPingPongTransfer(void)
{
/* Initialize the LDMA with default values. */
LDMA_Init_t init = LDMA_INIT_DEFAULT;
LDMA_Init(&init);
/* Start the peripheral transfer which is triggered by the EUSART0
* peripheral RXFL signal. */
LDMA_StartTransfer(0, &eusart0Transfer, &rxLoop[0]);
}
#endif
Note
LDMA module does not implement LDMA interrupt handler. A template for an LDMA IRQ handler is included here as an example.
/* Template for an LDMA IRQ handler. */
void LDMA_IRQHandler(void)
{
uint32_t ch;
/* Get all pending and enabled interrupts. */
uint32_t pending = LDMA_IntGetEnabled();
/* Loop here on an LDMA error to enable debugging. */
while (pending & LDMA_IF_ERROR) {
}
/* Iterate over all LDMA channels. */
for (ch = 0; ch < DMA_CHAN_COUNT; ch++) {
uint32_t mask = 0x1 << ch;
if (pending & mask) {
/* Clear interrupt flag. */
#if defined (LDMA_HAS_SET_CLEAR)
LDMA->IF_CLR = mask;
#else
LDMA->IFC = mask;
#endif
/* Do more stuff here, execute callbacks etc. */
}
}
}

Data Structures

union  LDMA_Descriptor_t
 DMA descriptor.
 
struct  LDMA_Init_t
 LDMA initialization configuration structure.
 
struct  LDMA_TransferCfg_t
 DMA transfer configuration structure.
 

Functions

void LDMA_DeInit (void)
 De-initialize the LDMA controller.
 
void LDMA_EnableChannelRequest (int ch, bool enable)
 Enable or disable an LDMA channel request.
 
void LDMA_Init (const LDMA_Init_t *init)
 Initialize the LDMA controller.
 
void LDMA_StartTransfer (int ch, const LDMA_TransferCfg_t *transfer, const LDMA_Descriptor_t *descriptor)
 Start a DMA transfer.
 
void LDMA_StopTransfer (int ch)
 Stop a DMA transfer.
 
bool LDMA_TransferDone (int ch)
 Check if a DMA transfer has completed.
 
uint32_t LDMA_TransferRemainingCount (int ch)
 Get the number of items remaining in a transfer.
 
bool LDMA_ChannelEnabled (int ch)
 Check if a certain channel is enabled.
 
void LDMA_IntClear (uint32_t flags)
 Clear one or more pending LDMA interrupts.
 
void LDMA_IntDisable (uint32_t flags)
 Disable one or more LDMA interrupts.
 
void LDMA_IntEnable (uint32_t flags)
 Enable one or more LDMA interrupts.
 
uint32_t LDMA_IntGet (void)
 Get pending LDMA interrupt flags.
 
uint32_t LDMA_IntGetEnabled (void)
 Get enabled and pending LDMA interrupt flags.
 
void LDMA_IntSet (uint32_t flags)
 Set one or more pending LDMA interrupts.
 

Macros

#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD   4
 Size in words of a non-extended DMA descriptor.
 
#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD   7
 Size in words of an extended DMA descriptor.
 
#define LDMA_INIT_DEFAULT
 Default DMA initialization structure.
 
#define LDMA_TRANSFER_CFG_MEMORY()
 Generic DMA transfer configuration for memory to memory transfers.
 
#define LDMA_TRANSFER_CFG_MEMORY_LOOP(loopCnt)
 Generic DMA transfer configuration for looped memory to memory transfers.
 
#define LDMA_TRANSFER_CFG_PERIPHERAL(signal)
 Generic DMA transfer configuration for memory to/from peripheral transfers.
 
#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP(signal, loopCnt)
 Generic DMA transfer configuration for looped memory to/from peripheral transfers.
 
#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD(src, dest, count)
 DMA descriptor initializer for single memory to memory word transfer.
 
#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF(src, dest, count)
 DMA descriptor initializer for single memory to memory half-word transfer.
 
#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE(src, dest, count)
 DMA descriptor initializer for single memory to memory byte transfer.
 
#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD(src, dest, count)
 DMA descriptor initializer for linked memory to memory word transfer.
 
#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF(src, dest, count)
 DMA descriptor initializer for linked memory to memory half-word transfer.
 
#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE(src, dest, count)
 DMA descriptor initializer for linked memory to memory byte transfer.
 
#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD(src, dest, count, linkjmp)
 DMA descriptor initializer for linked memory to memory word transfer.
 
#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF(src, dest, count, linkjmp)
 DMA descriptor initializer for linked memory to memory half-word transfer.
 
#define LDMA_DESCRIPTOR_LINKREL_M2M_BYTE(src, dest, count, linkjmp)
 DMA descriptor initializer for linked memory to memory byte transfer.
 
#define LDMA_DESCRIPTOR_SINGLE_P2M_BYTE(src, dest, count)
 DMA descriptor initializer for byte transfers from a peripheral to memory.
 
#define LDMA_DESCRIPTOR_SINGLE_P2P_BYTE(src, dest, count)
 DMA descriptor initializer for byte transfers from a peripheral to a peripheral.
 
#define LDMA_DESCRIPTOR_SINGLE_M2P_BYTE(src, dest, count)
 DMA descriptor initializer for byte transfers from memory to a peripheral.
 
#define LDMA_DESCRIPTOR_LINKREL_P2M_BYTE(src, dest, count, linkjmp)
 DMA descriptor initializer for byte transfers from a peripheral to memory.
 
#define LDMA_DESCRIPTOR_LINKREL_P2M_WORD(src, dest, count, linkjmp)
 DMA descriptor initializer for word transfers from a peripheral to memory.
 
#define LDMA_DESCRIPTOR_LINKREL_M2P_BYTE(src, dest, count, linkjmp)
 DMA descriptor initializer for byte transfers from memory to a peripheral.
 
#define LDMA_DESCRIPTOR_SINGLE_WRITE(value, address)
 DMA descriptor initializer for Immediate WRITE transfer.
 
#define LDMA_DESCRIPTOR_LINKABS_WRITE(value, address)
 DMA descriptor initializer for Immediate WRITE transfer.
 
#define LDMA_DESCRIPTOR_LINKREL_WRITE(value, address, linkjmp)
 DMA descriptor initializer for Immediate WRITE transfer.
 
#define LDMA_DESCRIPTOR_SINGLE_SYNC(set, clr, matchValue, matchEnable)
 DMA descriptor initializer for SYNC transfer.
 
#define LDMA_DESCRIPTOR_LINKABS_SYNC(set, clr, matchValue, matchEnable)
 DMA descriptor initializer for SYNC transfer.
 
#define LDMA_DESCRIPTOR_LINKREL_SYNC(set, clr, matchValue, matchEnable, linkjmp)
 DMA descriptor initializer for SYNC transfer.
 

Enumerations

enum  LDMA_CtrlBlockSize_t {
  ldmaCtrlBlockSizeUnit1 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1,
  ldmaCtrlBlockSizeUnit2 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT2,
  ldmaCtrlBlockSizeUnit3 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT3,
  ldmaCtrlBlockSizeUnit4 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT4,
  ldmaCtrlBlockSizeUnit6 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT6,
  ldmaCtrlBlockSizeUnit8 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT8,
  ldmaCtrlBlockSizeUnit16 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT16,
  ldmaCtrlBlockSizeUnit32 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT32,
  ldmaCtrlBlockSizeUnit64 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT64,
  ldmaCtrlBlockSizeUnit128 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT128,
  ldmaCtrlBlockSizeUnit256 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT256,
  ldmaCtrlBlockSizeUnit512 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT512,
  ldmaCtrlBlockSizeUnit1024 = _LDMA_CH_CTRL_BLOCKSIZE_UNIT1024,
  ldmaCtrlBlockSizeAll = _LDMA_CH_CTRL_BLOCKSIZE_ALL
}
 Controls the number of unit data transfers per arbitration cycle, providing a means to balance DMA channels' load on the controller.
 
enum  LDMA_CtrlStructType_t {
  ldmaCtrlStructTypeXfer = _LDMA_CH_CTRL_STRUCTTYPE_TRANSFER,
  ldmaCtrlStructTypeSync = _LDMA_CH_CTRL_STRUCTTYPE_SYNCHRONIZE,
  ldmaCtrlStructTypeWrite = _LDMA_CH_CTRL_STRUCTTYPE_WRITE
}
 DMA structure type.
 
enum  LDMA_CtrlReqMode_t {
  ldmaCtrlReqModeBlock = _LDMA_CH_CTRL_REQMODE_BLOCK,
  ldmaCtrlReqModeAll = _LDMA_CH_CTRL_REQMODE_ALL
}
 DMA transfer block or cycle selector.
 
enum  LDMA_CtrlSrcInc_t {
  ldmaCtrlSrcIncOne = _LDMA_CH_CTRL_SRCINC_ONE,
  ldmaCtrlSrcIncTwo = _LDMA_CH_CTRL_SRCINC_TWO,
  ldmaCtrlSrcIncFour = _LDMA_CH_CTRL_SRCINC_FOUR,
  ldmaCtrlSrcIncNone = _LDMA_CH_CTRL_SRCINC_NONE
}
 Source address increment unit size.
 
enum  LDMA_CtrlSize_t {
  ldmaCtrlSizeByte = _LDMA_CH_CTRL_SIZE_BYTE,
  ldmaCtrlSizeHalf = _LDMA_CH_CTRL_SIZE_HALFWORD,
  ldmaCtrlSizeWord = _LDMA_CH_CTRL_SIZE_WORD
}
 DMA transfer unit size.
 
enum  LDMA_CtrlDstInc_t {
  ldmaCtrlDstIncOne = _LDMA_CH_CTRL_DSTINC_ONE,
  ldmaCtrlDstIncTwo = _LDMA_CH_CTRL_DSTINC_TWO,
  ldmaCtrlDstIncFour = _LDMA_CH_CTRL_DSTINC_FOUR,
  ldmaCtrlDstIncNone = _LDMA_CH_CTRL_DSTINC_NONE
}
 Destination address increment unit size.
 
enum  LDMA_CtrlSrcAddrMode_t {
  ldmaCtrlSrcAddrModeAbs = _LDMA_CH_CTRL_SRCMODE_ABSOLUTE,
  ldmaCtrlSrcAddrModeRel = _LDMA_CH_CTRL_SRCMODE_RELATIVE
}
 Source addressing mode.
 
enum  LDMA_CtrlDstAddrMode_t {
  ldmaCtrlDstAddrModeAbs = _LDMA_CH_CTRL_DSTMODE_ABSOLUTE,
  ldmaCtrlDstAddrModeRel = _LDMA_CH_CTRL_DSTMODE_RELATIVE
}
 Destination addressing mode.
 
enum  LDMA_LinkMode_t {
  ldmaLinkModeAbs = _LDMA_CH_LINK_LINKMODE_ABSOLUTE,
  ldmaLinkModeRel = _LDMA_CH_LINK_LINKMODE_RELATIVE
}
 DMA link load address mode.
 
enum  LDMA_CfgArbSlots_t {
  ldmaCfgArbSlotsAs1 = _LDMA_CH_CFG_ARBSLOTS_ONE,
  ldmaCfgArbSlotsAs2 = _LDMA_CH_CFG_ARBSLOTS_TWO,
  ldmaCfgArbSlotsAs4 = _LDMA_CH_CFG_ARBSLOTS_FOUR,
  ldmaCfgArbSlotsAs8 = _LDMA_CH_CFG_ARBSLOTS_EIGHT
}
 Insert extra arbitration slots to increase channel arbitration priority.
 
enum  LDMA_CfgSrcIncSign_t {
  ldmaCfgSrcIncSignPos = _LDMA_CH_CFG_SRCINCSIGN_POSITIVE,
  ldmaCfgSrcIncSignNeg = _LDMA_CH_CFG_SRCINCSIGN_NEGATIVE
}
 Source address increment sign.
 
enum  LDMA_CfgDstIncSign_t {
  ldmaCfgDstIncSignPos = _LDMA_CH_CFG_DSTINCSIGN_POSITIVE,
  ldmaCfgDstIncSignNeg = _LDMA_CH_CFG_DSTINCSIGN_NEGATIVE
}
 Destination address increment sign.
 
enum  LDMA_PeripheralSignal_t {
  ldmaPeripheralSignal_NONE = LDMA_CH_REQSEL_SOURCESEL_NONE,
  ldmaPeripheralSignal_ADC0_SCAN = LDMA_CH_REQSEL_SIGSEL_ADC0SCAN | LDMA_CH_REQSEL_SOURCESEL_ADC0,
  ldmaPeripheralSignal_ADC0_SINGLE = LDMA_CH_REQSEL_SIGSEL_ADC0SINGLE | LDMA_CH_REQSEL_SOURCESEL_ADC0,
  ldmaPeripheralSignal_CRYPTO0_DATA0RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
  ldmaPeripheralSignal_CRYPTO0_DATA0WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
  ldmaPeripheralSignal_CRYPTO0_DATA0XWR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA0XWR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
  ldmaPeripheralSignal_CRYPTO0_DATA1RD = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1RD | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
  ldmaPeripheralSignal_CRYPTO0_DATA1WR = LDMA_CH_REQSEL_SIGSEL_CRYPTO0DATA1WR | LDMA_CH_REQSEL_SOURCESEL_CRYPTO0,
  ldmaPeripheralSignal_CSEN_BSLN = LDMA_CH_REQSEL_SIGSEL_CSENBSLN | LDMA_CH_REQSEL_SOURCESEL_CSEN,
  ldmaPeripheralSignal_CSEN_DATA = LDMA_CH_REQSEL_SIGSEL_CSENDATA | LDMA_CH_REQSEL_SOURCESEL_CSEN,
  ldmaPeripheralSignal_I2C0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C0,
  ldmaPeripheralSignal_I2C0_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C0TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C0,
  ldmaPeripheralSignal_I2C1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_I2C1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_I2C1,
  ldmaPeripheralSignal_I2C1_TXBL = LDMA_CH_REQSEL_SIGSEL_I2C1TXBL | LDMA_CH_REQSEL_SOURCESEL_I2C1,
  ldmaPeripheralSignal_LESENSE_BUFDATAV = LDMA_CH_REQSEL_SIGSEL_LESENSEBUFDATAV | LDMA_CH_REQSEL_SOURCESEL_LESENSE,
  ldmaPeripheralSignal_LEUART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_LEUART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
  ldmaPeripheralSignal_LEUART0_TXBL = LDMA_CH_REQSEL_SIGSEL_LEUART0TXBL | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
  ldmaPeripheralSignal_LEUART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_LEUART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_LEUART0,
  ldmaPeripheralSignal_MSC_WDATA = LDMA_CH_REQSEL_SIGSEL_MSCWDATA | LDMA_CH_REQSEL_SOURCESEL_MSC,
  ldmaPeripheralSignal_PRS_REQ0 = LDMA_CH_REQSEL_SIGSEL_PRSREQ0 | LDMA_CH_REQSEL_SOURCESEL_PRS,
  ldmaPeripheralSignal_PRS_REQ1 = LDMA_CH_REQSEL_SIGSEL_PRSREQ1 | LDMA_CH_REQSEL_SOURCESEL_PRS,
  ldmaPeripheralSignal_TIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
  ldmaPeripheralSignal_TIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
  ldmaPeripheralSignal_TIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
  ldmaPeripheralSignal_TIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER0,
  ldmaPeripheralSignal_TIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
  ldmaPeripheralSignal_TIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
  ldmaPeripheralSignal_TIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
  ldmaPeripheralSignal_TIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_TIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
  ldmaPeripheralSignal_TIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_TIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_TIMER1,
  ldmaPeripheralSignal_UART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_UART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_UART0,
  ldmaPeripheralSignal_UART0_TXBL = LDMA_CH_REQSEL_SIGSEL_UART0TXBL | LDMA_CH_REQSEL_SOURCESEL_UART0,
  ldmaPeripheralSignal_UART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_UART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_UART0,
  ldmaPeripheralSignal_USART0_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART0RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART0,
  ldmaPeripheralSignal_USART0_TXBL = LDMA_CH_REQSEL_SIGSEL_USART0TXBL | LDMA_CH_REQSEL_SOURCESEL_USART0,
  ldmaPeripheralSignal_USART0_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART0TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART0,
  ldmaPeripheralSignal_USART1_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART1,
  ldmaPeripheralSignal_USART1_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
  ldmaPeripheralSignal_USART1_TXBL = LDMA_CH_REQSEL_SIGSEL_USART1TXBL | LDMA_CH_REQSEL_SOURCESEL_USART1,
  ldmaPeripheralSignal_USART1_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART1TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART1,
  ldmaPeripheralSignal_USART1_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART1TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART1,
  ldmaPeripheralSignal_USART2_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART2RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART2,
  ldmaPeripheralSignal_USART2_TXBL = LDMA_CH_REQSEL_SIGSEL_USART2TXBL | LDMA_CH_REQSEL_SOURCESEL_USART2,
  ldmaPeripheralSignal_USART2_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART2TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART2,
  ldmaPeripheralSignal_USART3_RXDATAV = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAV | LDMA_CH_REQSEL_SOURCESEL_USART3,
  ldmaPeripheralSignal_USART3_RXDATAVRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3RXDATAVRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
  ldmaPeripheralSignal_USART3_TXBL = LDMA_CH_REQSEL_SIGSEL_USART3TXBL | LDMA_CH_REQSEL_SOURCESEL_USART3,
  ldmaPeripheralSignal_USART3_TXBLRIGHT = LDMA_CH_REQSEL_SIGSEL_USART3TXBLRIGHT | LDMA_CH_REQSEL_SOURCESEL_USART3,
  ldmaPeripheralSignal_USART3_TXEMPTY = LDMA_CH_REQSEL_SIGSEL_USART3TXEMPTY | LDMA_CH_REQSEL_SOURCESEL_USART3,
  ldmaPeripheralSignal_VDAC0_CH0 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH0 | LDMA_CH_REQSEL_SOURCESEL_VDAC0,
  ldmaPeripheralSignal_VDAC0_CH1 = LDMA_CH_REQSEL_SIGSEL_VDAC0CH1 | LDMA_CH_REQSEL_SOURCESEL_VDAC0,
  ldmaPeripheralSignal_WTIMER0_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
  ldmaPeripheralSignal_WTIMER0_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
  ldmaPeripheralSignal_WTIMER0_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER0CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
  ldmaPeripheralSignal_WTIMER0_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER0UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER0,
  ldmaPeripheralSignal_WTIMER1_CC0 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC0 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
  ldmaPeripheralSignal_WTIMER1_CC1 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC1 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
  ldmaPeripheralSignal_WTIMER1_CC2 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC2 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
  ldmaPeripheralSignal_WTIMER1_CC3 = LDMA_CH_REQSEL_SIGSEL_WTIMER1CC3 | LDMA_CH_REQSEL_SOURCESEL_WTIMER1,
  ldmaPeripheralSignal_WTIMER1_UFOF = LDMA_CH_REQSEL_SIGSEL_WTIMER1UFOF | LDMA_CH_REQSEL_SOURCESEL_WTIMER1
}
 Peripherals that can trigger LDMA transfers.
 

Function Documentation

◆ LDMA_DeInit()

void LDMA_DeInit ( void  )

De-initialize the LDMA controller.

LDMA interrupts are disabled and the LDMA clock is stopped.

◆ LDMA_EnableChannelRequest()

void LDMA_EnableChannelRequest ( int  ch,
bool  enable 
)

Enable or disable an LDMA channel request.

Use this function to enable or disable an LDMA channel request. This will prevent the LDMA from proceeding after its current transaction if disabled.

Parameters
[in]chLDMA channel to enable or disable requests.
[in]enableIf 'true', the request will be enabled. If 'false', the request will be disabled.

◆ LDMA_Init()

void LDMA_Init ( const LDMA_Init_t *  init)

Initialize the LDMA controller.

This function will disable all the LDMA channels and enable the LDMA bus clock in the CMU. This function will also enable the LDMA IRQ in the NVIC and set the LDMA IRQ priority to a user-configurable priority. The LDMA interrupt priority is configured using the LDMA_Init_t structure.

Note
Since this function enables the LDMA IRQ, always add a custom LDMA_IRQHandler to the application to handle any interrupts from LDMA.
Parameters
[in]initA pointer to the initialization structure used to configure the LDMA.

◆ LDMA_StartTransfer()

void LDMA_StartTransfer ( int  ch,
const LDMA_TransferCfg_t *  transfer,
const LDMA_Descriptor_t *  descriptor 
)

Start a DMA transfer.

Parameters
[in]chA DMA channel.
[in]transferThe initialization structure used to configure the transfer.
[in]descriptorThe transfer descriptor, which can be an array of descriptors linked together. Each descriptor's fields stored in RAM will be loaded into the certain hardware registers at the proper time to perform the DMA transfer.

◆ LDMA_StopTransfer()

void LDMA_StopTransfer ( int  ch)

Stop a DMA transfer.

Note
The DMA will complete the current AHB burst transfer before stopping.
Parameters
[in]chA DMA channel to stop.

◆ LDMA_TransferDone()

bool LDMA_TransferDone ( int  ch)

Check if a DMA transfer has completed.

Parameters
[in]chA DMA channel to check.
Returns
True if transfer has completed, false if not.

◆ LDMA_TransferRemainingCount()

uint32_t LDMA_TransferRemainingCount ( int  ch)

Get the number of items remaining in a transfer.

Note
This function does not take into account that a DMA transfer with a chain of linked transfers might be ongoing. It will only check the count for the current transfer.
Parameters
[in]chThe channel number of the transfer to check.
Returns
A number of items remaining in the transfer.

◆ LDMA_ChannelEnabled()

bool LDMA_ChannelEnabled ( int  ch)
inline

Check if a certain channel is enabled.

Parameters
[in]chLDMA channel to check.
Returns
return true if the LDMA channel is enabled and false if the channel is not enabled.

◆ LDMA_IntClear()

void LDMA_IntClear ( uint32_t  flags)
inline

Clear one or more pending LDMA interrupts.

Parameters
[in]flagsPending LDMA interrupt sources to clear. Use one or more valid interrupt flags for the LDMA module. The flags are LDMA_IFC_ERROR and one done flag for each channel.

◆ LDMA_IntDisable()

void LDMA_IntDisable ( uint32_t  flags)
inline

Disable one or more LDMA interrupts.

Parameters
[in]flagsLDMA interrupt sources to disable. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR and one done flag for each channel.

◆ LDMA_IntEnable()

void LDMA_IntEnable ( uint32_t  flags)
inline

Enable one or more LDMA interrupts.

Note
Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using LDMA_IntClear() prior to enabling the interrupt.
Parameters
[in]flagsLDMA interrupt sources to enable. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IEN_ERROR and one done flag for each channel.

◆ LDMA_IntGet()

uint32_t LDMA_IntGet ( void  )
inline

Get pending LDMA interrupt flags.

Note
Event bits are not cleared by the use of this function.
Returns
LDMA interrupt sources pending. Returns one or more valid interrupt flags for LDMA module. The flags are LDMA_IF_ERROR and one flag for each LDMA channel.

◆ LDMA_IntGetEnabled()

uint32_t LDMA_IntGetEnabled ( void  )
inline

Get enabled and pending LDMA interrupt flags.

Useful for handling more interrupt sources in the same interrupt handler.

Note
Interrupt flags are not cleared by the use of this function.
Returns
Pending and enabled LDMA interrupt sources Return value is the bitwise AND of
  • the enabled interrupt sources in LDMA_IEN and
  • the pending interrupt flags LDMA_IF

◆ LDMA_IntSet()

void LDMA_IntSet ( uint32_t  flags)
inline

Set one or more pending LDMA interrupts.

Parameters
[in]flagsLDMA interrupt sources to set to pending. Use one or more valid interrupt flags for LDMA module. The flags are LDMA_IFS_ERROR and one done flag for each LDMA channel.

Macro Definition Documentation

◆ LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD

#define LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD   4

Size in words of a non-extended DMA descriptor.

◆ LDMA_DESCRIPTOR_EXTEND_SIZE_WORD

#define LDMA_DESCRIPTOR_EXTEND_SIZE_WORD   7

Size in words of an extended DMA descriptor.

◆ LDMA_INIT_DEFAULT

#define LDMA_INIT_DEFAULT
Value:
{ \
.ldmaInitCtrlNumFixed = _LDMA_CTRL_NUMFIXED_DEFAULT,/* Fixed priority arbitration.*/ \
.ldmaInitCtrlSyncPrsClrEn = 0, /* No PRS Synctrig clear enable*/ \
.ldmaInitCtrlSyncPrsSetEn = 0, /* No PRS Synctrig set enable. */ \
.ldmaInitIrqPriority = 3 /* IRQ priority level 3. */ \
}

Default DMA initialization structure.

◆ LDMA_TRANSFER_CFG_MEMORY

#define LDMA_TRANSFER_CFG_MEMORY ( )
Value:
{ \
0, 0, 0, 0, 0, \
false, false, ldmaCfgArbSlotsAs1, \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
}

Generic DMA transfer configuration for memory to memory transfers.

◆ LDMA_TRANSFER_CFG_MEMORY_LOOP

#define LDMA_TRANSFER_CFG_MEMORY_LOOP (   loopCnt)
Value:
{ \
0, 0, 0, 0, 0, \
false, false, ldmaCfgArbSlotsAs1, \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, \
loopCnt \
}

Generic DMA transfer configuration for looped memory to memory transfers.

◆ LDMA_TRANSFER_CFG_PERIPHERAL

#define LDMA_TRANSFER_CFG_PERIPHERAL (   signal)
Value:
{ \
signal, 0, 0, 0, 0, \
false, false, ldmaCfgArbSlotsAs1, \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, 0 \
}

Generic DMA transfer configuration for memory to/from peripheral transfers.

◆ LDMA_TRANSFER_CFG_PERIPHERAL_LOOP

#define LDMA_TRANSFER_CFG_PERIPHERAL_LOOP (   signal,
  loopCnt 
)
Value:
{ \
signal, 0, 0, 0, 0, \
false, false, ldmaCfgArbSlotsAs1, \
ldmaCfgSrcIncSignPos, ldmaCfgDstIncSignPos, loopCnt \
}

Generic DMA transfer configuration for looped memory to/from peripheral transfers.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_WORD

#define LDMA_DESCRIPTOR_SINGLE_M2M_WORD (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeWord, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory word transfer.

Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of words to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_HALF

#define LDMA_DESCRIPTOR_SINGLE_M2M_HALF (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeHalf, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory half-word transfer.

Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of half-words to transfer.

◆ LDMA_DESCRIPTOR_SINGLE_M2M_BYTE

#define LDMA_DESCRIPTOR_SINGLE_M2M_BYTE (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 1, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeByte, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = 0, \
.link = 0, \
.linkAddr = 0 \
} \
}

DMA descriptor initializer for single memory to memory byte transfer.

Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of bytes to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_WORD

#define LDMA_DESCRIPTOR_LINKABS_M2M_WORD (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeWord, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs, \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory word transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of words to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_HALF

#define LDMA_DESCRIPTOR_LINKABS_M2M_HALF (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeHalf, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs, \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory half-word transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of half-words to transfer.

◆ LDMA_DESCRIPTOR_LINKABS_M2M_BYTE

#define LDMA_DESCRIPTOR_LINKABS_M2M_BYTE (   src,
  dest,
  count 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeByte, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeAbs, \
.link = 1, \
.linkAddr = 0 /* Must be set runtime ! */ \
} \
}

DMA descriptor initializer for linked memory to memory byte transfer.

Link address must be an absolute address.

Note
The linkAddr member of the transfer descriptor is not initialized. linkAddr must be initialized by using the proper bits right-shift to get the correct bits from the absolute address. _LDMA_CH_LINK_LINKADDR_SHIFT should be used for that operation:
desc.linkAddr = ((int32_t)&next_desc) >> _LDMA_CH_LINK_LINKADDR_SHIFT;
The opposite bit shift (left) must be done if linkAddr is read.
Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of bytes to transfer.

◆ LDMA_DESCRIPTOR_LINKREL_M2M_WORD

#define LDMA_DESCRIPTOR_LINKREL_M2M_WORD (   src,
  dest,
  count,
  linkjmp 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockSizeUnit1, \
.doneIfs = 0, \
.reqMode = ldmaCtrlReqModeAll, \
.decLoopCnt = 0, \
.ignoreSrec = 0, \
.srcInc = ldmaCtrlSrcIncOne, \
.size = ldmaCtrlSizeWord, \
.dstInc = ldmaCtrlDstIncOne, \
.srcAddrMode = ldmaCtrlSrcAddrModeAbs, \
.dstAddrMode = ldmaCtrlDstAddrModeAbs, \
.srcAddr = (uint32_t)(src), \
.dstAddr = (uint32_t)(dest), \
.linkMode = ldmaLinkModeRel, \
.link = 1, \
.linkAddr = (linkjmp) * LDMA_DESCRIPTOR_NON_EXTEND_SIZE_WORD \
} \
}

DMA descriptor initializer for linked memory to memory word transfer.

Link address is a relative address.

Note
The linkAddr member of the transfer descriptor is initialized to 4 (regular descriptor) or 7 (extended descriptor), assuming that the next descriptor immediately follows this descriptor (in memory).
Parameters
[in]srcSource data address.
[in]destDestination data address.
[in]countNumber of words to transfer.
[in]linkjmpAddress of descriptor to link to, expressed as a signed number of descriptors from "here". 1=one descriptor forward in memory, 0=this descriptor, -1=one descriptor back in memory.

◆ LDMA_DESCRIPTOR_LINKREL_M2M_HALF

#define LDMA_DESCRIPTOR_LINKREL_M2M_HALF (   src,
  dest,
  count,
  linkjmp 
)
Value:
{ \
.xfer = \
{ \
.structType = ldmaCtrlStructTypeXfer, \
.structReq = 1, \
.xferCnt = (count) - 1, \
.byteSwap = 0, \
.blockSize = ldmaCtrlBlockS