EBI operation mode, data, and address limits.

Address Ready pin polarity, active high or low.

Address Latch Enable pin polarity, active high or low.

Write Enable pin polarity, active high or low.

Read Enable pin polarity, active high or low.

Chip Select pin polarity, active high or low.

Byte Lane pin polarity, active high or low.

Flag to enable or disable Byte Lane support.

Flag to enable or disable idle state insertion between transfers.

Flag to enable or disable Address Ready support.

Set to turn off 32 cycle timeout ability.

Mask of flags which selects address banks to configure EBI_BANK<0-3>.

Mask of flags which selects chip select lines to configure EBI_CS<0-3>.

Number of cycles address is held after Address Latch Enable is asserted.

Number of cycles address is driven onto the ADDRDAT bus before ALE is asserted.

Enable or disables half cycle duration of the ALE strobe in the last address setup cycle.

Number of cycles for address setup before REn is asserted.

Number of cycles REn is held active.

Number of cycles CSn is held active after REn is deasserted.

Enable or disable page mode reads.

Enables or disable prefetching from sequential addresses.

Enabled or disables half cycle duration of the REn signal in the last strobe cycle.

Number of cycles for address setup before WEn is asserted.

Number of cycles WEn is held active.

Number of cycles CSn is held active after WEn is deasserted.

Enable or disable the write buffer.

Enables or disables half cycle duration of the WEn signal in the last strobe cycle.

Lower address pin limit to enable.

High address pin limit to enable.

Flag, if EBI should be enabled after configuration.