CORE - Core Interrupt#

Introduction#

CORE interrupt API provides a simple and safe means to disable and enable interrupts to protect sections of code.

This is often referred to as "critical sections". This module provides support for three types of critical sections, each with different interrupt blocking capabilities.

CRITICAL section: Inside a critical section, all interrupts are disabled (except for fault handlers). The PRIMASK register is always used for interrupt disable/enable.
ATOMIC section: This type of section is configurable and the default method is to use PRIMASK. With BASEPRI configuration, interrupts with priority equal to or lower than a given configurable level are disabled. The interrupt disable priority level is defined at compile time. The BASEPRI register is not available for all architectures.
NVIC mask section: Disable NVIC (external interrupts) on an individual manner.

em_core also has an API for manipulating RAM-based interrupt vector tables.

Compile-time Configuration#

The following #defines are used to configure em_core:

// The interrupt priority level used inside ATOMIC sections.
#define CORE_ATOMIC_BASE_PRIORITY_LEVEL    3

// A method used for interrupt disable/enable within ATOMIC sections.
#define CORE_ATOMIC_METHOD                 CORE_ATOMIC_METHOD_PRIMASK

If the default values do not support your needs, they can be overridden by supplying -D compiler flags on the compiler command line or by collecting all macro redefinitions in a file named emlib_config.h and then supplying -DEMLIB_USER_CONFIG on a compiler command line.

Note

The default emlib configuration for ATOMIC section interrupt disable method is using PRIMASK, i.e., ATOMIC sections are implemented as CRITICAL sections.
Due to architectural limitations Cortex-M0+ devices do not support ATOMIC type critical sections using the BASEPRI register. On M0+ devices ATOMIC section helper macros are available but they are implemented as CRITICAL sections using PRIMASK register.

Macro API#

The primary em_core API is the macro API. Macro API will map to correct CORE functions according to the selected CORE_ATOMIC_METHOD and similar configurations (the full CORE API is of course also available). The most useful macros are as follows:

CORE_DECLARE_IRQ_STATE CORE_ENTER_ATOMIC()@n Used together to implement an ATOMIC section.

{
  CORE_DECLARE_IRQ_STATE;           // Storage for saving IRQ state prior to
                                    // atomic section entry.

  CORE_ENTER_ATOMIC();              // Enter atomic section.

  ...
  ... your code goes here ...
  ...

  CORE_EXIT_ATOMIC();               // Exit atomic section, IRQ state is restored.
}

@n A concatenation of all three macros above.

{
  CORE_ATOMIC_SECTION(
    ...
    ... your code goes here ...
    ...
  )
}

CORE_DECLARE_IRQ_STATE CORE_ENTER_CRITICAL()CORE_EXIT_CRITICAL()@n These macros implement CRITICAL sections in a similar fashion as described above for ATOMIC sections.

CORE_DECLARE_NVIC_STATE CORE_ENTER_NVIC()CORE_EXIT_NVIC()@n These macros implement NVIC mask sections in a similar fashion as described above for ATOMIC sections. See Examples for an example.

Refer to Macros or Macro Definition Documentation below for a full list of macros.

API reimplementation#

Most of the functions in the API are implemented as weak functions. This means that it is easy to reimplement when special needs arise. Shown below is a reimplementation of CRITICAL sections suitable if FreeRTOS OS is used:

CORE_irqState_t CORE_EnterCritical(void)
{
  vPortEnterCritical();
  return 0;
}

void CORE_ExitCritical(CORE_irqState_t irqState)
{
  (void)irqState;
  vPortExitCritical();
}

Also note that CORE_Enter/ExitCritical() are not implemented as inline functions. As a result, reimplementations will be possible even when original implementations are inside a linked library.

Some RTOSes must be notified on interrupt handler entry and exit. Macros CORE_INTERRUPT_ENTRY() and CORE_INTERRUPT_EXIT() are suitable placeholders for inserting such code. Insert these macros in all your interrupt handlers and then override the default macro implementations. This is an example if uC/OS is used:

// In emlib_config.h:

#define CORE_INTERRUPT_ENTRY()   OSIntEnter()
#define CORE_INTERRUPT_EXIT()    OSIntExit()

Interrupt vector tables#

When using RAM based interrupt vector tables it is the user's responsibility to allocate the table space correctly. The tables must be aligned as specified in the CPU reference manual.

@n Initialize a RAM based vector table by copying table entries from a source vector table to a target table. VTOR is set to the address of the target vector table.

CORE_GetNvicRamTableHandler()@n Use these functions to get or set the interrupt handler for a specific IRQn. They both use the interrupt vector table defined by the current VTOR register value.

Maximum Interrupt Disabled Time#

The maximum time spent (in cycles) in critical and atomic sections can be measured for performance and interrupt latency analysis. To enable the timings, use the SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING configuration option. When enabled, the functions CORE_get_max_time_critical_section()CORE_get_max_time_atomic_section() can be used to get the max timings since startup.

Examples#

Implement an NVIC critical section:

{
  CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask

  // Set mask bits for IRQs to block in the NVIC critical section.
  // In many cases, you can create the disable mask once upon application
  // startup and use the mask globally throughout the application lifetime.
  CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask);
  CORE_NvicMaskSetIRQ(VCMP_IRQn,    &mask);

  // Enter NVIC critical section with the disable mask
  CORE_NVIC_SECTION(&mask,
    ...
    ... your code goes here ...
    ...
  )
}

Porting from em_int#

Existing code using INT_Enable() and INT_Disable() must be ported to the em_core API. While em_int used, a global counter to store the interrupt state, em_core uses a local variable. Any usage of INT_Disable(), therefore, needs to be replaced with a declaration of the interrupt state variable before entering the critical section.

Since the state variable is in local scope, the critical section exit needs to occur within the scope of the variable. If multiple nested critical sections are used, each needs to have its own state variable in its own scope.

In many cases, completely disabling all interrupts using CRITICAL sections might be more heavy-handed than needed. When porting, consider whether other types of sections, such as ATOMIC or NVIC mask, can be used to only disable a subset of the interrupts.

Replacing em_int calls with em_core function calls:

void func(void)
{
  // INT_Disable();
  CORE_DECLARE_IRQ_STATE;
  CORE_ENTER_ATOMIC();
    .
    .
    .
  // INT_Enable();
  CORE_EXIT_ATOMIC();
}

Modules#

dwt_cycle_counter_handle_t

CORE_nvicMask_t

Typedefs#

typedef uint32_t

CORE_irqState_t

Storage for PRIMASK or BASEPRI value.

typedef uint32_t

CORE_irqState_t

Storage for PRIMASK or BASEPRI value.

Functions#

void

CORE_CriticalDisableIrq(void)

Disable interrupts.

void

CORE_CriticalEnableIrq(void)

Enable interrupts.

CORE_irqState_t

CORE_EnterCritical(void)

Enter a CRITICAL section.

void

CORE_ExitCritical(CORE_irqState_t irqState)

Exit a CRITICAL section.

void

CORE_YieldCritical(void)

Brief interrupt enable/disable sequence to allow handling of pending interrupts.

void

CORE_AtomicDisableIrq(void)

Disable interrupts.

void

CORE_AtomicEnableIrq(void)

Enable interrupts.

CORE_irqState_t

CORE_EnterAtomic(void)

Enter an ATOMIC section.

void

CORE_ExitAtomic(CORE_irqState_t irqState)

Exit an ATOMIC section.

void

CORE_YieldAtomic(void)

Brief interrupt enable/disable sequence to allow handling of pending interrupts.

void

CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)

Enter a NVIC mask section.

void

CORE_NvicDisableMask(const CORE_nvicMask_t *disable)

Disable NVIC interrupts.

void

CORE_NvicEnableMask(const CORE_nvicMask_t *enable)

Set current NVIC interrupt enable mask.

void

CORE_YieldNvicMask(const CORE_nvicMask_t *enable)

Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.

void

CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)

Utility function to set an IRQn bit in a NVIC enable/disable mask.

void

CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)

Utility function to clear an IRQn bit in a NVIC enable/disable mask.

bool

CORE_InIrqContext(void)

Check whether the current CPU operation mode is handler mode.

bool

CORE_IrqIsBlocked(IRQn_Type irqN)

Check if a specific interrupt is disabled or blocked.

bool

CORE_IrqIsDisabled(void)

Check if interrupts are disabled.

void

CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)

Get the current NVIC enable mask state.

bool

CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)

Get NVIC disable state for a given mask.

bool

CORE_NvicIRQDisabled(IRQn_Type irqN)

Check if an NVIC interrupt is disabled.

void *

CORE_GetNvicRamTableHandler(IRQn_Type irqN)

Utility function to get the handler for a specific interrupt.

void

CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)

Utility function to set the handler for a specific interrupt.

void

CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)

Initialize an interrupt vector table by copying table entries from a source to a target table.

void

cycle_counter_start(dwt_cycle_counter_handle_t *handle)

Start a recording.

void

cycle_counter_stop(dwt_cycle_counter_handle_t *handle)

Stop a recording.

uint32_t

CORE_get_max_time_critical_section(void)

Returns the max time spent in critical section.

uint32_t

CORE_get_max_time_atomic_section(void)

Returns the max time spent in atomic section.

void

CORE_clear_max_time_critical_section(void)

Clears the max time spent in atomic section.

void

CORE_clear_max_time_atomic_section(void)

Clears the max time spent in atomic section.

Macros#

#define

CORE_DECLARE_IRQ_STATE undefined

Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.

#define

CORE_CRITICAL_IRQ_DISABLE ()

CRITICAL style interrupt disable.

#define

CORE_CRITICAL_IRQ_ENABLE ()

CRITICAL style interrupt enable.

#define

CORE_CRITICAL_SECTION (yourcode)

Convenience macro for implementing a CRITICAL section.

#define

CORE_ENTER_CRITICAL ()

Enter CRITICAL section.

#define

CORE_EXIT_CRITICAL ()

Exit CRITICAL section.

#define

CORE_YIELD_CRITICAL ()

CRITICAL style yield.

#define

CORE_ATOMIC_IRQ_DISABLE ()

ATOMIC style interrupt disable.

#define

CORE_ATOMIC_IRQ_ENABLE ()

ATOMIC style interrupt enable.

#define

CORE_ATOMIC_SECTION (yourcode)

Convenience macro for implementing an ATOMIC section.

#define

CORE_ENTER_ATOMIC ()

Enter ATOMIC section.

#define

CORE_EXIT_ATOMIC ()

Exit ATOMIC section.

#define

CORE_YIELD_ATOMIC ()

ATOMIC style yield.

#define

CORE_INTERRUPT_ENTRY ()

Placeholder for optional interrupt handler entry code.

#define

CORE_INTERRUPT_EXIT ()

Placeholder for optional interrupt handler exit code.

#define

CORE_NVIC_REG_WORDS ((EXT_IRQ_COUNT + 31) / 32)

Number of words in a NVIC mask set.

#define

CORE_DEFAULT_VECTOR_TABLE_ENTRIES (EXT_IRQ_COUNT + 16)

Number of entries in a default interrupt vector table.

#define

CORE_INTERRUPT_HIGHEST_PRIORITY 0

Highest priority for core interrupt.

#define

CORE_INTERRUPT_DEFAULT_PRIORITY 5

Default priority for core interrupt.

#define

CORE_INTERRUPT_LOWEST_PRIORITY 7

Lowest priority for core interrupt.

#define

CORE_ATOMIC_METHOD_DEFAULT CORE_ATOMIC_METHOD_BASEPRI

Default method to disable interrupts in ATOMIC sections.

#define

CORE_ATOMIC_METHOD CORE_ATOMIC_METHOD_PRIMASK

Specify which method to use when implementing ATOMIC sections.

#define

CORE_DECLARE_NVIC_STATE CORE_nvicMask_t nvicState

Allocate storage for NVIC interrupt masks for use by CORE_ENTER/EXIT_NVIC() macros.

#define

CORE_DECLARE_NVIC_MASK (x)

Allocate storage for NVIC interrupt masks.

#define

CORE_DECLARE_NVIC_ZEROMASK (x)

Allocate storage for and zero initialize NVIC interrupt mask.

#define

CORE_NVIC_DISABLE (mask)

NVIC mask style interrupt disable.

#define

CORE_NVIC_ENABLE (mask)

NVIC mask style interrupt enable.

#define

CORE_NVIC_SECTION (mask, yourcode)

Convenience macro for implementing a NVIC mask section.

#define

CORE_ENTER_NVIC (disable)

Enter NVIC mask section.

#define

CORE_EXIT_NVIC ()

Exit NVIC mask section.

#define

CORE_YIELD_NVIC (enable)

NVIC maks style yield.

#define

CORE_ATOMIC_METHOD_PRIMASK 0

Use PRIMASK register to disable interrupts in ATOMIC sections.

#define

CORE_ATOMIC_METHOD_BASEPRI 1

Use BASEPRI register to disable interrupts in ATOMIC sections.

#define

CORE_ATOMIC_BASE_PRIORITY_LEVEL 3

The interrupt priority level disabled within ATOMIC regions.

#define

CORE_DECLARE_IRQ_STATE CORE_irqState_t irqState

Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.

#define

CORE_CRITICAL_IRQ_DISABLE ()

CRITICAL style interrupt disable.

#define

CORE_CRITICAL_IRQ_ENABLE ()

CRITICAL style interrupt enable.

#define

CORE_CRITICAL_SECTION (yourcode)

Convenience macro for implementing a CRITICAL section.

#define

CORE_ENTER_CRITICAL ()

Enter CRITICAL section.

#define

CORE_EXIT_CRITICAL ()

Exit CRITICAL section.

#define

CORE_YIELD_CRITICAL ()

CRITICAL style yield.

#define

CORE_ATOMIC_IRQ_DISABLE ()

ATOMIC style interrupt disable.

#define

CORE_ATOMIC_IRQ_ENABLE ()

ATOMIC style interrupt enable.

#define

CORE_ATOMIC_SECTION (yourcode)

Convenience macro for implementing an ATOMIC section.

#define

CORE_ENTER_ATOMIC ()

Enter ATOMIC section.

#define

CORE_EXIT_ATOMIC ()

Exit ATOMIC section.

#define

CORE_YIELD_ATOMIC ()

ATOMIC style yield.

#define

CORE_IRQ_DISABLED ()

Check if IRQ is disabled.

#define

CORE_IN_IRQ_CONTEXT ()

Check if inside an IRQ handler.

Typedef Documentation#

CORE_irqState_t#

typedef uint32_t CORE_irqState_t

Storage for PRIMASK or BASEPRI value.

Definition at line 121 of file platform/emlib/host/inc/em_core_generic.h

CORE_irqState_t#

typedef uint32_t CORE_irqState_t

Storage for PRIMASK or BASEPRI value.

Definition at line 146 of file platform/emlib/inc/em_core_generic.h

Function Documentation#

CORE_CriticalDisableIrq#

void CORE_CriticalDisableIrq (void)

Disable interrupts.

Parameters

N/A

Disable all interrupts by setting PRIMASK. (Fault exception handlers will still be enabled).

Definition at line 321 of file platform/emlib/src/em_core.c

CORE_CriticalEnableIrq#

void CORE_CriticalEnableIrq (void)

Enable interrupts.

Parameters

N/A

Enable interrupts by clearing PRIMASK.

Definition at line 332 of file platform/emlib/src/em_core.c

CORE_EnterCritical#

CORE_irqState_t CORE_EnterCritical (void)

Enter a CRITICAL section.

Parameters

N/A

When a CRITICAL section is entered, all interrupts (except fault handlers) are disabled.

Returns

The value of PRIMASK register prior to the CRITICAL section entry.

Definition at line 347 of file platform/emlib/src/em_core.c

CORE_ExitCritical#

void CORE_ExitCritical (CORE_irqState_t irqState)

Exit a CRITICAL section.

Parameters

[in]

irqState

The interrupt priority blocking level to restore to PRIMASK when exiting the CRITICAL section. This value is usually the one returned by a prior call to CORE_EnterCritical().

Definition at line 368 of file platform/emlib/src/em_core.c

CORE_YieldCritical#

void CORE_YieldCritical (void)

Brief interrupt enable/disable sequence to allow handling of pending interrupts.

Parameters

N/A

Note

Usually used within a CRITICAL section.

Definition at line 386 of file platform/emlib/src/em_core.c

CORE_AtomicDisableIrq#

void CORE_AtomicDisableIrq (void)

Disable interrupts.

Parameters

N/A

Disable interrupts with a priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL. Sets core BASEPRI register to CORE_ATOMIC_BASE_PRIORITY_LEVEL.

Note

If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK, this function is identical to CORE_CriticalDisableIrq().

Definition at line 407 of file platform/emlib/src/em_core.c

CORE_AtomicEnableIrq#

void CORE_AtomicEnableIrq (void)

Enable interrupts.

Parameters

N/A

Enable interrupts by setting core BASEPRI register to 0.

Note

If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_BASEPRI and PRIMASK is set (CPU is inside a CRITICAL section), interrupts will still be disabled after calling this function.
If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK, this function is identical to CORE_CriticalEnableIrq().

Definition at line 431 of file platform/emlib/src/em_core.c

CORE_EnterAtomic#

CORE_irqState_t CORE_EnterAtomic (void)

Enter an ATOMIC section.

Parameters

N/A

When an ATOMIC section is entered, interrupts with priority lower or equal to CORE_ATOMIC_BASE_PRIORITY_LEVEL are disabled.

Note

If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK, this function is identical to CORE_EnterCritical().

Returns

The value of BASEPRI register prior to ATOMIC section entry.

Definition at line 454 of file platform/emlib/src/em_core.c

CORE_ExitAtomic#

void CORE_ExitAtomic (CORE_irqState_t irqState)

Exit an ATOMIC section.

Parameters

[in]

irqState

The interrupt priority blocking level to restore to BASEPRI when exiting the ATOMIC section. This value is usually the one returned by a prior call to CORE_EnterAtomic().

Note

If CORE_ATOMIC_METHOD is set to CORE_ATOMIC_METHOD_PRIMASK, this function is identical to CORE_ExitCritical().

Definition at line 491 of file platform/emlib/src/em_core.c

CORE_YieldAtomic#

void CORE_YieldAtomic (void)

Brief interrupt enable/disable sequence to allow handling of pending interrupts.

Parameters

N/A

Note

Usully used within an ATOMIC section.
If CORE_ATOMIC_METHOD is CORE_ATOMIC_METHOD_PRIMASK, this function is identical to CORE_YieldCritical().

Definition at line 523 of file platform/emlib/src/em_core.c

CORE_EnterNvicMask#

void CORE_EnterNvicMask (CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)

Enter a NVIC mask section.

Parameters

[out]	nvicState	Return NVIC interrupts enable mask prior to section entry.
[in]	disable	A mask specifying which NVIC interrupts to disable within the section.

When a NVIC mask section is entered, specified NVIC interrupts are disabled.

Definition at line 554 of file platform/emlib/src/em_core.c

CORE_NvicDisableMask#

void CORE_NvicDisableMask (const CORE_nvicMask_t *disable)

Disable NVIC interrupts.

Parameters

[in]

disable

A mask specifying which NVIC interrupts to disable.

Definition at line 570 of file platform/emlib/src/em_core.c

CORE_NvicEnableMask#

void CORE_NvicEnableMask (const CORE_nvicMask_t *enable)

Set current NVIC interrupt enable mask.

Parameters

[out]

enable

A mask specifying which NVIC interrupts are currently enabled.

Definition at line 584 of file platform/emlib/src/em_core.c

CORE_YieldNvicMask#

void CORE_YieldNvicMask (const CORE_nvicMask_t *enable)

Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.

Parameters

[in]

enable

A mask specifying which NVIC interrupts to briefly enable.

Note

Usually used within an NVIC mask section.

Definition at line 602 of file platform/emlib/src/em_core.c

CORE_NvicMaskSetIRQ#

void CORE_NvicMaskSetIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask)

Utility function to set an IRQn bit in a NVIC enable/disable mask.

Parameters

[in]	irqN	The IRQn_Type enumerator for the interrupt.
[inout]	mask	The mask to set the interrupt bit in.

Definition at line 654 of file platform/emlib/src/em_core.c

CORE_NvicMaskClearIRQ#

void CORE_NvicMaskClearIRQ (IRQn_Type irqN, CORE_nvicMask_t *mask)

Utility function to clear an IRQn bit in a NVIC enable/disable mask.

Parameters

[in]	irqN	The IRQn_Type enumerator for the interrupt.
[inout]	mask	The mask to clear the interrupt bit in.

Definition at line 670 of file platform/emlib/src/em_core.c

CORE_InIrqContext#

bool CORE_InIrqContext (void)

Check whether the current CPU operation mode is handler mode.

Parameters

N/A

Returns

True if the CPU is in handler mode (currently executing an interrupt handler). False if the CPU is in thread mode.

Definition at line 684 of file platform/emlib/src/em_core.c

CORE_IrqIsBlocked#

bool CORE_IrqIsBlocked (IRQn_Type irqN)

Check if a specific interrupt is disabled or blocked.

Parameters

[in]

irqN

The IRQn_Type enumerator for the interrupt to check.

Returns

True if the interrupt is disabled or blocked.

Definition at line 699 of file platform/emlib/src/em_core.c

CORE_IrqIsDisabled#

bool CORE_IrqIsDisabled (void)

Check if interrupts are disabled.

Parameters

N/A

Returns

True if interrupts are disabled.

Definition at line 748 of file platform/emlib/src/em_core.c

CORE_GetNvicEnabledMask#

void CORE_GetNvicEnabledMask (CORE_nvicMask_t *mask)

Get the current NVIC enable mask state.

Parameters

[out]

mask

The current NVIC enable mask.

Definition at line 767 of file platform/emlib/src/em_core.c

CORE_GetNvicMaskDisableState#

bool CORE_GetNvicMaskDisableState (const CORE_nvicMask_t *mask)

Get NVIC disable state for a given mask.

Parameters

[in]

mask

An NVIC mask to check.

Returns

True if all NVIC interrupt mask bits are clear.

Definition at line 784 of file platform/emlib/src/em_core.c

CORE_NvicIRQDisabled#

bool CORE_NvicIRQDisabled (IRQn_Type irqN)

Check if an NVIC interrupt is disabled.

Parameters

[in]

irqN

The IRQn_Type enumerator for the interrupt to check.

Returns

True if the interrupt is disabled.

Definition at line 816 of file platform/emlib/src/em_core.c

CORE_GetNvicRamTableHandler#

void * CORE_GetNvicRamTableHandler (IRQn_Type irqN)

Utility function to get the handler for a specific interrupt.

Parameters

[in]

irqN

The IRQn_Type enumerator for the interrupt.

Returns

The handler address.

Note

Uses the interrupt vector table defined by the current VTOR register value.

Definition at line 839 of file platform/emlib/src/em_core.c

CORE_SetNvicRamTableHandler#

void CORE_SetNvicRamTableHandler (IRQn_Type irqN, void *handler)

Utility function to set the handler for a specific interrupt.

Parameters

[in]	irqN	The IRQn_Type enumerator for the interrupt.
[in]	handler	The handler address.

Note

Uses the interrupt vector table defined by the current VTOR register value.

Definition at line 858 of file platform/emlib/src/em_core.c

CORE_InitNvicVectorTable#

void CORE_InitNvicVectorTable (uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)

Initialize an interrupt vector table by copying table entries from a source to a target table.

Parameters

[in]	sourceTable	The address of the source vector table.
[in]	sourceSize	A number of entries in the source vector table.
[in]	targetTable	The address of the target (new) vector table.
[in]	targetSize	A number of entries in the target vector table.
[in]	defaultHandler	An address of the interrupt handler used for target entries for which where there is no corresponding source entry (i.e., the target table is larger than the source table).
[in]	overwriteActive	When true, a target table entry is always overwritten with the corresponding source entry. If false, a target table entry is only overwritten if it is zero. This makes it possible for an application to partly initialize a target table before passing it to this function.

Note

This function will set a new VTOR register value.

Definition at line 895 of file platform/emlib/src/em_core.c

cycle_counter_start#

static void cycle_counter_start (dwt_cycle_counter_handle_t *handle)

Start a recording.

Parameters

[in]

handle

Pointer to initialized counter handle.

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 954 of file platform/emlib/src/em_core.c

cycle_counter_stop#

static void cycle_counter_stop (dwt_cycle_counter_handle_t *handle)

Stop a recording.

Parameters

[in]

handle

Pointer to initialized counter handle.

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 968 of file platform/emlib/src/em_core.c

CORE_get_max_time_critical_section#

uint32_t CORE_get_max_time_critical_section (void)

Returns the max time spent in critical section.

Parameters

N/A

Returns

The max time spent in critical section.

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 986 of file platform/emlib/src/em_core.c

CORE_get_max_time_atomic_section#

uint32_t CORE_get_max_time_atomic_section (void)

Returns the max time spent in atomic section.

Parameters

N/A

Returns

The max time spent in atomic section.

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 1000 of file platform/emlib/src/em_core.c

CORE_clear_max_time_critical_section#

void CORE_clear_max_time_critical_section (void)

Clears the max time spent in atomic section.

Parameters

N/A

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 1011 of file platform/emlib/src/em_core.c

CORE_clear_max_time_atomic_section#

void CORE_clear_max_time_atomic_section (void)

Clears the max time spent in atomic section.

Parameters

N/A

Note

SL_EMLIB_CORE_ENABLE_INTERRUPT_DISABLED_TIMING must be enabled.

Definition at line 1022 of file platform/emlib/src/em_core.c

Macro Definition Documentation#

CORE_DECLARE_IRQ_STATE#

#define CORE_DECLARE_IRQ_STATE

Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.

Definition at line 54 of file platform/emlib/host/inc/em_core_generic.h

CORE_CRITICAL_IRQ_DISABLE#

#define CORE_CRITICAL_IRQ_DISABLE

CRITICAL style interrupt disable.

Definition at line 57 of file platform/emlib/host/inc/em_core_generic.h

CORE_CRITICAL_IRQ_ENABLE#

#define CORE_CRITICAL_IRQ_ENABLE

CRITICAL style interrupt enable.

Definition at line 60 of file platform/emlib/host/inc/em_core_generic.h

CORE_CRITICAL_SECTION#

#define CORE_CRITICAL_SECTION

Value:

{ \

CORE_DECLARE_IRQ_STATE; \

CORE_ENTER_CRITICAL(); \

{ \

yourcode \

} \

CORE_EXIT_CRITICAL(); \

}

Convenience macro for implementing a CRITICAL section.

Definition at line 63 of file platform/emlib/host/inc/em_core_generic.h

CORE_ENTER_CRITICAL#

#define CORE_ENTER_CRITICAL

Enter CRITICAL section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 75 of file platform/emlib/host/inc/em_core_generic.h

CORE_EXIT_CRITICAL#

#define CORE_EXIT_CRITICAL

Exit CRITICAL section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 79 of file platform/emlib/host/inc/em_core_generic.h

CORE_YIELD_CRITICAL#

#define CORE_YIELD_CRITICAL

CRITICAL style yield.

Definition at line 82 of file platform/emlib/host/inc/em_core_generic.h

CORE_ATOMIC_IRQ_DISABLE#

#define CORE_ATOMIC_IRQ_DISABLE

ATOMIC style interrupt disable.

Definition at line 89 of file platform/emlib/host/inc/em_core_generic.h

CORE_ATOMIC_IRQ_ENABLE#

#define CORE_ATOMIC_IRQ_ENABLE

ATOMIC style interrupt enable.

Definition at line 92 of file platform/emlib/host/inc/em_core_generic.h

CORE_ATOMIC_SECTION#

#define CORE_ATOMIC_SECTION

Value:

{ \

CORE_DECLARE_IRQ_STATE; \

CORE_ENTER_ATOMIC(); \

{ \

yourcode \

} \

CORE_EXIT_ATOMIC(); \

}

Convenience macro for implementing an ATOMIC section.

Definition at line 95 of file platform/emlib/host/inc/em_core_generic.h

CORE_ENTER_ATOMIC#

#define CORE_ENTER_ATOMIC

Enter ATOMIC section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 107 of file platform/emlib/host/inc/em_core_generic.h

CORE_EXIT_ATOMIC#

#define CORE_EXIT_ATOMIC

Exit ATOMIC section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 111 of file platform/emlib/host/inc/em_core_generic.h

CORE_YIELD_ATOMIC#

#define CORE_YIELD_ATOMIC

ATOMIC style yield.

Definition at line 114 of file platform/emlib/host/inc/em_core_generic.h

CORE_INTERRUPT_ENTRY#

#define CORE_INTERRUPT_ENTRY

Placeholder for optional interrupt handler entry code.

This might be needed when working with an RTOS.

Definition at line 261 of file platform/emlib/src/em_core.c

CORE_INTERRUPT_EXIT#

#define CORE_INTERRUPT_EXIT

Placeholder for optional interrupt handler exit code.

This might be needed when working with an RTOS.

Definition at line 267 of file platform/emlib/src/em_core.c

CORE_NVIC_REG_WORDS#

#define CORE_NVIC_REG_WORDS

Value:

((EXT_IRQ_COUNT + 31) / 32)

Number of words in a NVIC mask set.

Definition at line 63 of file platform/emlib/inc/em_core.h

CORE_DEFAULT_VECTOR_TABLE_ENTRIES#

#define CORE_DEFAULT_VECTOR_TABLE_ENTRIES

Value:

(EXT_IRQ_COUNT + 16)

Number of entries in a default interrupt vector table.

Definition at line 66 of file platform/emlib/inc/em_core.h

CORE_INTERRUPT_HIGHEST_PRIORITY#

#define CORE_INTERRUPT_HIGHEST_PRIORITY

Value:

Highest priority for core interrupt.

Definition at line 73 of file platform/emlib/inc/em_core.h

CORE_INTERRUPT_DEFAULT_PRIORITY#

#define CORE_INTERRUPT_DEFAULT_PRIORITY

Value:

Default priority for core interrupt.

Definition at line 76 of file platform/emlib/inc/em_core.h

CORE_INTERRUPT_LOWEST_PRIORITY#

#define CORE_INTERRUPT_LOWEST_PRIORITY

Value:

Lowest priority for core interrupt.

Definition at line 79 of file platform/emlib/inc/em_core.h

CORE_ATOMIC_METHOD_DEFAULT#

#define CORE_ATOMIC_METHOD_DEFAULT

Value:

CORE_ATOMIC_METHOD_BASEPRI

Default method to disable interrupts in ATOMIC sections.

Definition at line 82 of file platform/emlib/inc/em_core.h

CORE_ATOMIC_METHOD#

#define CORE_ATOMIC_METHOD

Value:

CORE_ATOMIC_METHOD_PRIMASK

Specify which method to use when implementing ATOMIC sections.

You can select between BASEPRI or PRIMASK method. Note

On Cortex-M0+ devices only PRIMASK can be used.

Definition at line 103 of file platform/emlib/inc/em_core.h

CORE_DECLARE_NVIC_STATE#

#define CORE_DECLARE_NVIC_STATE

Value:

CORE_nvicMask_t nvicState

Allocate storage for NVIC interrupt masks for use by CORE_ENTER/EXIT_NVIC() macros.

Definition at line 128 of file platform/emlib/inc/em_core.h

CORE_DECLARE_NVIC_MASK#

#define CORE_DECLARE_NVIC_MASK

Value:

(x)

Allocate storage for NVIC interrupt masks.

Definition at line 133 of file platform/emlib/inc/em_core.h

CORE_DECLARE_NVIC_ZEROMASK#

#define CORE_DECLARE_NVIC_ZEROMASK

Value:

(x)

Allocate storage for and zero initialize NVIC interrupt mask.

Definition at line 138 of file platform/emlib/inc/em_core.h

CORE_NVIC_DISABLE#

#define CORE_NVIC_DISABLE

Value:

(mask)

NVIC mask style interrupt disable.

Definition at line 143 of file platform/emlib/inc/em_core.h

CORE_NVIC_ENABLE#

#define CORE_NVIC_ENABLE

Value:

(mask)

NVIC mask style interrupt enable.

Definition at line 148 of file platform/emlib/inc/em_core.h

CORE_NVIC_SECTION#

#define CORE_NVIC_SECTION

Value:

{ \

CORE_DECLARE_NVIC_STATE; \

CORE_ENTER_NVIC(mask); \

{ \

yourcode \

} \

CORE_EXIT_NVIC(); \

}

Convenience macro for implementing a NVIC mask section.

Definition at line 155 of file platform/emlib/inc/em_core.h

CORE_ENTER_NVIC#

#define CORE_ENTER_NVIC

Value:

(disable)

Enter NVIC mask section.

Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.

Definition at line 169 of file platform/emlib/inc/em_core.h

CORE_EXIT_NVIC#

#define CORE_EXIT_NVIC

Value:

()

Exit NVIC mask section.

Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.

Definition at line 173 of file platform/emlib/inc/em_core.h

CORE_YIELD_NVIC#

#define CORE_YIELD_NVIC

Value:

(enable)

NVIC maks style yield.

Definition at line 178 of file platform/emlib/inc/em_core.h

CORE_ATOMIC_METHOD_PRIMASK#

#define CORE_ATOMIC_METHOD_PRIMASK

Value:

Use PRIMASK register to disable interrupts in ATOMIC sections.

Definition at line 47 of file platform/emlib/inc/em_core_generic.h

CORE_ATOMIC_METHOD_BASEPRI#

#define CORE_ATOMIC_METHOD_BASEPRI

Value:

Use BASEPRI register to disable interrupts in ATOMIC sections.

Definition at line 50 of file platform/emlib/inc/em_core_generic.h

CORE_ATOMIC_BASE_PRIORITY_LEVEL#

#define CORE_ATOMIC_BASE_PRIORITY_LEVEL

Value:

The interrupt priority level disabled within ATOMIC regions.

Interrupts with priority level equal to or lower than this definition will be disabled within ATOMIC regions.

Definition at line 56 of file platform/emlib/inc/em_core_generic.h

CORE_DECLARE_IRQ_STATE#

#define CORE_DECLARE_IRQ_STATE

Value:

CORE_irqState_t irqState

Allocate storage for PRIMASK or BASEPRI value for use by CORE_ENTER/EXIT_ATOMIC() and CORE_ENTER/EXIT_CRITICAL() macros.

Definition at line 73 of file platform/emlib/inc/em_core_generic.h

CORE_CRITICAL_IRQ_DISABLE#

#define CORE_CRITICAL_IRQ_DISABLE

Value:

()

CRITICAL style interrupt disable.

Definition at line 76 of file platform/emlib/inc/em_core_generic.h

CORE_CRITICAL_IRQ_ENABLE#

#define CORE_CRITICAL_IRQ_ENABLE

Value:

()

CRITICAL style interrupt enable.

Definition at line 79 of file platform/emlib/inc/em_core_generic.h

CORE_CRITICAL_SECTION#

#define CORE_CRITICAL_SECTION

Value:

{ \

CORE_DECLARE_IRQ_STATE; \

CORE_ENTER_CRITICAL(); \

{ \

yourcode \

} \

CORE_EXIT_CRITICAL(); \

}

Convenience macro for implementing a CRITICAL section.

Definition at line 82 of file platform/emlib/inc/em_core_generic.h

CORE_ENTER_CRITICAL#

#define CORE_ENTER_CRITICAL

Value:

()

Enter CRITICAL section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 94 of file platform/emlib/inc/em_core_generic.h

CORE_EXIT_CRITICAL#

#define CORE_EXIT_CRITICAL

Value:

()

Exit CRITICAL section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 98 of file platform/emlib/inc/em_core_generic.h

CORE_YIELD_CRITICAL#

#define CORE_YIELD_CRITICAL

Value:

()

CRITICAL style yield.

Definition at line 101 of file platform/emlib/inc/em_core_generic.h

CORE_ATOMIC_IRQ_DISABLE#

#define CORE_ATOMIC_IRQ_DISABLE

Value:

()

ATOMIC style interrupt disable.

Definition at line 108 of file platform/emlib/inc/em_core_generic.h

CORE_ATOMIC_IRQ_ENABLE#

#define CORE_ATOMIC_IRQ_ENABLE

Value:

()

ATOMIC style interrupt enable.

Definition at line 111 of file platform/emlib/inc/em_core_generic.h

CORE_ATOMIC_SECTION#

#define CORE_ATOMIC_SECTION

Value:

{ \

CORE_DECLARE_IRQ_STATE; \

CORE_ENTER_ATOMIC(); \

{ \

yourcode \

} \

CORE_EXIT_ATOMIC(); \

}

Convenience macro for implementing an ATOMIC section.

Definition at line 114 of file platform/emlib/inc/em_core_generic.h

CORE_ENTER_ATOMIC#

#define CORE_ENTER_ATOMIC

Value:

()

Enter ATOMIC section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 126 of file platform/emlib/inc/em_core_generic.h

CORE_EXIT_ATOMIC#

#define CORE_EXIT_ATOMIC

Value:

()

Exit ATOMIC section.

Assumes that a CORE_DECLARE_IRQ_STATE exist in scope.

Definition at line 130 of file platform/emlib/inc/em_core_generic.h

CORE_YIELD_ATOMIC#

#define CORE_YIELD_ATOMIC

Value:

()

ATOMIC style yield.

Definition at line 133 of file platform/emlib/inc/em_core_generic.h

CORE_IRQ_DISABLED#

#define CORE_IRQ_DISABLED

Value:

()

Check if IRQ is disabled.

Definition at line 136 of file platform/emlib/inc/em_core_generic.h

CORE_IN_IRQ_CONTEXT#

#define CORE_IN_IRQ_CONTEXT

Value:

()

Check if inside an IRQ handler.

Definition at line 139 of file platform/emlib/inc/em_core_generic.h