CMU - Clock Management Unit#

Clock management unit (CMU) Peripheral API.

This module contains functions for the CMU peripheral of Silicon Labs 32-bit MCUs and SoCs. The CMU module controls oscillators, clocks gates, clock multiplexers, pre-scalers, calibration modules and wait-states.

Modules#

CMU_LFXOInit_TypeDef

CMU_HFXOInit_TypeDef

CMU_DPLLInit_TypeDef

Enumerations#

enum
cmuHFRCOFreq_1M0Hz = 1000000U
cmuHFRCOFreq_2M0Hz = 2000000U
cmuHFRCOFreq_4M0Hz = 4000000U
cmuHFRCOFreq_7M0Hz = 7000000U
cmuHFRCOFreq_13M0Hz = 13000000U
cmuHFRCOFreq_16M0Hz = 16000000U
cmuHFRCOFreq_19M0Hz = 19000000U
cmuHFRCOFreq_26M0Hz = 26000000U
cmuHFRCOFreq_32M0Hz = 32000000U
cmuHFRCOFreq_38M0Hz = 38000000U
cmuHFRCOFreq_UserDefined = 0
}

High-frequency system RCO bands.

enum
cmuAUXHFRCOFreq_1M0Hz = 1000000U
cmuAUXHFRCOFreq_2M0Hz = 2000000U
cmuAUXHFRCOFreq_4M0Hz = 4000000U
cmuAUXHFRCOFreq_7M0Hz = 7000000U
cmuAUXHFRCOFreq_13M0Hz = 13000000U
cmuAUXHFRCOFreq_16M0Hz = 16000000U
cmuAUXHFRCOFreq_19M0Hz = 19000000U
cmuAUXHFRCOFreq_26M0Hz = 26000000U
cmuAUXHFRCOFreq_32M0Hz = 32000000U
cmuAUXHFRCOFreq_38M0Hz = 38000000U
cmuAUXHFRCOFreq_UserDefined = 0
}

AUX high-frequency RCO bands.

enum
cmuClock_HF = (CMU_HFCLKDIV_REG << CMU_DIV_REG_POS) | (CMU_HFCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_DBG = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_DBGCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_DBG_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_AUX = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_AUX_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_EXPORT = (CMU_HFEXPPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFEXP_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_BUS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CRYPTO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CRYPTO0 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CRYPTO1 = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_CRYPTO1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LDMA = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_LDMA_SHIFT << CMU_EN_BIT_POS) | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_GPCRC = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_GPCRC_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_GPIO = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_GPIO_SHIFT << CMU_EN_BIT_POS) | (CMU_HFBUS_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_HFLE = (CMU_HFCLKLEPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_LE_SHIFT << CMU_EN_BIT_POS) | (CMU_HFLE_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_PRS = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFBUSCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFBUSCLKEN0_PRS_SHIFT << CMU_EN_BIT_POS) | (CMU_HF_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_HFPER = (CMU_HFPERPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_CTRL_EN_REG << CMU_EN_REG_POS) | (_CMU_CTRL_HFPERCLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_USART0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_USART1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_USART2 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_USART2_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_TIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_TIMER1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TIMER1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_WTIMER0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_WTIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CRYOTIMER = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_CRYOTIMER_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_ACMP0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_ACMP1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ACMP1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_VDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_VDAC0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_IDAC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_IDAC0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_ADC0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_ADC0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_I2C0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_I2C0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_I2C1 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_I2C1_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CSEN_HF = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_TRNG0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_HFPERCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_HFPERCLKEN0_TRNG0_SHIFT << CMU_EN_BIT_POS) | (CMU_HFPER_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CORE = (CMU_HFCORECLKDIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_HFCORE_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LFA = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFACLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LETIMER0 = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LETIMER0_SHIFT << CMU_EN_BIT_POS) | (CMU_LETIMER0_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_PCNT0 = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_PCNT_EN_REG << CMU_EN_REG_POS) | (_CMU_PCNTCTRL_PCNT0CLKEN_SHIFT << CMU_EN_BIT_POS) | (CMU_LFA_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LESENSE = (CMU_LFAPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFACLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFACLKEN0_LESENSE_SHIFT << CMU_EN_BIT_POS) | (CMU_LESENSE_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LFB = (CMU_NODIV_REG << CMU_DIV_REG_POS) | (CMU_LFBCLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFB_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LEUART0 = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_LEUART0_SHIFT << CMU_EN_BIT_POS) | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_CSEN_LF = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_CSEN_SHIFT << CMU_EN_BIT_POS) | (CMU_CSEN_LF_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_SYSTICK = (CMU_LFBPRESC0_REG << CMU_DIV_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFBCLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFBCLKEN0_SYSTICK_SHIFT << CMU_EN_BIT_POS) | (CMU_LEUART0_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_LFE = (CMU_NOPRESC_REG << CMU_PRESC_REG_POS) | (CMU_LFECLKSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_LFE_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_RTCC = (CMU_LFEPRESC0_REG << CMU_PRESC_REG_POS) | (CMU_NOSEL_REG << CMU_SEL_REG_POS) | (CMU_LFECLKEN0_EN_REG << CMU_EN_REG_POS) | (_CMU_LFECLKEN0_RTCC_SHIFT << CMU_EN_BIT_POS) | (CMU_RTCC_CLK_BRANCH << CMU_CLK_BRANCH_POS)
cmuClock_ADC0ASYNC = (CMU_ADCASYNCDIV_REG << CMU_DIV_REG_POS) | (CMU_ADC0ASYNCSEL_REG << CMU_SEL_REG_POS) | (CMU_NO_EN_REG << CMU_EN_REG_POS) | (0 << CMU_EN_BIT_POS) | (CMU_ADC0ASYNC_CLK_BRANCH << CMU_CLK_BRANCH_POS)
}

Clock points in CMU.

enum
cmuOsc_LFXO
cmuOsc_LFRCO
cmuOsc_HFXO
cmuOsc_HFRCO
cmuOsc_AUXHFRCO
cmuOsc_ULFRCO
cmuOsc_CLKIN0
}

Oscillator types.

enum
cmuOscMode_Crystal
cmuOscMode_AcCoupled
cmuOscMode_External
}

Oscillator modes.

enum
cmuSelect_Error
cmuSelect_Disabled
cmuSelect_LFXO
cmuSelect_LFRCO
cmuSelect_HFXO
cmuSelect_HFRCO
cmuSelect_HFCLKLE
cmuSelect_AUXHFRCO
cmuSelect_HFSRCCLK
cmuSelect_HFCLK
cmuSelect_ULFRCO
cmuSelect_HFRCODIV2
cmuSelect_CLKIN0
}

Selectable clock sources.

enum
cmuHFXOTuningMode_Auto = 0
cmuHFXOTuningMode_PeakDetectCommand = CMU_CMD_HFXOPEAKDETSTART
cmuHFXOTuningMode_ShuntCommand = CMU_CMD_HFXOSHUNTOPTSTART
cmuHFXOTuningMode_PeakShuntCommand = CMU_CMD_HFXOPEAKDETSTART | CMU_CMD_HFXOSHUNTOPTSTART
}

HFXO tuning modes.

enum
cmuDPLLClkSel_Hfxo = _CMU_DPLLCTRL_REFSEL_HFXO
cmuDPLLClkSel_Lfxo = _CMU_DPLLCTRL_REFSEL_LFXO
cmuDPLLClkSel_Clkin0 = _CMU_DPLLCTRL_REFSEL_CLKIN0
}

DPLL reference clock selector.

enum
cmuDPLLEdgeSel_Fall = _CMU_DPLLCTRL_EDGESEL_FALL
cmuDPLLEdgeSel_Rise = _CMU_DPLLCTRL_EDGESEL_RISE
}

DPLL reference clock edge detect selector.

enum
cmuDPLLLockMode_Freq = _CMU_DPLLCTRL_MODE_FREQLL
cmuDPLLLockMode_Phase = _CMU_DPLLCTRL_MODE_PHASELL
}

DPLL lock mode selector.

Typedefs#

typedef uint32_t

Clock divider configuration.

typedef uint32_t

Clockprescaler configuration.

Functions#

Get the current AUXHFRCO frequency.

void
CMU_AUXHFRCOBandSet(CMU_AUXHFRCOFreq_TypeDef setFreq)

Set AUXHFRCO calibration for the selected target frequency.

uint32_t
CMU_Calibrate(uint32_t HFCycles, CMU_Osc_TypeDef reference)

Calibrate the clock.

void
CMU_CalibrateConfig(uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)

Configure the clock calibration.

uint32_t

Get the calibration count register.

void
CMU_ClockEnable(CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

CMU_ClockDivGet(CMU_Clock_TypeDef clock)

Get the clock divisor/prescaler.

void
CMU_ClockDivSet(CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set the clock divisor/prescaler.

uint32_t
CMU_ClockFreqGet(CMU_Clock_TypeDef clock)

Get the clock frequency for a clock point.

void
CMU_ClockPrescSet(CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)

Set the clock prescaler.

uint32_t
CMU_ClockPrescGet(CMU_Clock_TypeDef clock)

Get the clock prescaler.

void
CMU_ClockSelectSet(CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select the reference clock/oscillator used for a clock branch.

CMU_ClockSelectGet(CMU_Clock_TypeDef clock)

Get the currently selected reference clock used for a clock branch.

uint16_t
CMU_LF_ClockPrecisionGet(CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

uint16_t
CMU_HF_ClockPrecisionGet(CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

bool
CMU_DPLLLock(const CMU_DPLLInit_TypeDef *init)

Lock the DPLL to a given frequency.

void
CMU_FreezeEnable(bool enable)

CMU low frequency register synchronization freeze control.

Get the current HFRCO frequency.

void
CMU_HFRCOBandSet(CMU_HFRCOFreq_TypeDef setFreq)

Set the HFRCO calibration for the selected target frequency.

void
CMU_HFXOAutostartEnable(uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)

Enable or disable HFXO autostart.

void
CMU_HFXOInit(const CMU_HFXOInit_TypeDef *hfxoInit)

Set HFXO control registers.

uint32_t

Get the LCD framerate divisor (FDIV) setting.

void
CMU_LCDClkFDIVSet(uint32_t div)

Set the LCD framerate divisor (FDIV) setting.

void
CMU_LFXOInit(const CMU_LFXOInit_TypeDef *lfxoInit)

Set LFXO control registers.

void
CMU_LFXOPrecisionSet(uint16_t precision)

Sets LFXO's crystal precision, in PPM.

uint16_t

Gets LFXO's crystal precision, in PPM.

void
CMU_HFXOPrecisionSet(uint16_t precision)

Sets HFXO's crystal precision, in PPM.

uint16_t

Gets HFXO's crystal precision, in PPM.

void
CMU_OscillatorEnable(CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

uint32_t
CMU_OscillatorTuningGet(CMU_Osc_TypeDef osc)

Get the oscillator frequency tuning setting.

void
CMU_OscillatorTuningSet(CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

bool
CMU_OscillatorTuningWait(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)

Wait for the oscillator tuning optimization.

bool
CMU_OscillatorTuningOptimize(CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)

Start and optionally wait for the oscillator tuning optimization.

void
CMU_PCNTClockExternalSet(unsigned int instance, bool external)

Select the PCNTn clock.

bool
CMU_PCNTClockExternalGet(unsigned int instance)

Determine if the currently selected PCNTn clock used is external or LFBCLK.

void
CMU_UpdateWaitStates(uint32_t freq, int vscale)

Configure various wait states to switch to a certain frequency and a certain voltage scale.

void
CMU_CalibrateCont(bool enable)

Configure continuous calibration mode.

void

Start calibration.

void

Stop the calibration counters.

uint32_t
CMU_DivToLog2(CMU_ClkDiv_TypeDef div)

Convert divider to logarithmic value.

void

Unlock DPLL.

void
CMU_IntClear(uint32_t flags)

Clear one or more pending CMU interrupts.

void
CMU_IntDisable(uint32_t flags)

Disable one or more CMU interrupts.

void
CMU_IntEnable(uint32_t flags)

Enable one or more CMU interrupts.

uint32_t

Get pending CMU interrupts.

uint32_t

Get enabled and pending CMU interrupt flags.

void
CMU_IntSet(uint32_t flags)

Set one or more pending CMU interrupts.

void
CMU_Lock(void)

Lock the CMU to protect some of its registers against unintended modification.

void

Unlock the CMU so that writing to locked registers again is possible.

uint32_t
CMU_PrescToLog2(uint32_t presc)

Convert prescaler divider to a logarithmic value.

uint32_t
auxClkGet(void)

Get the AUX clock frequency.

uint32_t

Get the HFSRCCLK frequency.

uint32_t
dbgClkGet(void)

Get the Debug Trace clock frequency.

uint32_t
adcAsyncClkGet(uint32_t adc)

Get the ADC n asynchronous clock frequency.

void
flashWaitStateControl(uint32_t coreFreq, int vscale)

Configure flash access wait states to support the given core clock frequency.

void

Configure flash access wait states to the most conservative setting for this target.

uint32_t
getRegIshUpperVal(uint32_t steadyStateRegIsh)

Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH.

uint32_t

Get the HFXO tuning mode.

void
setHfxoTuningMode(uint32_t mode)

Set the HFXO tuning mode.

uint32_t
lfClkGet(CMU_Clock_TypeDef lfClkBranch)

Get the LFnCLK frequency based on the current configuration.

void
syncReg(uint32_t mask)

Wait for an ongoing sync of register(s) to low-frequency domain to complete.

void

Set HFPER clock tree prescalers to safe values.

void

Set HFPER clock tree prescalers to give highest possible clock node frequency while still beeing within spec.

uint32_t
CMU_AUXHFRCODevinfoGet(CMU_AUXHFRCOFreq_TypeDef freq)

Get the AUXHFRCO frequency calibration word in DEVINFO.

uint32_t
CMU_HFRCODevinfoGet(CMU_HFRCOFreq_TypeDef freq)

Get the HFRCO frequency calibration word in DEVINFO.

Macros#

#define

Macro to set clock sources in the clock tree.

#define

Clock divisors.

#define

Divide clock by 2.

#define

Divide clock by 4.

#define

Divide clock by 8.

#define

Divide clock by 16.

#define

Divide clock by 32.

#define

Divide clock by 64.

#define

Divide clock by 128.

#define

Divide clock by 256.

#define

Divide clock by 512.

#define

Divide clock by 1024.

#define

Divide clock by 2048.

#define

Divide clock by 4096.

#define

Divide clock by 8192.

#define

Divide clock by 16384.

#define

Divide clock by 32768.

#define
CMU_HFRCO_MIN cmuHFRCOFreq_1M0Hz

HFRCO minimum frequency.

#define
CMU_HFRCO_MAX cmuHFRCOFreq_38M0Hz

HFRCO maximum frequency.

#define
CMU_AUXHFRCO_MIN cmuAUXHFRCOFreq_1M0Hz

AUXHFRCO minimum frequency.

#define
CMU_AUXHFRCO_MAX cmuAUXHFRCOFreq_38M0Hz

AUXHFRCO maximum frequency.

#define

Default LFXO initialization values.

#define

Default LFXO initialization for external clock.

#define

Default HFXO initialization values for Platform 2 devices, which contain a separate HFXOCTRL register.

#define

Init of HFXO with external clock.

#define

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.

Enumeration Documentation#

CMU_HFRCOFreq_TypeDef#

CMU_HFRCOFreq_TypeDef

High-frequency system RCO bands.

Enumerator
cmuHFRCOFreq_1M0Hz

1 MHz RC band

cmuHFRCOFreq_2M0Hz

2 MHz RC band

cmuHFRCOFreq_4M0Hz

4 MHz RC band

cmuHFRCOFreq_7M0Hz

7 MHz RC band

cmuHFRCOFreq_13M0Hz

13 MHz RC band

cmuHFRCOFreq_16M0Hz

16 MHz RC band

cmuHFRCOFreq_19M0Hz

19 MHz RC band

cmuHFRCOFreq_26M0Hz

26 MHz RC band

cmuHFRCOFreq_32M0Hz

32 MHz RC band

cmuHFRCOFreq_38M0Hz

38 MHz RC band

cmuHFRCOFreq_UserDefined

Definition at line 1900 of file platform/emlib/inc/em_cmu.h

CMU_AUXHFRCOFreq_TypeDef#

CMU_AUXHFRCOFreq_TypeDef

AUX high-frequency RCO bands.

Enumerator
cmuAUXHFRCOFreq_1M0Hz

1 MHz RC band

cmuAUXHFRCOFreq_2M0Hz

2 MHz RC band

cmuAUXHFRCOFreq_4M0Hz

4 MHz RC band

cmuAUXHFRCOFreq_7M0Hz

7 MHz RC band

cmuAUXHFRCOFreq_13M0Hz

13 MHz RC band

cmuAUXHFRCOFreq_16M0Hz

16 MHz RC band

cmuAUXHFRCOFreq_19M0Hz

19 MHz RC band

cmuAUXHFRCOFreq_26M0Hz

26 MHz RC band

cmuAUXHFRCOFreq_32M0Hz

32 MHz RC band

cmuAUXHFRCOFreq_38M0Hz

38 MHz RC band

cmuAUXHFRCOFreq_UserDefined

Definition at line 1948 of file platform/emlib/inc/em_cmu.h

CMU_Clock_TypeDef#

CMU_Clock_TypeDef

Clock points in CMU.

See CMU overview in the reference manual.

Enumerator
cmuClock_HF

High-frequency clock.

cmuClock_DBG

Debug clock.

cmuClock_AUX

AUX clock.

cmuClock_EXPORT

Export clock.

cmuClock_BUS

High-frequency bus clock.

cmuClock_CRYPTO

Cryptography accelerator clock.

cmuClock_CRYPTO0

Cryptography accelerator 0 clock.

cmuClock_CRYPTO1

Cryptography accelerator 1 clock.

cmuClock_LDMA

Direct-memory access controller clock.

cmuClock_GPCRC

General-purpose cyclic redundancy checksum clock.

cmuClock_GPIO

General-purpose input/output clock.

cmuClock_HFLE

Low-energy clock divided down from HFCLK.

cmuClock_PRS

Peripheral reflex system clock.

cmuClock_HFPER

High-frequency peripheral clock.

cmuClock_USART0

Universal sync/async receiver/transmitter 0 clock.

cmuClock_USART1

Universal sync/async receiver/transmitter 1 clock.

cmuClock_USART2

Universal sync/async receiver/transmitter 2 clock.

cmuClock_TIMER0

Timer 0 clock.

cmuClock_TIMER1

Timer 1 clock.

cmuClock_WTIMER0

Wide-timer 0 clock.

cmuClock_CRYOTIMER

CRYOtimer clock.

cmuClock_ACMP0

Analog comparator 0 clock.

cmuClock_ACMP1

Analog comparator 1 clock.

cmuClock_VDAC0

Voltage digital-to-analog converter 0 clock.

cmuClock_IDAC0

Current digital-to-analog converter 0 clock.

cmuClock_ADC0

Analog-to-digital converter 0 clock.

cmuClock_I2C0

I2C 0 clock.

cmuClock_I2C1

I2C 1 clock.

cmuClock_CSEN_HF

Capacitive Sense HF clock.

cmuClock_TRNG0

True random number generator clock.

cmuClock_CORE

Core clock.

cmuClock_LFA

Low-frequency A clock.

cmuClock_LETIMER0

Low-energy timer 0 clock.

cmuClock_PCNT0

Pulse counter 0 clock.

cmuClock_LESENSE

LESENSE clock.

cmuClock_LFB

Low-frequency B clock.

cmuClock_LEUART0

Low-energy universal asynchronous receiver/transmitter 0 clock.

cmuClock_CSEN_LF

Capacitive Sense LF clock.

cmuClock_SYSTICK

Cortex SYSTICK LF clock.

cmuClock_LFE

Low-frequency E clock.

cmuClock_RTCC

Real-time counter and calendar clock.

cmuClock_ADC0ASYNC

ADC0 asynchronous clock.


Definition at line 1982 of file platform/emlib/inc/em_cmu.h

CMU_Osc_TypeDef#

CMU_Osc_TypeDef

Oscillator types.

Enumerator
cmuOsc_LFXO

Low-frequency crystal oscillator.

cmuOsc_LFRCO

Low-frequency RC oscillator.

cmuOsc_HFXO

High-frequency crystal oscillator.

cmuOsc_HFRCO

High-frequency RC oscillator.

cmuOsc_AUXHFRCO

Auxiliary high-frequency RC oscillator.

cmuOsc_ULFRCO

Ultra low-frequency RC oscillator.

cmuOsc_CLKIN0

External oscillator.


Definition at line 2976 of file platform/emlib/inc/em_cmu.h

CMU_OscMode_TypeDef#

CMU_OscMode_TypeDef

Oscillator modes.

Enumerator
cmuOscMode_Crystal

Crystal oscillator.

cmuOscMode_AcCoupled

AC-coupled buffer.

cmuOscMode_External

External digital clock.


Definition at line 2997 of file platform/emlib/inc/em_cmu.h

CMU_Select_TypeDef#

CMU_Select_TypeDef

Selectable clock sources.

Enumerator
cmuSelect_Error

Usage error.

cmuSelect_Disabled

Clock selector disabled.

cmuSelect_LFXO

Low-frequency crystal oscillator.

cmuSelect_LFRCO

Low-frequency RC oscillator.

cmuSelect_HFXO

High-frequency crystal oscillator.

cmuSelect_HFRCO

High-frequency RC oscillator.

cmuSelect_HFCLKLE

High-frequency LE clock divided by 2 or 4.

cmuSelect_AUXHFRCO

Auxiliary clock source can be used for debug clock.

cmuSelect_HFSRCCLK

High-frequency source clock.

cmuSelect_HFCLK

Divided HFCLK on Giant for debug clock, undivided on Tiny Gecko and for USBC (not used on Gecko).

cmuSelect_ULFRCO

Ultra low-frequency RC oscillator.

cmuSelect_HFRCODIV2

High-frequency RC oscillator divided by 2.

cmuSelect_CLKIN0

External clock input.


Definition at line 3004 of file platform/emlib/inc/em_cmu.h

CMU_HFXOTuningMode_TypeDef#

CMU_HFXOTuningMode_TypeDef

HFXO tuning modes.

Enumerator
cmuHFXOTuningMode_Auto
cmuHFXOTuningMode_PeakDetectCommand

Run peak detect optimization only.

cmuHFXOTuningMode_ShuntCommand

Run shunt current optimization only.

cmuHFXOTuningMode_PeakShuntCommand

Run peak and shunt current optimization.


Definition at line 3048 of file platform/emlib/inc/em_cmu.h

CMU_DPLLClkSel_TypeDef#

CMU_DPLLClkSel_TypeDef

DPLL reference clock selector.

Enumerator
cmuDPLLClkSel_Hfxo

HFXO is DPLL reference clock.

cmuDPLLClkSel_Lfxo

LFXO is DPLL reference clock.

cmuDPLLClkSel_Clkin0

CLKIN0 is DPLL reference clock.


Definition at line 3073 of file platform/emlib/inc/em_cmu.h

CMU_DPLLEdgeSel_TypeDef#

CMU_DPLLEdgeSel_TypeDef

DPLL reference clock edge detect selector.

Enumerator
cmuDPLLEdgeSel_Fall

Detect falling edge of reference clock.

cmuDPLLEdgeSel_Rise

Detect rising edge of reference clock.


Definition at line 3080 of file platform/emlib/inc/em_cmu.h

CMU_DPLLLockMode_TypeDef#

CMU_DPLLLockMode_TypeDef

DPLL lock mode selector.

Enumerator
cmuDPLLLockMode_Freq

Frequency lock mode.

cmuDPLLLockMode_Phase

Phase lock mode.


Definition at line 3086 of file platform/emlib/inc/em_cmu.h

Typedef Documentation#

CMU_ClkDiv_TypeDef#

typedef uint32_t CMU_ClkDiv_TypeDef

Clock divider configuration.


Definition at line 1838 of file platform/emlib/inc/em_cmu.h

CMU_ClkPresc_TypeDef#

typedef uint32_t CMU_ClkPresc_TypeDef

Clockprescaler configuration.


Definition at line 1842 of file platform/emlib/inc/em_cmu.h

Function Documentation#

CMU_AUXHFRCOBandGet#

CMU_AUXHFRCOFreq_TypeDef CMU_AUXHFRCOBandGet (void )

Get the current AUXHFRCO frequency.

Parameters
N/A

Returns

  • AUXHFRCO frequency.


Definition at line 6830 of file platform/emlib/src/em_cmu.c

CMU_AUXHFRCOBandSet#

void CMU_AUXHFRCOBandSet (CMU_AUXHFRCOFreq_TypeDef setFreq)

Set AUXHFRCO calibration for the selected target frequency.

Parameters
[in]setFreq

AUXHFRCO frequency to set


Definition at line 6844 of file platform/emlib/src/em_cmu.c

CMU_Calibrate#

uint32_t CMU_Calibrate (uint32_t HFCycles, CMU_Osc_TypeDef reference)

Calibrate the clock.

Parameters
[in]HFCycles

The number of HFCLK cycles to run the calibration. Increasing this number increases precision but the calibration will take more time.

[in]reference

The reference clock used to compare HFCLK.

Run a calibration for HFCLK against a selectable reference clock. See the reference manual, CMU chapter, for more details.

Note

  • This function will not return until the calibration measurement is completed.

Returns

  • The number of ticks the reference clock after HFCycles ticks on the HF clock.


Definition at line 6905 of file platform/emlib/src/em_cmu.c

CMU_CalibrateConfig#

void CMU_CalibrateConfig (uint32_t downCycles, CMU_Osc_TypeDef downSel, CMU_Osc_TypeDef upSel)

Configure the clock calibration.

Parameters
[in]downCycles

The number of downSel clock cycles to run the calibration. Increasing this number increases precision but the calibration will take more time.

[in]downSel

The clock, which will be counted down downCycles.

[in]upSel

The reference clock; the number of cycles generated by this clock will be counted and added up and the result can be given with the CMU_CalibrateCountGet() function call.

Configure a calibration for a selectable clock source against another selectable reference clock. See the reference manual, CMU chapter, for more details.

Note


Definition at line 6994 of file platform/emlib/src/em_cmu.c

CMU_CalibrateCountGet#

uint32_t CMU_CalibrateCountGet (void )

Get the calibration count register.

Parameters
N/A

Note

  • If continuous calibration mode is active, calibration busy will almost always be off and only the value needs to be read. In a normal case, this function call is triggered by the CALRDY interrupt flag.

Returns

  • The calibration count, the number of UPSEL clocks in the period of DOWNSEL oscillator clock cycles configured by a previous write operation to CMU->CALCNT.


Definition at line 7102 of file platform/emlib/src/em_cmu.c

CMU_ClockEnable#

void CMU_ClockEnable (CMU_Clock_TypeDef clock, bool enable)

Enable/disable a clock.

Parameters
[in]clock

The clock to enable/disable. Notice that not all defined clock points have separate enable/disable control. See the CMU overview in the reference manual.

[in]enable
  • true - enable specified clock.

  • false - disable specified clock.

In general, module clocking is disabled after a reset. If a module clock is disabled, the registers of that module are not accessible and reading from such registers may return undefined values. Writing to registers of clock-disabled modules has no effect. Avoid accessing module registers of a module with a disabled clock.

Note

  • If enabling/disabling an LF clock, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.


Definition at line 7502 of file platform/emlib/src/em_cmu.c

CMU_ClockDivGet#

CMU_ClkDiv_TypeDef CMU_ClockDivGet (CMU_Clock_TypeDef clock)

Get the clock divisor/prescaler.

Parameters
[in]clock

A clock point to get the divisor/prescaler for. Notice that not all clock points have a divisor/prescaler. See the CMU overview in the reference manual.

Returns

  • The current clock point divisor/prescaler. 1 is returned if clock specifies a clock point without a divisor/prescaler.


Definition at line 7137 of file platform/emlib/src/em_cmu.c

CMU_ClockDivSet#

void CMU_ClockDivSet (CMU_Clock_TypeDef clock, CMU_ClkDiv_TypeDef div)

Set the clock divisor/prescaler.

Parameters
[in]clock

Clock point to set divisor/prescaler for. Notice that not all clock points have a divisor/prescaler. See the CMU overview in the reference manual.

[in]div

The clock divisor to use (<= cmuClkDiv_512).

Note

  • If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.


Definition at line 7277 of file platform/emlib/src/em_cmu.c

CMU_ClockFreqGet#

uint32_t CMU_ClockFreqGet (CMU_Clock_TypeDef clock)

Get the clock frequency for a clock point.

Parameters
[in]clock

A clock point to fetch the frequency for.

Returns

  • The current frequency in Hz.


Definition at line 7626 of file platform/emlib/src/em_cmu.c

CMU_ClockPrescSet#

void CMU_ClockPrescSet (CMU_Clock_TypeDef clock, CMU_ClkPresc_TypeDef presc)

Set the clock prescaler.

Parameters
[in]clock

A clock point to set the prescaler for. Notice that not all clock points have a prescaler. See the CMU overview in the reference manual.

[in]presc

The clock prescaler. The prescaler value is linked to the clock divider by: divider = 'presc' + 1.

Note

  • If setting an LF clock prescaler, synchronization into the low-frequency domain is required. If the same register is modified before a previous update has completed, this function will stall until the previous synchronization has completed. See CMU_FreezeEnable() for a suggestion on how to reduce the stalling time in some use cases.

HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.


Definition at line 8139 of file platform/emlib/src/em_cmu.c

CMU_ClockPrescGet#

uint32_t CMU_ClockPrescGet (CMU_Clock_TypeDef clock)

Get the clock prescaler.

Parameters
[in]clock

A clock point to get the prescaler for. Notice that not all clock points have a prescaler. See the CMU overview in the reference manual.

Returns

  • The prescaler value of the current clock point. 0 is returned if clock specifies a clock point without a prescaler.


Definition at line 7924 of file platform/emlib/src/em_cmu.c

CMU_ClockSelectSet#

void CMU_ClockSelectSet (CMU_Clock_TypeDef clock, CMU_Select_TypeDef ref)

Select the reference clock/oscillator used for a clock branch.

Parameters
[in]clock

A clock branch to select reference clock for. One of:

[in]ref

A reference selected for clocking. See the reference manual for details about references available for a specific clock branch.

Notice that if a selected reference is not enabled prior to selecting its use, it will be enabled and this function will wait for the selected oscillator to be stable. It will however NOT be disabled if another reference clock is selected later.

This feature is particularly important if selecting a new reference clock for the clock branch clocking the core. Otherwise, the system may halt.

Note

  • HFCLKLE prescaler is automatically modified when peripherals with clock domain HFBUSCLK is chosen based on the maximum HFLE frequency allowed.


Definition at line 9393 of file platform/emlib/src/em_cmu.c

CMU_ClockSelectGet#

CMU_Select_TypeDef CMU_ClockSelectGet (CMU_Clock_TypeDef clock)

Get the currently selected reference clock used for a clock branch.

Parameters
[in]clock

Clock branch to fetch selected ref. clock for. One of:

Returns

  • The reference clock used for clocking the selected branch, cmuSelect_Error if invalid clock provided.


Definition at line 8477 of file platform/emlib/src/em_cmu.c

CMU_LF_ClockPrecisionGet#

uint16_t CMU_LF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified low frequency clock branch.

Parameters
[in]clock

Clock branch.

Returns

  • Precision, in PPM, of the specified clock branch.

Note

  • This function is only for internal usage.

  • The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.


Definition at line 10117 of file platform/emlib/src/em_cmu.c

CMU_HF_ClockPrecisionGet#

uint16_t CMU_HF_ClockPrecisionGet (CMU_Clock_TypeDef clock)

Gets the precision (in PPM) of the specified high frequency clock branch.

Parameters
[in]clock

Clock branch.

Returns

  • Precision, in PPM, of the specified clock branch.

Note

  • This function is only for internal usage.

  • The current implementation of this function is used to determine if the clock has a precision <= 500 ppm or not (which is the minimum required for BLE). Future version of this function should provide more accurate precision numbers to allow for further optimizations from the stacks.


Definition at line 10160 of file platform/emlib/src/em_cmu.c

CMU_DPLLLock#

bool CMU_DPLLLock (const CMU_DPLLInit_TypeDef * init)

Lock the DPLL to a given frequency.

Parameters
[in]init

DPLL setup parameters.

The frequency is given by: Fout = Fref * (N+1) / (M+1).

Note

  • This function does not check if the given N & M values will actually produce the desired target frequency.
    N & M limitations:
    300 < N <= 4095
    0 <= M <= 4095
    Any peripheral running off HFRCO should be switched to HFRCODIV2 prior to calling this function to avoid over-clocking.

HFCLKLE prescaler is automatically modified before updating HFRCO based on the maximum HFLE frequency allowed.

Returns

  • Returns false on invalid target frequency or DPLL locking error.


Definition at line 10207 of file platform/emlib/src/em_cmu.c

CMU_FreezeEnable#

void CMU_FreezeEnable (bool enable)

CMU low frequency register synchronization freeze control.

Parameters
[in]enable
  • true - enable freeze, modified registers are not propagated to the LF domain

  • false - disable freeze, modified registers are propagated to the LF domain

Some CMU registers require synchronization into the low-frequency (LF) domain. The freeze feature allows for several such registers to be modified before passing them to the LF domain simultaneously (which takes place when the freeze mode is disabled).

Another use case for this feature is using an API (such as the CMU API) for modifying several bit fields consecutively in the same register. If freeze mode is enabled during this sequence, stalling can be avoided.

Note

  • When enabling freeze mode, this function will wait for all current ongoing CMU synchronization to LF domain to complete (normally synchronization will not be in progress.) However, for this reason, when using freeze mode, modifications of registers requiring LF synchronization should be done within one freeze enable/disable block to avoid unnecessary stalling.


Definition at line 10363 of file platform/emlib/src/em_cmu.c

CMU_HFRCOBandGet#

CMU_HFRCOFreq_TypeDef CMU_HFRCOBandGet (void )

Get the current HFRCO frequency.

Parameters
N/A

Returns

  • HFRCO frequency.


Definition at line 10555 of file platform/emlib/src/em_cmu.c

CMU_HFRCOBandSet#

void CMU_HFRCOBandSet (CMU_HFRCOFreq_TypeDef setFreq)

Set the HFRCO calibration for the selected target frequency.

Parameters
[in]setFreq

HFRCO frequency to set.

Note

  • HFCLKLE prescaler is automatically modified based on the maximum HFLE frequency allowed.


Definition at line 10571 of file platform/emlib/src/em_cmu.c

CMU_HFXOAutostartEnable#

void CMU_HFXOAutostartEnable (uint32_t userSel, bool enEM0EM1Start, bool enEM0EM1StartSel)

Enable or disable HFXO autostart.

Parameters
[in]userSel

Additional user specified enable bit.

[in]enEM0EM1Start

If true, HFXO is automatically started upon entering EM0/EM1 entry from EM2/EM3. HFXO selection has to be handled by the user. If false, HFXO is not started automatically when entering EM0/EM1.

[in]enEM0EM1StartSel

If true, HFXO is automatically started and immediately selected upon entering EM0/EM1 entry from EM2/EM3. Note that this option stalls the use of HFSRCCLK until HFXO becomes ready. HFCLKLE prescaler is also automatically modified if userSel is specified. If false, HFXO is not started or selected automatically when entering EM0/EM1.


Definition at line 10799 of file platform/emlib/src/em_cmu.c

CMU_HFXOInit#

void CMU_HFXOInit (const CMU_HFXOInit_TypeDef * hfxoInit)

Set HFXO control registers.

Parameters
[in]hfxoInit

HFXO setup parameters.

Note

  • HFXO configuration should be obtained from a configuration tool, app note, or crystal data sheet. This function disables the HFXO to ensure a valid state before update.


Definition at line 10864 of file platform/emlib/src/em_cmu.c

CMU_LCDClkFDIVGet#

uint32_t CMU_LCDClkFDIVGet (void )

Get the LCD framerate divisor (FDIV) setting.

Parameters
N/A

Returns

  • The LCD framerate divisor.


Definition at line 10996 of file platform/emlib/src/em_cmu.c

CMU_LCDClkFDIVSet#

void CMU_LCDClkFDIVSet (uint32_t div)

Set the LCD framerate divisor (FDIV) setting.

Parameters
[in]div

The FDIV setting to use.

Note

  • The FDIV field (CMU LCDCTRL register) should only be modified while the LCD module is clock disabled (CMU LFACLKEN0.LCD bit is 0). This function will NOT modify FDIV if the LCD module clock is enabled. See CMU_ClockEnable() for disabling/enabling LCD clock.


Definition at line 11018 of file platform/emlib/src/em_cmu.c

CMU_LFXOInit#

void CMU_LFXOInit (const CMU_LFXOInit_TypeDef * lfxoInit)

Set LFXO control registers.

Parameters
[in]lfxoInit

LFXO setup parameters.

Note

  • LFXO configuration should be obtained from a configuration tool, app note, or crystal data sheet. This function disables the LFXO when necessary to ensure a valid state before update.


Definition at line 11048 of file platform/emlib/src/em_cmu.c

CMU_LFXOPrecisionSet#

void CMU_LFXOPrecisionSet (uint16_t precision)

Sets LFXO's crystal precision, in PPM.

Parameters
[in]precision

LFXO's crystal precision, in PPM.

Note

  • LFXO precision should be obtained from a crystal datasheet.


Definition at line 11101 of file platform/emlib/src/em_cmu.c

CMU_LFXOPrecisionGet#

uint16_t CMU_LFXOPrecisionGet (void )

Gets LFXO's crystal precision, in PPM.

Parameters
[in]

LFXO's crystal precision, in PPM.


Definition at line 11113 of file platform/emlib/src/em_cmu.c

CMU_HFXOPrecisionSet#

void CMU_HFXOPrecisionSet (uint16_t precision)

Sets HFXO's crystal precision, in PPM.

Parameters
[in]precision

HFXO's crystal precision, in PPM.

Note

  • HFXO precision should be obtained from a crystal datasheet.


Definition at line 11128 of file platform/emlib/src/em_cmu.c

CMU_HFXOPrecisionGet#

uint16_t CMU_HFXOPrecisionGet (void )

Gets HFXO's crystal precision, in PPM.

Parameters
[in]

HFXO's crystal precision, in PPM.


Definition at line 11140 of file platform/emlib/src/em_cmu.c

CMU_OscillatorEnable#

void CMU_OscillatorEnable (CMU_Osc_TypeDef osc, bool enable, bool wait)

Enable/disable oscillator.

Parameters
[in]osc

The oscillator to enable/disable.

[in]enable
  • true - enable specified oscillator.

  • false - disable specified oscillator.

[in]wait

Only used if enable is true.

  • true - wait for oscillator start-up time to timeout before returning.

  • false - do not wait for oscillator start-up time to timeout before returning.

Note

  • WARNING: When this function is called to disable either cmuOsc_LFXO or cmuOsc_HFXO, the LFXOMODE or HFXOMODE fields of the CMU_CTRL register are reset to the reset value. In other words, if external clock sources are selected in either LFXOMODE or HFXOMODE fields, the configuration will be cleared and needs to be reconfigured if needed later.


Definition at line 11169 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningGet#

uint32_t CMU_OscillatorTuningGet (CMU_Osc_TypeDef osc)

Get the oscillator frequency tuning setting.

Parameters
[in]osc

An oscillator to get tuning value for, one of the following:

Returns

  • The oscillator frequency tuning setting in use.


Definition at line 11358 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningSet#

void CMU_OscillatorTuningSet (CMU_Osc_TypeDef osc, uint32_t val)

Set the oscillator frequency tuning control.

Parameters
[in]osc

An oscillator to set tuning value for, one of the following:

[in]val

The oscillator frequency tuning setting to use.

Note

  • Oscillator tuning is done during production and the tuning value is automatically loaded after reset. Changing the tuning value from the calibrated value is for more advanced use. Certain oscillators also have build-in tuning optimization.


Definition at line 11432 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningWait#

bool CMU_OscillatorTuningWait (CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode)

Wait for the oscillator tuning optimization.

Parameters
[in]osc

An oscillator to set tuning value for, one of the following:

[in]mode

Tuning optimization mode.

Returns

  • Returns false on invalid parameters or oscillator error status.


Definition at line 11561 of file platform/emlib/src/em_cmu.c

CMU_OscillatorTuningOptimize#

bool CMU_OscillatorTuningOptimize (CMU_Osc_TypeDef osc, CMU_HFXOTuningMode_TypeDef mode, bool wait)

Start and optionally wait for the oscillator tuning optimization.

Parameters
[in]osc

An oscillator to set tuning value for, one of the following:

[in]mode

Tuning optimization mode.

[in]wait

Wait for tuning optimization to complete. true - wait for tuning optimization to complete. false - return without waiting.

Returns

  • Returns false on invalid parameters or oscillator error status.


Definition at line 11627 of file platform/emlib/src/em_cmu.c

CMU_PCNTClockExternalSet#

void CMU_PCNTClockExternalSet (unsigned int instance, bool external)

Select the PCNTn clock.

Parameters
[in]instance

PCNT instance number to set selected clock source for.

[in]external

Set to true to select the external clock, false to select LFBCLK.


Definition at line 11704 of file platform/emlib/src/em_cmu.c

CMU_PCNTClockExternalGet#

bool CMU_PCNTClockExternalGet (unsigned int instance)

Determine if the currently selected PCNTn clock used is external or LFBCLK.

Parameters
[in]instance

PCNT instance number to get currently selected clock source for.

Returns

    • true - selected clock is external clock.

    • false - selected clock is LFBCLK.


Definition at line 11664 of file platform/emlib/src/em_cmu.c

CMU_UpdateWaitStates#

void CMU_UpdateWaitStates (uint32_t freq, int vscale)

Configure various wait states to switch to a certain frequency and a certain voltage scale.

Parameters
[in]freq

The core clock frequency to configure wait-states.

[in]vscale

The voltage scale to configure wait-states. Expected values are 0 or 2, higher number is lower voltage.

This function will set up the necessary flash, bus, and RAM wait states. Updating the wait state configuration must be done before increasing the clock frequency and it must be done after decreasing the clock frequency. Updating the wait state configuration must be done before core voltage is decreased and it must be done after a core voltage is increased.

  • 0 = 1.2 V (VSCALE2)

  • 2 = 1.0 V (VSCALE0)


Definition at line 6316 of file platform/emlib/src/em_cmu.c

CMU_CalibrateCont#

void CMU_CalibrateCont (bool enable)

Configure continuous calibration mode.

Parameters
[in]enable

If true, enables continuous calibration, if false disables continuous calibration.


Definition at line 3429 of file platform/emlib/inc/em_cmu.h

CMU_CalibrateStart#

void CMU_CalibrateStart (void )

Start calibration.

Parameters
N/A

Note


Definition at line 3442 of file platform/emlib/inc/em_cmu.h

CMU_CalibrateStop#

void CMU_CalibrateStop (void )

Stop the calibration counters.

Parameters
N/A

Definition at line 3452 of file platform/emlib/inc/em_cmu.h

CMU_DivToLog2#

uint32_t CMU_DivToLog2 (CMU_ClkDiv_TypeDef div)

Convert divider to logarithmic value.

Parameters
[in]div

An unscaled divider.

It only works for even numbers equal to 2^n.

Returns

  • Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.


Definition at line 3470 of file platform/emlib/inc/em_cmu.h

CMU_DPLLUnlock#

void CMU_DPLLUnlock (void )

Unlock DPLL.

Parameters
N/A

Note

  • HFRCO is not turned off.


Definition at line 3490 of file platform/emlib/inc/em_cmu.h

CMU_IntClear#

void CMU_IntClear (uint32_t flags)

Clear one or more pending CMU interrupts.

Parameters
[in]flags

CMU interrupt sources to clear.


Definition at line 3503 of file platform/emlib/inc/em_cmu.h

CMU_IntDisable#

void CMU_IntDisable (uint32_t flags)

Disable one or more CMU interrupts.

Parameters
[in]flags

CMU interrupt sources to disable.


Definition at line 3515 of file platform/emlib/inc/em_cmu.h

CMU_IntEnable#

void CMU_IntEnable (uint32_t flags)

Enable one or more CMU interrupts.

Parameters
[in]flags

CMU interrupt sources to enable.

Note

  • Depending on use case, a pending interrupt may already be set prior to enabling the interrupt. Consider using CMU_IntClear() prior to enabling if the pending interrupt should be ignored.


Definition at line 3532 of file platform/emlib/inc/em_cmu.h

CMU_IntGet#

uint32_t CMU_IntGet (void )

Get pending CMU interrupts.

Parameters
N/A

Returns

  • CMU interrupt sources pending.


Definition at line 3544 of file platform/emlib/inc/em_cmu.h

CMU_IntGetEnabled#

uint32_t CMU_IntGetEnabled (void )

Get enabled and pending CMU interrupt flags.

Parameters
N/A

Useful for handling more interrupt sources in the same interrupt handler.

Note

  • This function does not clear event bits.

Returns

  • Pending and enabled CMU interrupt sources. The return value is the bitwise AND of

    • the enabled interrupt sources in CMU_IEN and

    • the pending interrupt flags CMU_IF


Definition at line 3565 of file platform/emlib/inc/em_cmu.h

CMU_IntSet#

void CMU_IntSet (uint32_t flags)

Set one or more pending CMU interrupts.

Parameters
[in]flags

CMU interrupt sources to set to pending.


Definition at line 3580 of file platform/emlib/inc/em_cmu.h

CMU_Lock#

void CMU_Lock (void )

Lock the CMU to protect some of its registers against unintended modification.

Parameters
N/A

See the reference manual for CMU registers that will be locked.

Note

  • If locking the CMU registers, they must be unlocked prior to using any CMU API functions modifying CMU registers protected by the lock.


Definition at line 3598 of file platform/emlib/inc/em_cmu.h

CMU_Unlock#

void CMU_Unlock (void )

Unlock the CMU so that writing to locked registers again is possible.

Parameters
N/A

Definition at line 3607 of file platform/emlib/inc/em_cmu.h

CMU_PrescToLog2#

uint32_t CMU_PrescToLog2 (uint32_t presc)

Convert prescaler divider to a logarithmic value.

Parameters
[in]presc

Prescaler value used to set the frequency divider. The divider is equal to ('presc' + 1). If a divider value is passed for 'presc', 'presc' will be equal to (divider - 1).

It only works for even numbers equal to 2^n.

Returns

  • Logarithm base 2 (binary) value, i.e. exponent as used by fixed 2^n prescalers.


Definition at line 3629 of file platform/emlib/inc/em_cmu.h

auxClkGet#

static uint32_t auxClkGet (void )

Get the AUX clock frequency.

Parameters
N/A

Used by MSC flash programming and LESENSE, by default also as a debug clock.

Returns

  • AUX Frequency in Hz.


Definition at line 5742 of file platform/emlib/src/em_cmu.c

hfSrcClkGet#

static uint32_t hfSrcClkGet (void )

Get the HFSRCCLK frequency.

Parameters
N/A

Returns

  • HFSRCCLK Frequency in Hz.


Definition at line 5810 of file platform/emlib/src/em_cmu.c

dbgClkGet#

static uint32_t dbgClkGet (void )

Get the Debug Trace clock frequency.

Parameters
N/A

Returns

  • Debug Trace frequency in Hz.


Definition at line 5827 of file platform/emlib/src/em_cmu.c

adcAsyncClkGet#

static uint32_t adcAsyncClkGet (uint32_t adc)

Get the ADC n asynchronous clock frequency.

Parameters
N/Aadc

Returns

  • ADC n asynchronous frequency in Hz.


Definition at line 5860 of file platform/emlib/src/em_cmu.c

flashWaitStateControl#

static void flashWaitStateControl (uint32_t coreFreq, int vscale)

Configure flash access wait states to support the given core clock frequency.

Parameters
[in]coreFreq

The core clock frequency to configure flash wait-states.

[in]vscale

Voltage Scale level. Supported levels are 0 and 2 where 0 is the default.


Definition at line 6098 of file platform/emlib/src/em_cmu.c

flashWaitStateMax#

static void flashWaitStateMax (void )

Configure flash access wait states to the most conservative setting for this target.

Parameters
N/A

Retain SCBTP (Suppressed Conditional Branch Target Prefetch) setting.


Definition at line 6207 of file platform/emlib/src/em_cmu.c

getRegIshUpperVal#

static uint32_t getRegIshUpperVal (uint32_t steadyStateRegIsh)

Return the upper value for CMU_HFXOSTEADYSTATECTRL_REGISH.

Parameters
N/AsteadyStateRegIsh

Definition at line 6340 of file platform/emlib/src/em_cmu.c

getHfxoTuningMode#

uint32_t getHfxoTuningMode (void )

Get the HFXO tuning mode.

Parameters
N/A

Returns

  • The current HFXO tuning mode from the HFXOCTRL register.


Definition at line 6360 of file platform/emlib/src/em_cmu.c

setHfxoTuningMode#

void setHfxoTuningMode (uint32_t mode)

Set the HFXO tuning mode.

Parameters
[in]mode

The new HFXO tuning mode. This can be HFXO_TUNING_MODE_AUTO or HFXO_TUNING_MODE_CMD.


Definition at line 6379 of file platform/emlib/src/em_cmu.c

lfClkGet#

static uint32_t lfClkGet (CMU_Clock_TypeDef lfClkBranch)

Get the LFnCLK frequency based on the current configuration.

Parameters
[in]lfClkBranch

Selected LF branch.

Returns

  • The LFnCLK frequency in Hz. If no LFnCLK is selected (disabled), 0 is returned.


Definition at line 6402 of file platform/emlib/src/em_cmu.c

syncReg#

void syncReg (uint32_t mask)

Wait for an ongoing sync of register(s) to low-frequency domain to complete.

Parameters
[in]mask

A bitmask corresponding to SYNCBUSY register defined bits, indicating registers that must complete any ongoing synchronization.


Definition at line 6564 of file platform/emlib/src/em_cmu.c

hfperClkSafePrescaler#

static void hfperClkSafePrescaler (void )

Set HFPER clock tree prescalers to safe values.

Parameters
N/A

Note

  • This function applies to EFM32GG11B. There are 3 HFPER clock trees with these frequency limits: HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode.


Definition at line 6629 of file platform/emlib/src/em_cmu.c

hfperClkOptimizedPrescaler#

static void hfperClkOptimizedPrescaler (void )

Set HFPER clock tree prescalers to give highest possible clock node frequency while still beeing within spec.

Parameters
N/A

Note

  • This function applies to EFM32GG11B. There are 3 HFPER clock trees with these frequency limits: HFPERCLK (A-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode. HFPERBCLK (B-tree): 20MHz in VSCALE0 mode, 72MHz in VSCALE2 mode. HFPERCCLK (C-tree): 20MHz in VSCALE0 mode, 50MHz in VSCALE2 mode.


Definition at line 6652 of file platform/emlib/src/em_cmu.c

CMU_AUXHFRCODevinfoGet#

static uint32_t CMU_AUXHFRCODevinfoGet (CMU_AUXHFRCOFreq_TypeDef freq)

Get the AUXHFRCO frequency calibration word in DEVINFO.

Parameters
[in]freq

Frequency in Hz.

Returns

  • AUXHFRCO calibration word for a given frequency.


Definition at line 6777 of file platform/emlib/src/em_cmu.c

CMU_HFRCODevinfoGet#

static uint32_t CMU_HFRCODevinfoGet (CMU_HFRCOFreq_TypeDef freq)

Get the HFRCO frequency calibration word in DEVINFO.

Parameters
[in]freq

Frequency in Hz.

Returns

  • HFRCO calibration word for a given frequency.


Definition at line 10493 of file platform/emlib/src/em_cmu.c

Macro Definition Documentation#

CMU_CLOCK_SELECT_SET#

#define CMU_CLOCK_SELECT_SET
Value:
(clock, sel)

Macro to set clock sources in the clock tree.


Definition at line 55 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_1#

#define cmuClkDiv_1
Value:
1

Clock divisors.

These values are valid for prescalers. Divide clock by 1.


Definition at line 1820 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_2#

#define cmuClkDiv_2
Value:
2

Divide clock by 2.


Definition at line 1821 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_4#

#define cmuClkDiv_4
Value:
4

Divide clock by 4.


Definition at line 1822 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_8#

#define cmuClkDiv_8
Value:
8

Divide clock by 8.


Definition at line 1823 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_16#

#define cmuClkDiv_16
Value:
16

Divide clock by 16.


Definition at line 1824 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_32#

#define cmuClkDiv_32
Value:
32

Divide clock by 32.


Definition at line 1825 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_64#

#define cmuClkDiv_64
Value:
64

Divide clock by 64.


Definition at line 1826 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_128#

#define cmuClkDiv_128
Value:
128

Divide clock by 128.


Definition at line 1827 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_256#

#define cmuClkDiv_256
Value:
256

Divide clock by 256.


Definition at line 1828 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_512#

#define cmuClkDiv_512
Value:
512

Divide clock by 512.


Definition at line 1829 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_1024#

#define cmuClkDiv_1024
Value:
1024

Divide clock by 1024.


Definition at line 1830 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_2048#

#define cmuClkDiv_2048
Value:
2048

Divide clock by 2048.


Definition at line 1831 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_4096#

#define cmuClkDiv_4096
Value:
4096

Divide clock by 4096.


Definition at line 1832 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_8192#

#define cmuClkDiv_8192
Value:
8192

Divide clock by 8192.


Definition at line 1833 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_16384#

#define cmuClkDiv_16384
Value:
16384

Divide clock by 16384.


Definition at line 1834 of file platform/emlib/inc/em_cmu.h

cmuClkDiv_32768#

#define cmuClkDiv_32768
Value:
32768

Divide clock by 32768.


Definition at line 1835 of file platform/emlib/inc/em_cmu.h

CMU_HFRCO_MIN#

#define CMU_HFRCO_MIN
Value:
cmuHFRCOFreq_1M0Hz

HFRCO minimum frequency.


Definition at line 1927 of file platform/emlib/inc/em_cmu.h

CMU_HFRCO_MAX#

#define CMU_HFRCO_MAX
Value:
cmuHFRCOFreq_38M0Hz

HFRCO maximum frequency.


Definition at line 1942 of file platform/emlib/inc/em_cmu.h

CMU_AUXHFRCO_MIN#

#define CMU_AUXHFRCO_MIN
Value:
cmuAUXHFRCOFreq_1M0Hz

AUXHFRCO minimum frequency.


Definition at line 1968 of file platform/emlib/inc/em_cmu.h

CMU_AUXHFRCO_MAX#

#define CMU_AUXHFRCO_MAX
Value:
cmuAUXHFRCOFreq_38M0Hz

AUXHFRCO maximum frequency.


Definition at line 1977 of file platform/emlib/inc/em_cmu.h

CMU_LFXOINIT_DEFAULT#

#define CMU_LFXOINIT_DEFAULT
Value:
{ \
_CMU_LFXOCTRL_TUNING_DEFAULT, /* Default CTUNE value, 0 */ \
_CMU_LFXOCTRL_GAIN_DEFAULT, /* Default gain, 2 */ \
_CMU_LFXOCTRL_TIMEOUT_DEFAULT, /* Default start-up delay, 32 K cycles */ \
cmuOscMode_Crystal, /* Crystal oscillator */ \
}

Default LFXO initialization values.


Definition at line 3112 of file platform/emlib/inc/em_cmu.h

CMU_LFXOINIT_EXTERNAL_CLOCK#

#define CMU_LFXOINIT_EXTERNAL_CLOCK
Value:
{ \
0, /* No CTUNE value needed */ \
0, /* No LFXO startup gain */ \
_CMU_LFXOCTRL_TIMEOUT_2CYCLES, /* Minimal lfxo start-up delay, 2 cycles */ \
cmuOscMode_External, /* External digital clock */ \
}

Default LFXO initialization for external clock.


Definition at line 3120 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_DEFAULT#

#define CMU_HFXOINIT_DEFAULT
Value:
{ \
false, /* Low-noise mode for EFR32 */ \
false, /* @deprecated no longer in use */ \
false, /* @deprecated no longer in use */ \
false, /* @deprecated no longer in use */ \
_CMU_HFXOSTARTUPCTRL_CTUNE_DEFAULT, \
_CMU_HFXOSTEADYSTATECTRL_CTUNE_DEFAULT, \
0xA, /* Default Shunt steady-state current */ \
0x20, /* Matching errata fix in @ref CHIP_Init() */ \
0x7, /* Recommended steady-state XO core bias current */ \
0x6, /* Recommended peak detection threshold */ \
0x2, /* Recommended shunt optimization timeout */ \
0xA, /* Recommended peak detection timeout */ \
0x4, /* Recommended steady timeout */ \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_DEFAULT, \
cmuOscMode_Crystal, \
}

Default HFXO initialization values for Platform 2 devices, which contain a separate HFXOCTRL register.


Definition at line 3210 of file platform/emlib/inc/em_cmu.h

CMU_HFXOINIT_EXTERNAL_CLOCK#

#define CMU_HFXOINIT_EXTERNAL_CLOCK
Value:
{ \
true, /* Low-power mode */ \
false, /* @deprecated no longer in use */ \
false, /* @deprecated no longer in use */ \
false, /* @deprecated no longer in use */ \
0, /* Startup CTUNE=0 recommended for external clock */ \
0, /* Steady CTUNE=0 recommended for external clock */ \
0xA, /* Default shunt steady-state current */ \
0, /* Startup IBTRIMXOCORE=0 recommended for external clock */ \
0, /* Steady IBTRIMXOCORE=0 recommended for external clock */ \
0x6, /* Recommended peak detection threshold */ \
0x2, /* Recommended shunt optimization timeout */ \
0x0, /* Peak-detect not recommended for external clock usage */ \
_CMU_HFXOTIMEOUTCTRL_STEADYTIMEOUT_2CYCLES, /* Minimal steady timeout */ \
_CMU_HFXOTIMEOUTCTRL_STARTUPTIMEOUT_2CYCLES, /* Minimal startup timeout */ \
cmuOscMode_External, \
}

Init of HFXO with external clock.


Definition at line 3249 of file platform/emlib/inc/em_cmu.h

CMU_DPLL_LFXO_TO_40MHZ#

#define CMU_DPLL_LFXO_TO_40MHZ
Value:
{ \
39998805, /* Target frequency. */ \
3661, /* Factor N. */ \
2, /* Factor M. */ \
0, /* No spread spectrum clocking. */ \
0, /* No spread spectrum clocking. */ \
cmuDPLLClkSel_Lfxo, /* Select LFXO as reference clock. */ \
cmuDPLLEdgeSel_Fall, /* Select falling edge of ref clock. */ \
cmuDPLLLockMode_Freq, /* Use frequency lock mode. */ \
true /* Enable automatic lock recovery. */ \
}

DPLL initialization values for 39,998,805 Hz using LFXO as reference clock, M=2 and N=3661.


Definition at line 3307 of file platform/emlib/inc/em_cmu.h