External memory bank for driving display.

Width.

Color source for masking and alpha blending.

Bus Interleave mode.

Trigger for updating frame buffer pointer.

Drive DCLK from negative clock edge of internal clock.

Masking and alpha blending mode.

TFT Direct Drive mode.

TFT Polarity for Chip Select (CS) Line.

TFT Polarity for Data Clock (DCLK) Line.

TFT Polarity for Data Enable (DATAEN) Line.

TFT Polarity for Horizontal Sync (HSYNC) Line.

TFT Polarity for Vertical Sync (VSYNC) Line.

Horizontal size in pixels.

Horizontal Front Porch Size.

Horizontal Back Porch Size.

Horizontal Synchronization Pulse Width.

Vertical size in pixels.

Vertical Front Porch Size.

Vertical Back Porch Size.

Vertical Synchronization Pulse Width.

TFT Frame Buffer address, offset to EBI bank base address.

TFT DCLK period in internal cycles.

Starting position of External Direct Drive relative to DCLK inactive edge.

Number of cycles RGB data is driven before active edge of DCLK.

Number of cycles RGB data is held after active edge of DCLK.