CORE - Interrupt Handling#
Warnings
If you are looking for atomic and critical sections, they have been moved to platform/common in the Core API.
Introduction#
This module provides support for NVIC sections. NVIC sections are like critical sections, except interrupts are masked on an individual IRQ basis. This module also provides an API to relocate the vector table in RAM, and register IRQ handlers in the RAM based interrupt vector table.
NVIC mask section: Mask interrupts (external interrupts) on an individual IRQ basis.
Examples#
Implement an NVIC critical section:
{
CORE_DECLARE_NVIC_ZEROMASK(mask); // A zero initialized NVIC disable mask
// Set mask bits for IRQs to block in the NVIC critical section.
// In many cases, you can create the disable mask once upon application
// startup and use the mask globally throughout the application lifetime.
CORE_NvicMaskSetIRQ(LEUART0_IRQn, &mask);
CORE_NvicMaskSetIRQ(VCMP_IRQn, &mask);
// Enter NVIC critical section with the disable mask
CORE_NVIC_SECTION(&mask,
...
... your code goes here ...
...
)
}
Interrupt vector tables#
When using RAM based interrupt vector tables it is the user's responsibility to allocate the table space correctly. The tables must be aligned as specified in the CPU reference manual.
Use CORE_InitNvicVectorTable() to initialize a RAM based vector table by copying table entries from a source vector table to a target table. VTOR is set to the address of the target vector table.
Use CORE_GetNvicRamTableHandler()CORE_SetNvicRamTableHandler() to get or set the interrupt handler for a specific IRQn. They both use the interrupt vector table defined by the current VTOR register value.
Modules#
Functions#
Check if a specific interrupt is disabled or blocked.
Get the current NVIC enable mask state.
Get NVIC disable state for a given mask.
Enter a NVIC mask section.
Disable NVIC interrupts.
Set current NVIC interrupt enable mask.
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
Utility function to set an IRQn bit in a NVIC enable/disable mask.
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
Check if an NVIC interrupt is disabled.
Utility function to get the handler for a specific interrupt.
Utility function to set the handler for a specific interrupt.
Initialize an interrupt vector table by copying table entries from a source to a target table.
Macros#
Number of words in a NVIC mask set.
Number of entries in a default interrupt vector table.
Highest priority for core interrupt.
Default priority for core interrupt.
Lowest priority for core interrupt.
Allocate storage for NVIC interrupt masks for use by CORE_ENTER/EXIT_NVIC() macros.
Allocate storage for NVIC interrupt masks.
Allocate storage for and zero initialize NVIC interrupt mask.
NVIC mask style interrupt disable.
NVIC mask style interrupt enable.
Convenience macro for implementing a NVIC mask section.
Enter NVIC mask section.
Exit NVIC mask section.
NVIC maks style yield.
Function Documentation#
CORE_IrqIsBlocked#
bool CORE_IrqIsBlocked (IRQn_Type irqN)
Check if a specific interrupt is disabled or blocked.
| [in] | irqN | The IRQn_Type enumerator for the interrupt to check. |
Returns
True if the interrupt is disabled or blocked.
476 of file platform/emlib/src/em_core.cCORE_GetNvicEnabledMask#
void CORE_GetNvicEnabledMask (CORE_nvicMask_t * mask)
Get the current NVIC enable mask state.
| [out] | mask | The current NVIC enable mask. |
258 of file platform/emlib/src/em_core.cCORE_GetNvicMaskDisableState#
bool CORE_GetNvicMaskDisableState (const CORE_nvicMask_t * mask)
Get NVIC disable state for a given mask.
| [in] | mask | An NVIC mask to check. |
Returns
True if all NVIC interrupt mask bits are clear.
277 of file platform/emlib/src/em_core.cCORE_EnterNvicMask#
void CORE_EnterNvicMask (CORE_nvicMask_t * nvicState, const CORE_nvicMask_t * disable)
Enter a NVIC mask section.
| [out] | nvicState | Return NVIC interrupts enable mask prior to section entry. |
| [in] | disable | A mask specifying which NVIC interrupts to disable within the section. |
When a NVIC mask section is entered, specified NVIC interrupts are disabled.
111 of file platform/emlib/src/em_core.cCORE_NvicDisableMask#
void CORE_NvicDisableMask (const CORE_nvicMask_t * disable)
Disable NVIC interrupts.
| [in] | disable | A mask specifying which NVIC interrupts to disable. |
129 of file platform/emlib/src/em_core.cCORE_NvicEnableMask#
void CORE_NvicEnableMask (const CORE_nvicMask_t * enable)
Set current NVIC interrupt enable mask.
| [out] | enable | A mask specifying which NVIC interrupts are currently enabled. |
145 of file platform/emlib/src/em_core.cCORE_YieldNvicMask#
void CORE_YieldNvicMask (const CORE_nvicMask_t * enable)
Brief NVIC interrupt enable/disable sequence to allow handling of pending interrupts.
| [in] | enable | A mask specifying which NVIC interrupts to briefly enable. |
Note
Usually used within an NVIC mask section.
165 of file platform/emlib/src/em_core.cCORE_NvicMaskSetIRQ#
void CORE_NvicMaskSetIRQ (IRQn_Type irqN, CORE_nvicMask_t * mask)
Utility function to set an IRQn bit in a NVIC enable/disable mask.
| [in] | irqN | The IRQn_Type enumerator for the interrupt. |
| [inout] | mask | The mask to set the interrupt bit in. |
222 of file platform/emlib/src/em_core.cCORE_NvicMaskClearIRQ#
void CORE_NvicMaskClearIRQ (IRQn_Type irqN, CORE_nvicMask_t * mask)
Utility function to clear an IRQn bit in a NVIC enable/disable mask.
| [in] | irqN | The IRQn_Type enumerator for the interrupt. |
| [inout] | mask | The mask to clear the interrupt bit in. |
243 of file platform/emlib/src/em_core.cCORE_NvicIRQDisabled#
bool CORE_NvicIRQDisabled (IRQn_Type irqN)
Check if an NVIC interrupt is disabled.
| [in] | irqN | The IRQn_Type enumerator for the interrupt to check. |
Returns
True if the interrupt is disabled.
333 of file platform/emlib/src/em_core.cCORE_GetNvicRamTableHandler#
void * CORE_GetNvicRamTableHandler (IRQn_Type irqN)
Utility function to get the handler for a specific interrupt.
| [in] | irqN | The IRQn_Type enumerator for the interrupt. |
Returns
The handler address.
Note
Uses the interrupt vector table defined by the current VTOR register value.
353 of file platform/emlib/src/em_core.cCORE_SetNvicRamTableHandler#
void CORE_SetNvicRamTableHandler (IRQn_Type irqN, void * handler)
Utility function to set the handler for a specific interrupt.
| [in] | irqN | The IRQn_Type enumerator for the interrupt. |
| [in] | handler | The handler address. |
Note
Uses the interrupt vector table defined by the current VTOR register value.
376 of file platform/emlib/src/em_core.cCORE_InitNvicVectorTable#
void CORE_InitNvicVectorTable (uint32_t * sourceTable, uint32_t sourceSize, uint32_t * targetTable, uint32_t targetSize, void * defaultHandler, bool overwriteActive)
Initialize an interrupt vector table by copying table entries from a source to a target table.
| [in] | sourceTable | The address of the source vector table. |
| [in] | sourceSize | A number of entries in the source vector table. |
| [in] | targetTable | The address of the target (new) vector table. |
| [in] | targetSize | A number of entries in the target vector table. |
| [in] | defaultHandler | An address of the interrupt handler used for target entries for which where there is no corresponding source entry (i.e., the target table is larger than the source table). |
| [in] | overwriteActive | When true, a target table entry is always overwritten with the corresponding source entry. If false, a target table entry is only overwritten if it is zero. This makes it possible for an application to partly initialize a target table before passing it to this function. |
Note
This function will set a new VTOR register value.
413 of file platform/emlib/src/em_core.cMacro Definition Documentation#
CORE_NVIC_REG_WORDS#
#define CORE_NVIC_REG_WORDSValue:
((EXT_IRQ_COUNT + 31) / 32)
Number of words in a NVIC mask set.
47 of file platform/emlib/inc/em_core.hCORE_DEFAULT_VECTOR_TABLE_ENTRIES#
#define CORE_DEFAULT_VECTOR_TABLE_ENTRIESValue:
(EXT_IRQ_COUNT + 16)
Number of entries in a default interrupt vector table.
50 of file platform/emlib/inc/em_core.hCORE_INTERRUPT_HIGHEST_PRIORITY#
#define CORE_INTERRUPT_HIGHEST_PRIORITYValue:
0
Highest priority for core interrupt.
53 of file platform/emlib/inc/em_core.hCORE_INTERRUPT_DEFAULT_PRIORITY#
#define CORE_INTERRUPT_DEFAULT_PRIORITYValue:
5
Default priority for core interrupt.
56 of file platform/emlib/inc/em_core.hCORE_INTERRUPT_LOWEST_PRIORITY#
#define CORE_INTERRUPT_LOWEST_PRIORITYValue:
7
Lowest priority for core interrupt.
59 of file platform/emlib/inc/em_core.hCORE_DECLARE_NVIC_STATE#
#define CORE_DECLARE_NVIC_STATEValue:
CORE_nvicMask_t nvicState
Allocate storage for NVIC interrupt masks for use by CORE_ENTER/EXIT_NVIC() macros.
80 of file platform/emlib/inc/em_core.hCORE_DECLARE_NVIC_MASK#
#define CORE_DECLARE_NVIC_MASKValue:
(x)
Allocate storage for NVIC interrupt masks.
85 of file platform/emlib/inc/em_core.hCORE_DECLARE_NVIC_ZEROMASK#
#define CORE_DECLARE_NVIC_ZEROMASKValue:
(x)
Allocate storage for and zero initialize NVIC interrupt mask.
90 of file platform/emlib/inc/em_core.hCORE_NVIC_DISABLE#
#define CORE_NVIC_DISABLEValue:
(mask)
NVIC mask style interrupt disable.
95 of file platform/emlib/inc/em_core.hCORE_NVIC_ENABLE#
#define CORE_NVIC_ENABLEValue:
(mask)
NVIC mask style interrupt enable.
100 of file platform/emlib/inc/em_core.hCORE_NVIC_SECTION#
#define CORE_NVIC_SECTIONValue:
Convenience macro for implementing a NVIC mask section.
107 of file platform/emlib/inc/em_core.hCORE_ENTER_NVIC#
#define CORE_ENTER_NVICValue:
(disable)
Enter NVIC mask section.
Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
121 of file platform/emlib/inc/em_core.hCORE_EXIT_NVIC#
#define CORE_EXIT_NVICValue:
()
Exit NVIC mask section.
Assumes that a CORE_DECLARE_NVIC_STATE exist in scope.
125 of file platform/emlib/inc/em_core.hCORE_YIELD_NVIC#
#define CORE_YIELD_NVICValue:
(enable)
NVIC maks style yield.
130 of file platform/emlib/inc/em_core.h