EUSART - Enhanced USART#
Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter.
Introduction#
This module contains functions to control the Enhanced Universal Synchronous / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, therefore, be connected to an external transceiver to communicate with another host using the serial link.
It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, and IrDA devices.
EUSART has a wide selection of operating modes, frame formats, and baud rates. All features are supported through the API of this module.
This module does not support DMA configuration. UARTDRV and SPIDRV drivers provide full support for DMA and more.
Example#
EUSART Asynchronous UART TX example:
{
#define GPIO_TX PB0
sl_hal_eusart_uart_init_t init = SL_HAL_EUSART_UART_INIT_DEFAULT_HF;
// Configure the clocks.
sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_EUSART0);
sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
// Calculate and configure the eusart's clock divider.
uint32_t baudrate = 38400; // Desired baudrate.
sl_clock_branch_t clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_EUSART0);
uint32_t freq;
sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq);
init.clock_div = sl_hal_eusart_uart_calculate_clock_div(freq, baudrate, init.oversampling);
// Configure the EUSART port.
sl_gpio_set_pin_mode(GPIO_TX, SL_GPIO_MODE_PUSH_PULL, 0);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].TXROUTE = (GPIO_TX->port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
| (GPIO_TX->pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN;
// Initialize the EUSART.
sl_hal_eusart_init_uart_hf(EUSART0, &init);
sl_hal_eusart_enable(EUSART0);
sl_hal_eusart_enable_tx(EUSART0);
uint16_t data = 0xFF;
sl_hal_eusart_tx(EUSART0, data);
}
EUSART Synchronous SPI Initialization example:
{
#define GPIO_MOSI PC0
#define GPIO_MISO PC1
#define GPIO_SCLK PC2
sl_hal_eusart_spi_init_t init = SL_HAL_EUSART_SPI_MASTER_INIT_DEFAULT_HF;
// Clock idle low, sample on falling edge.
init.clock_mode = SL_HAL_EUSART_CLOCK_MODE_1;
// Configure the clocks.
sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_EUSART1);
sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);
// Calculate and configure the eusart's clock divider.
uint32_t baudrate = 1000000; // Desired baudrate.
sl_clock_branch_t clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_EUSART1);
uint32_t freq;
sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq);
init.clock_div = sl_hal_eusart_spi_calculate_clock_div(freq, baudrate);
// Configure the SPI ports.
sl_gpio_set_pin_mode(GPIO_MOSI, SL_GPIO_MODE_PUSH_PULL, 0);
sl_gpio_set_pin_mode(GPIO_MISO, SL_GPIO_MODE_INPUT, 0);
sl_gpio_set_pin_mode(GPIO_SCLK, SL_GPIO_MODE_PUSH_PULL, 0);
// Connect EUSART to ports.
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (GPIO_MOSI->port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
| (GPIO_MOSI->pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (GPIO_MISO->port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
| (GPIO_MISO->pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (GPIO_SCLK->port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
| (GPIO_SCLK->pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_RXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;
// Initialize the EUSART.
sl_hal_eusart_init_spi(EUSART1, &init);
sl_hal_eusart_enable(EUSART1);
sl_hal_eusart_enable_rx(EUSART1);
sl_hal_eusart_enable_tx(EUSART1);
}
Modules#
sl_hal_eusart_uart_advanced_init_t
sl_hal_eusart_spi_advanced_init_t
Enumerations#
Data bit selection.
Parity selection.
Stop bits selection.
Oversampling selection, used for asynchronous operation.
Loopback enable.
Majority vote enable.
Hardware flow control configuration.
IO polarity selection.
Auto TX delay transmission.
FIFO Interrupt and Status Watermark.
IrDA frequency mode (high/low frequency).
Pulse width selection for IrDA mode.
Chip select assertion/de-assertion time.
Inter-character spacing after each TX frame while TX FIFO is not empty.
Chip select polarity.
Clock polarity/phase mode.
Functions#
Initialize EUSART when used in UART mode with the high frequency clock.
Initialize EUSART when used in UART mode with the low frequency clock.
Initialize EUSART when used in IrDA mode with the high or low frequency clock.
Initialize EUSART when used in SPI mode.
Configure EUSART to its reset state.
Receive one 8 bits frame, (or part of 9 bit frame).
Receive one 8-16 bit frame with extended information.
Transmit one 8 bits frame.
Transmit one 8-9 bit frame with extended control.
Transmit one 8-16 bit frame and return received data.
Calculate SPI clock divider using given reference frequency and baudrate.
Calculate UART clock divider using given reference frequency, oversampling and baudrate.
Get the calculated baudrate from the current EUSART configuration and clock.
Get the calculated baudrate from the current EUSART configuration and clock.
Wait for ongoing sync of register(s) to the low-frequency domain to complete.
Enable EUSART.
Disable EUSART.
Wait for disabling to finish.
Enable EUSART receiver.
Disable EUSART receiver.
Enable EUSART transmitter.
Disable EUSART transmitter.
Enable reception operation until the configured start frame is received.
Disable reception operation until the configured start frame is received.
Enable the tristating of the transmitter output.
Disable the tristating of the transmitter output.
Clear RX FIFO.
Clear TX FIFO.
Get EUSART STATUS register.
Set UART mode clock divider.
Get UART mode clock divider.
Get UART mode oversampling value.
Clear one or more pending EUSART interrupts.
Disable one or more EUSART interrupts.
Enable one or more EUSART interrupts.
Get pending EUSART interrupt flags.
Get enabled and pending EUSART interrupt flags.
Set one or more pending EUSART interrupts from SW.
Macros#
Check if EUSART insance is valid.
Default configuration for EUSART initialization structure in UART mode with high-frequency clock.
Default configuration for EUSART initialization structure in UART mode with low-frequency clock.
Default configuration for EUSART advanced initialization structure in UART mode..
Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.
Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.
Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.
Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.
Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.
Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.
Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.
Enumeration Documentation#
sl_hal_eusart_data_bits_t#
sl_hal_eusart_data_bits_t
Data bit selection.
Enumerator | |
---|---|
SL_HAL_EUSART_DATA_BITS_7 | 7 data bits. |
SL_HAL_EUSART_DATA_BITS_8 | 8 data bits. |
SL_HAL_EUSART_DATA_BITS_9 | 9 data bits. |
SL_HAL_EUSART_DATA_BITS_10 | 10 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_11 | 11 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_12 | 12 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_13 | 13 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_14 | 14 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_15 | 15 data bits, SPI mode only. |
SL_HAL_EUSART_DATA_BITS_16 | 16 data bits, SPI mode only. |
sl_hal_eusart_parity_t#
sl_hal_eusart_parity_t
Parity selection.
Enumerator | |
---|---|
SL_HAL_EUSART_NO_PARITY | No parity. |
SL_HAL_EUSART_EVEN_PARITY | Even parity. |
SL_HAL_EUSART_ODD_PARITY | Odd parity. |
sl_hal_eusart_stop_bits_t#
sl_hal_eusart_stop_bits_t
Stop bits selection.
Enumerator | |
---|---|
SL_HAL_EUSART_STOP_BITS_0P5 | 0.5 stop bits. |
SL_HAL_EUSART_STOP_BITS_1P5 | 1.5 stop bits. |
SL_HAL_EUSART_STOP_BITS_1 | 1 stop bits. |
SL_HAL_EUSART_STOP_BITS_2 | 2 stop bits. |
sl_hal_eusart_ovs_t#
sl_hal_eusart_ovs_t
Oversampling selection, used for asynchronous operation.
Enumerator | |
---|---|
SL_HAL_EUSART_OVS_16 | 16x oversampling (normal). |
SL_HAL_EUSART_OVS_8 | 8x oversampling. |
SL_HAL_EUSART_OVS_6 | 6x oversampling. |
SL_HAL_EUSART_OVS_4 | 4x oversampling. |
SL_HAL_EUSART_OVS_0 | Oversampling disabled. |
sl_hal_eusart_loopback_t#
sl_hal_eusart_loopback_t
Loopback enable.
Enumerator | |
---|---|
SL_HAL_EUSART_LOOPBACK_ENABLE | Enable loopback. |
SL_HAL_EUSART_LOOPBACK_DISABLE | Disable loopback. |
sl_hal_eusart_majority_vote_t#
sl_hal_eusart_majority_vote_t
Majority vote enable.
Enumerator | |
---|---|
SL_HAL_EUSART_MAJORITY_VOTE_ENABLE | Enable majority vote for 16x, 8x and 6x oversampling modes. |
SL_HAL_EUSART_MAJORITY_VOTE_DISABLE | Disable majority vote for 16x, 8x and 6x oversampling modes. |
sl_hal_eusart_hw_flow_control_t#
sl_hal_eusart_hw_flow_control_t
Hardware flow control configuration.
Enumerator | |
---|---|
SL_HAL_EUSART_HW_FLOW_CONTROL_NONE | No Hardware Flow Control. |
SL_HAL_EUSART_HW_FLOW_CONTROL_CTS | CTS Hardware Flow Control. |
SL_HAL_EUSART_HW_FLOW_CONTROL_RTS | RTS Hardware Flow Control. |
SL_HAL_EUSART_HW_FLOW_CONTROL_CTS_RTS | CTS and RTS Hardware Flow Control. |
sl_hal_eusart_invert_io_t#
sl_hal_eusart_invert_io_t
IO polarity selection.
Enumerator | |
---|---|
SL_HAL_EUSART_INVERT_IO_DISABLE | Disable inversion on both RX and TX signals. |
SL_HAL_EUSART_INVERT_IO_RX_ENABLE | Invert RX signal, before receiver. |
SL_HAL_EUSART_INVERT_IO_TX_ENABLE | Invert TX signal, after transmitter. |
SL_HAL_EUSART_INVERT_IO_RXTX_ENABLE | Enable trigger on both receive and transmit. |
sl_hal_eusart_auto_tx_delay_t#
sl_hal_eusart_auto_tx_delay_t
Auto TX delay transmission.
Enumerator | |
---|---|
SL_HAL_EUSART_AUTO_TX_DELAY_NONE | Frames are transmitted immediately. |
SL_HAL_EUSART_AUTO_TX_DELAY_SINGLE | Transmission of new frames is delayed by a single bit period. |
SL_HAL_EUSART_AUTO_TX_DELAY_DOUBLE | Transmission of new frames is delayed by a two bit periods. |
SL_HAL_EUSART_AUTO_TX_DELAY_TRIPPLE | Transmission of new frames is delayed by a three bit periods. |
sl_hal_eusart_fifo_interrupt_watermark_t#
sl_hal_eusart_fifo_interrupt_watermark_t
FIFO Interrupt and Status Watermark.
Enumerator | |
---|---|
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ONE | Interrupt and status level are set after 1 frame. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWO | Interrupt and status level are set after 2 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THREE | Interrupt and status level are set after 3 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOUR | Interrupt and status level are set after 4 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIVE | Interrupt and status level are set after 5 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIX | Interrupt and status level are set after 6 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SEVEN | Interrupt and status level are set after 7 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_EIGHT | Interrupt and status level are set after 8 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_NINE | Interrupt and status level are set after 9 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TEN | Interrupt and status level are set after 10 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ELEVEN | Interrupt and status level are set after 11 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWELVE | Interrupt and status level are set after 12 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THIRTEEN | Interrupt and status level are set after 13 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOURTEEN | Interrupt and status level are set after 14 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIFTEEN | Interrupt and status level are set after 15 frames. |
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIXTEEN | Interrupt and status level are set after 16 frames. |
sl_hal_eusart_irda_frequency_mode_t#
sl_hal_eusart_irda_frequency_mode_t
IrDA frequency mode (high/low frequency).
Enumerator | |
---|---|
SL_HAL_EUSART_IRDA_MODE_HF | High frequency mode. |
SL_HAL_EUSART_IRDA_MODE_LF | Low frequency mode. |
sl_hal_eusart_irda_pulse_width_t#
sl_hal_eusart_irda_pulse_width_t
Pulse width selection for IrDA mode.
Enumerator | |
---|---|
SL_HAL_EUSART_PULSE_WIDTH_ONE | IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8. |
SL_HAL_EUSART_PULSE_WIDTH_TWO | IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8. |
SL_HAL_EUSART_PULSE_WIDTH_THREE | IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8. |
SL_HAL_EUSART_PULSE_WIDTH_FOUR | IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8. |
sl_hal_eusart_cs_time_t#
sl_hal_eusart_cs_time_t
Chip select assertion/de-assertion time.
Enumerator | |
---|---|
SL_HAL_EUSART_CS_TIME_ZERO | Chip select is asserted/de-asserted half or 1 baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_ONE | Chip select is asserted/de-asserted 1 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_TWO | Chip select is asserted/de-asserted 2 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_THREE | Chip select is asserted/de-asserted 3 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_FOUR | Chip select is asserted/de-asserted 4 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_FIVE | Chip select is asserted/de-asserted 5 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_SIX | Chip select is asserted/de-asserted 6 additional baud-time before transmission. |
SL_HAL_EUSART_CS_TIME_SEVEN | Chip select is asserted/de-asserted 7 additional baud-time before transmission. |
sl_hal_eusart_inter_character_space_t#
sl_hal_eusart_inter_character_space_t
Inter-character spacing after each TX frame while TX FIFO is not empty.
Enumerator | |
---|---|
SL_HAL_EUSART_ICS_TIME_ZERO | There is no space between characters.. |
SL_HAL_EUSART_ICS_TIME_ONE | Create a space on 1 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_TWO | Create a space on 2 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_THREE | Create a space on 3 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_FOUR | Create a space on 4 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_FIVE | Create a space on 5 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_SIX | Create a space on 6 baud-times between frames. |
SL_HAL_EUSART_ICS_TIME_SEVEN | Create a space on 7 baud-times between frames. |
sl_hal_eusart_cs_polarity_t#
sl_hal_eusart_cs_polarity_t
Chip select polarity.
Enumerator | |
---|---|
SL_HAL_EUSART_CS_ACTIVE_LOW | Chip select active low. |
SL_HAL_EUSART_CS_ACTIVE_HIGH | Chip select active high. |
sl_hal_eusart_clock_mode_t#
sl_hal_eusart_clock_mode_t
Clock polarity/phase mode.
Enumerator | |
---|---|
SL_HAL_EUSART_CLOCK_MODE_0 | Clock idle low, sample on rising edge. |
SL_HAL_EUSART_CLOCK_MODE_1 | Clock idle low, sample on falling edge. |
SL_HAL_EUSART_CLOCK_MODE_2 | Clock idle high, sample on falling edge. |
SL_HAL_EUSART_CLOCK_MODE_3 | Clock idle high, sample on rising edge. |
Function Documentation#
sl_hal_eusart_init_uart_hf#
void sl_hal_eusart_init_uart_hf (EUSART_TypeDef * eusart, const sl_hal_eusart_uart_init_t * init)
Initialize EUSART when used in UART mode with the high frequency clock.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
const sl_hal_eusart_uart_init_t * | [in] | init | A pointer to the initialization structure. |
sl_hal_eusart_init_uart_lf#
void sl_hal_eusart_init_uart_lf (EUSART_TypeDef * eusart, const sl_hal_eusart_uart_init_t * init)
Initialize EUSART when used in UART mode with the low frequency clock.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
const sl_hal_eusart_uart_init_t * | [in] | init | A pointer to the initialization structure. |
Note
(1) When EUSART oversampling is set to SL_HAL_EUSART_OVS_0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate. Number of stop bits must be 1 or 2. Data bits must be less than 9 bits. Majority Vote must be disabled.
sl_hal_eusart_init_irda#
void sl_hal_eusart_init_irda (EUSART_TypeDef * eusart, const sl_hal_eusart_irda_init_t * init)
Initialize EUSART when used in IrDA mode with the high or low frequency clock.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
const sl_hal_eusart_irda_init_t * | [in] | init | A pointer to the initialization structure. |
sl_hal_eusart_init_spi#
void sl_hal_eusart_init_spi (EUSART_TypeDef * eusart, const sl_hal_eusart_spi_init_t * init)
Initialize EUSART when used in SPI mode.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
const sl_hal_eusart_spi_init_t * | [in] | init | A pointer to the initialization structure. |
sl_hal_eusart_reset#
void sl_hal_eusart_reset (EUSART_TypeDef * eusart)
Configure EUSART to its reset state.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_rx#
uint16_t sl_hal_eusart_rx (EUSART_TypeDef * eusart)
Receive one 8 bits frame, (or part of 9 bit frame).
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
Note
This function will stall if buffer is empty until data is received.
Returns
Data received.
sl_hal_eusart_rx_extended#
uint16_t sl_hal_eusart_rx_extended (EUSART_TypeDef * eusart)
Receive one 8-16 bit frame with extended information.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
Note
This function is normally used to receive one frame and additional RX status information.
This function will stall if buffer is empty until data is received.
Returns
Data received and receive status.
sl_hal_eusart_tx#
void sl_hal_eusart_tx (EUSART_TypeDef * eusart, uint16_t data)
Transmit one 8 bits frame.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint16_t | [in] | data | Data to transmit. |
Note
This function will stall if the 4 frame FIFO is full, until the buffer becomes available.
sl_hal_eusart_tx_extended#
void sl_hal_eusart_tx_extended (EUSART_TypeDef * eusart, uint16_t data)
Transmit one 8-9 bit frame with extended control.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint16_t | [in] | data | Data to transmit. |
Note
Possible parity/stop bits in asynchronous mode are not considered part of a specified frame bit length.
This function will stall if buffer is full until the buffer becomes available.
sl_hal_eusart_spi_tx_rx#
uint16_t sl_hal_eusart_spi_tx_rx (EUSART_TypeDef * eusart, uint16_t data)
Transmit one 8-16 bit frame and return received data.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint16_t | [in] | data | Data to transmit. |
Returns
Data received and receive status.
Note
SPI master mode only.
This function will stall if the TX buffer is full until the buffer becomes available.
sl_hal_eusart_spi_calculate_clock_div#
uint32_t sl_hal_eusart_spi_calculate_clock_div (uint32_t ref_freq, uint32_t baudrate)
Calculate SPI clock divider using given reference frequency and baudrate.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | ref_freq | Peripheral clock frequency. |
uint32_t | [in] | baudrate | Transmission speed of the SPI interface. |
Returns
Eusart clock divider for desired baud rate.
sl_hal_eusart_uart_calculate_clock_div#
uint32_t sl_hal_eusart_uart_calculate_clock_div (uint32_t ref_freq, uint32_t baudrate, sl_hal_eusart_ovs_t ovs)
Calculate UART clock divider using given reference frequency, oversampling and baudrate.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | ref_freq | Peripheral clock frequency. |
uint32_t | [in] | baudrate | Transmission speed of the UART interface. |
sl_hal_eusart_ovs_t | [in] | ovs | Oversampling rate. |
Returns
Eusart clock divider for desired baud rate.
sl_hal_eusart_uart_calculate_baudrate#
uint32_t sl_hal_eusart_uart_calculate_baudrate (uint32_t div, sl_hal_eusart_ovs_t ovs, uint32_t freq)
Get the calculated baudrate from the current EUSART configuration and clock.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | div | CLKDIV register value of the EUSART. |
sl_hal_eusart_ovs_t | [in] | ovs | Oversample value of the EUSART. |
uint32_t | [in] | freq | The clock branch frequency to calculate the baudrate. |
Returns
The baudrate
sl_hal_eusart_spi_calculate_baudrate#
uint32_t sl_hal_eusart_spi_calculate_baudrate (uint32_t div, uint32_t freq)
Get the calculated baudrate from the current EUSART configuration and clock.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | div | clkdiv register value of the EUSART. |
uint32_t | [in] | freq | The clock branch frequency to calculate the baudrate. |
Returns
The baudrate.
sl_hal_eusart_wait_sync#
void sl_hal_eusart_wait_sync (EUSART_TypeDef * eusart, uint32_t mask)
Wait for ongoing sync of register(s) to the low-frequency domain to complete.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | mask | Bitmask for SYNCBUSY register - indicates which register(s) to wait for synchronization to complete |
sl_hal_eusart_enable#
void sl_hal_eusart_enable (EUSART_TypeDef * eusart)
Enable EUSART.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_disable#
void sl_hal_eusart_disable (EUSART_TypeDef * eusart)
Disable EUSART.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_wait_ready#
void sl_hal_eusart_wait_ready (EUSART_TypeDef * eusart)
Wait for disabling to finish.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_enable_rx#
void sl_hal_eusart_enable_rx (EUSART_TypeDef * eusart)
Enable EUSART receiver.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_disable_rx#
void sl_hal_eusart_disable_rx (EUSART_TypeDef * eusart)
Disable EUSART receiver.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_enable_tx#
void sl_hal_eusart_enable_tx (EUSART_TypeDef * eusart)
Enable EUSART transmitter.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_disable_tx#
void sl_hal_eusart_disable_tx (EUSART_TypeDef * eusart)
Disable EUSART transmitter.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_enable_block_rx#
void sl_hal_eusart_enable_block_rx (EUSART_TypeDef * eusart)
Enable reception operation until the configured start frame is received.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_disable_block_rx#
void sl_hal_eusart_disable_block_rx (EUSART_TypeDef * eusart)
Disable reception operation until the configured start frame is received.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_enable_tx_tristate#
void sl_hal_eusart_enable_tx_tristate (EUSART_TypeDef * eusart)
Enable the tristating of the transmitter output.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_disable_tx_tristate#
void sl_hal_eusart_disable_tx_tristate (EUSART_TypeDef * eusart)
Disable the tristating of the transmitter output.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_clear_rx#
void sl_hal_eusart_clear_rx (EUSART_TypeDef * eusart)
Clear RX FIFO.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_clear_tx#
void sl_hal_eusart_clear_tx (EUSART_TypeDef * eusart)
Clear TX FIFO.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
sl_hal_eusart_get_status#
uint32_t sl_hal_eusart_get_status (EUSART_TypeDef * eusart)
Get EUSART STATUS register.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
Returns
STATUS register value.
sl_hal_eusart_uart_set_clock_div#
void sl_hal_eusart_uart_set_clock_div (EUSART_TypeDef * eusart, uint32_t clock_divider)
Set UART mode clock divider.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | clock_divider | Clock divider value. |
sl_hal_eusart_uart_get_clock_div#
uint32_t sl_hal_eusart_uart_get_clock_div (EUSART_TypeDef * eusart)
Get UART mode clock divider.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | ointer to the EUSART peripheral register block. |
Returns
Clock divider value.
sl_hal_eusart_uart_get_oversampling#
sl_hal_eusart_ovs_t sl_hal_eusart_uart_get_oversampling (EUSART_TypeDef * eusart)
Get UART mode oversampling value.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
Returns
Oversampling value.
sl_hal_eusart_clear_interrupts#
void sl_hal_eusart_clear_interrupts (EUSART_TypeDef * eusart, uint32_t flags)
Clear one or more pending EUSART interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | flags | Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn). |
sl_hal_eusart_disable_interrupts#
void sl_hal_eusart_disable_interrupts (EUSART_TypeDef * eusart, uint32_t flags)
Disable one or more EUSART interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | flags | Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn). |
sl_hal_eusart_enable_interrupts#
void sl_hal_eusart_enable_interrupts (EUSART_TypeDef * eusart, uint32_t flags)
Enable one or more EUSART interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | flags | Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn). |
sl_hal_eusart_get_pending_interrupts#
uint32_t sl_hal_eusart_get_pending_interrupts (EUSART_TypeDef * eusart)
Get pending EUSART interrupt flags.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
Returns
Pending EUSART interrupt sources.
sl_hal_eusart_get_enabled_pending_interrupts#
uint32_t sl_hal_eusart_get_enabled_pending_interrupts (EUSART_TypeDef * eusart)
Get enabled and pending EUSART interrupt flags.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | ointer to the EUSART peripheral register block. |
Note
Useful for handling more interrupt sources in the same interrupt handler.
Returns
Pending and enabled EUSART interrupt sources.
sl_hal_eusart_set_interrupts#
void sl_hal_eusart_set_interrupts (EUSART_TypeDef * eusart, uint32_t flags)
Set one or more pending EUSART interrupts from SW.
Type | Direction | Argument Name | Description |
---|---|---|---|
EUSART_TypeDef * | [in] | eusart | Pointer to the EUSART peripheral register block. |
uint32_t | [in] | flags | Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn). |