EUSART - Enhanced USART#

Enhanced Universal Synchronous/Asynchronous Receiver/Transmitter.

Introduction#

This module contains functions to control the Enhanced Universal Synchronous / Asynchronous Receiver / Transmitter controller(s) (EUSART) peripheral of Silicon Labs' 32-bit MCUs and SoCs. EUSART can be used as a UART and can, therefore, be connected to an external transceiver to communicate with another host using the serial link.

It supports full duplex asynchronous UART communication as well as RS-485, SPI, MicroWire, and 3-wire. It can also interface with ISO7816 Smart-Cards, and IrDA devices.

EUSART has a wide selection of operating modes, frame formats, and baud rates. All features are supported through the API of this module.

This module does not support DMA configuration. UARTDRV and SPIDRV drivers provide full support for DMA and more.

Example#

EUSART Asynchronous UART TX example:

{
  #define GPIO_TX    PB0

  sl_hal_eusart_uart_init_t init = SL_HAL_EUSART_UART_INIT_DEFAULT_HF;

  // Configure the clocks.
  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_EUSART0);
  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);

  // Calculate and configure the eusart's clock divider.
  uint32_t baudrate = 38400;  // Desired baudrate.
  sl_clock_branch_t clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_EUSART0);
  uint32_t freq;
  sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq);
  init.clock_div = sl_hal_eusart_uart_calculate_clock_div(freq, baudrate, init.oversampling);

  // Configure the EUSART port.
  sl_gpio_set_pin_mode(GPIO_TX, SL_GPIO_MODE_PUSH_PULL, 0);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].TXROUTE = (GPIO_TX->port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
                                                 | (GPIO_TX->pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART0)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN;

  // Initialize the EUSART.
  sl_hal_eusart_init_uart_hf(EUSART0, &init);
  sl_hal_eusart_enable(EUSART0);
  sl_hal_eusart_enable_tx(EUSART0);

  uint16_t data = 0xFF;
  sl_hal_eusart_tx(EUSART0, data);
}

EUSART Synchronous SPI Initialization example:

{
  #define GPIO_MOSI    PC0
  #define GPIO_MISO    PC1
  #define GPIO_SCLK    PC2

  sl_hal_eusart_spi_init_t init = SL_HAL_EUSART_SPI_MASTER_INIT_DEFAULT_HF;
  // Clock idle low, sample on falling edge.
  init.clock_mode = SL_HAL_EUSART_CLOCK_MODE_1;

  // Configure the clocks.
  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_EUSART1);
  sl_clock_manager_enable_bus_clock(SL_BUS_CLOCK_GPIO);

  // Calculate and configure the eusart's clock divider.
  uint32_t baudrate  = 1000000;  // Desired baudrate.
  sl_clock_branch_t clock_branch = sl_device_peripheral_get_clock_branch(SL_PERIPHERAL_EUSART1);
  uint32_t freq;
  sl_clock_manager_get_clock_branch_frequency(clock_branch, &freq);
  init.clock_div = sl_hal_eusart_spi_calculate_clock_div(freq, baudrate);

  // Configure the SPI ports.
  sl_gpio_set_pin_mode(GPIO_MOSI, SL_GPIO_MODE_PUSH_PULL, 0);
  sl_gpio_set_pin_mode(GPIO_MISO, SL_GPIO_MODE_INPUT, 0);
  sl_gpio_set_pin_mode(GPIO_SCLK, SL_GPIO_MODE_PUSH_PULL, 0);

  // Connect EUSART to ports.
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].TXROUTE = (GPIO_MOSI->port << _GPIO_EUSART_TXROUTE_PORT_SHIFT)
                                                   | (GPIO_MOSI->pin << _GPIO_EUSART_TXROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].RXROUTE = (GPIO_MISO->port << _GPIO_EUSART_RXROUTE_PORT_SHIFT)
                                                   | (GPIO_MISO->pin << _GPIO_EUSART_RXROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].SCLKROUTE = (GPIO_SCLK->port << _GPIO_EUSART_SCLKROUTE_PORT_SHIFT)
                                                   | (GPIO_SCLK->pin << _GPIO_EUSART_SCLKROUTE_PIN_SHIFT);
  GPIO->EUSARTROUTE[EUSART_NUM(EUSART1)].ROUTEEN = GPIO_EUSART_ROUTEEN_TXPEN | GPIO_EUSART_ROUTEEN_RXPEN | GPIO_EUSART_ROUTEEN_SCLKPEN;

  // Initialize the EUSART.
  sl_hal_eusart_init_spi(EUSART1, &init);
  sl_hal_eusart_enable(EUSART1);
  sl_hal_eusart_enable_rx(EUSART1);
  sl_hal_eusart_enable_tx(EUSART1);
}

Modules#

sl_hal_eusart_uart_advanced_init_t

sl_hal_eusart_uart_init_t

sl_hal_eusart_irda_init_t

sl_hal_eusart_dali_init_t

sl_hal_eusart_spi_advanced_init_t

sl_hal_eusart_spi_init_t

Enumerations#

enum

sl_hal_eusart_data_bits_t {

SL_HAL_EUSART_DATA_BITS_7 = _EUSART_FRAMECFG_DATABITS_SEVEN

SL_HAL_EUSART_DATA_BITS_8 = _EUSART_FRAMECFG_DATABITS_EIGHT

SL_HAL_EUSART_DATA_BITS_9 = _EUSART_FRAMECFG_DATABITS_NINE

SL_HAL_EUSART_DATA_BITS_10 = _EUSART_FRAMECFG_DATABITS_TEN

SL_HAL_EUSART_DATA_BITS_11 = _EUSART_FRAMECFG_DATABITS_ELEVEN

SL_HAL_EUSART_DATA_BITS_12 = _EUSART_FRAMECFG_DATABITS_TWELVE

SL_HAL_EUSART_DATA_BITS_13 = _EUSART_FRAMECFG_DATABITS_THIRTEEN

SL_HAL_EUSART_DATA_BITS_14 = _EUSART_FRAMECFG_DATABITS_FOURTEEN

SL_HAL_EUSART_DATA_BITS_15 = _EUSART_FRAMECFG_DATABITS_FIFTEEN

SL_HAL_EUSART_DATA_BITS_16 = _EUSART_FRAMECFG_DATABITS_SIXTEEN

}

Data bit selection.

enum

sl_hal_eusart_parity_t {

SL_HAL_EUSART_NO_PARITY = _EUSART_FRAMECFG_PARITY_NONE

SL_HAL_EUSART_EVEN_PARITY = _EUSART_FRAMECFG_PARITY_EVEN

SL_HAL_EUSART_ODD_PARITY = _EUSART_FRAMECFG_PARITY_ODD

}

Parity selection.

enum

sl_hal_eusart_stop_bits_t {

SL_HAL_EUSART_STOP_BITS_0P5 = _EUSART_FRAMECFG_STOPBITS_HALF

SL_HAL_EUSART_STOP_BITS_1P5 = _EUSART_FRAMECFG_STOPBITS_ONEANDAHALF

SL_HAL_EUSART_STOP_BITS_1 = _EUSART_FRAMECFG_STOPBITS_ONE

SL_HAL_EUSART_STOP_BITS_2 = _EUSART_FRAMECFG_STOPBITS_TWO

}

Stop bits selection.

enum

sl_hal_eusart_ovs_t {

SL_HAL_EUSART_OVS_16 = _EUSART_CFG0_OVS_X16

SL_HAL_EUSART_OVS_8 = _EUSART_CFG0_OVS_X8

SL_HAL_EUSART_OVS_6 = _EUSART_CFG0_OVS_X6

SL_HAL_EUSART_OVS_4 = _EUSART_CFG0_OVS_X4

SL_HAL_EUSART_OVS_0 = _EUSART_CFG0_OVS_DISABLE

}

Oversampling selection, used for asynchronous operation.

enum

sl_hal_eusart_loopback_t {

SL_HAL_EUSART_LOOPBACK_ENABLE = _EUSART_CFG0_LOOPBK_ENABLE

SL_HAL_EUSART_LOOPBACK_DISABLE = _EUSART_CFG0_LOOPBK_DISABLE

}

Loopback enable.

enum

sl_hal_eusart_majority_vote_t {

SL_HAL_EUSART_MAJORITY_VOTE_ENABLE = 0

SL_HAL_EUSART_MAJORITY_VOTE_DISABLE = 1

}

Majority vote enable.

enum

sl_hal_eusart_hw_flow_control_t {

SL_HAL_EUSART_HW_FLOW_CONTROL_NONE = 0

SL_HAL_EUSART_HW_FLOW_CONTROL_CTS

SL_HAL_EUSART_HW_FLOW_CONTROL_RTS

SL_HAL_EUSART_HW_FLOW_CONTROL_CTS_RTS

}

Hardware flow control configuration.

enum

sl_hal_eusart_invert_io_t {

SL_HAL_EUSART_INVERT_IO_DISABLE = (EUSART_CFG0_RXINV_DISABLE | EUSART_CFG0_TXINV_DISABLE) >> _EUSART_CFG0_RXINV_SHIFT

SL_HAL_EUSART_INVERT_IO_RX_ENABLE = EUSART_CFG0_RXINV_ENABLE >> _EUSART_CFG0_RXINV_SHIFT

SL_HAL_EUSART_INVERT_IO_TX_ENABLE = EUSART_CFG0_TXINV_ENABLE >> _EUSART_CFG0_RXINV_SHIFT

SL_HAL_EUSART_INVERT_IO_RXTX_ENABLE = (EUSART_CFG0_RXINV_ENABLE | EUSART_CFG0_TXINV_ENABLE) >> _EUSART_CFG0_RXINV_SHIFT

}

IO polarity selection.

enum

sl_hal_eusart_auto_tx_delay_t {

SL_HAL_EUSART_AUTO_TX_DELAY_NONE = _EUSART_TIMINGCFG_TXDELAY_NONE

SL_HAL_EUSART_AUTO_TX_DELAY_SINGLE = _EUSART_TIMINGCFG_TXDELAY_SINGLE

SL_HAL_EUSART_AUTO_TX_DELAY_DOUBLE = _EUSART_TIMINGCFG_TXDELAY_DOUBLE

SL_HAL_EUSART_AUTO_TX_DELAY_TRIPPLE = _EUSART_TIMINGCFG_TXDELAY_TRIPPLE

}

Auto TX delay transmission.

enum

sl_hal_eusart_fifo_interrupt_watermark_t {

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ONE = _EUSART_CFG1_RXFIW_ONEFRAME

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWO = _EUSART_CFG1_RXFIW_TWOFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THREE = _EUSART_CFG1_RXFIW_THREEFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOUR = _EUSART_CFG1_RXFIW_FOURFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIVE = _EUSART_CFG1_RXFIW_FIVEFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIX = _EUSART_CFG1_RXFIW_SIXFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SEVEN = _EUSART_CFG1_RXFIW_SEVENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_EIGHT = _EUSART_CFG1_RXFIW_EIGHTFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_NINE = _EUSART_CFG1_RXFIW_NINEFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TEN = _EUSART_CFG1_RXFIW_TENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ELEVEN = _EUSART_CFG1_RXFIW_ELEVENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWELVE = _EUSART_CFG1_RXFIW_TWELVEFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THIRTEEN = _EUSART_CFG1_RXFIW_THIRTEENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOURTEEN = _EUSART_CFG1_RXFIW_FOURTEENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIFTEEN = _EUSART_CFG1_RXFIW_FIFTEENFRAMES

SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIXTEEN = _EUSART_CFG1_RXFIW_SIXTEENFRAMES

}

FIFO Interrupt and Status Watermark.

enum

sl_hal_eusart_irda_frequency_mode_t {

SL_HAL_EUSART_IRDA_MODE_HF

SL_HAL_EUSART_IRDA_MODE_LF

}

IrDA frequency mode (high/low frequency).

enum

sl_hal_eusart_irda_pulse_width_t {

SL_HAL_EUSART_PULSE_WIDTH_ONE = _EUSART_IRHFCFG_IRHFPW_ONE

SL_HAL_EUSART_PULSE_WIDTH_TWO = _EUSART_IRHFCFG_IRHFPW_TWO

SL_HAL_EUSART_PULSE_WIDTH_THREE = _EUSART_IRHFCFG_IRHFPW_THREE

SL_HAL_EUSART_PULSE_WIDTH_FOUR = _EUSART_IRHFCFG_IRHFPW_FOUR

}

Pulse width selection for IrDA mode.

enum

sl_hal_eusart_cs_time_t {

SL_HAL_EUSART_CS_TIME_ZERO = _EUSART_TIMINGCFG_CSSETUP_ZERO

SL_HAL_EUSART_CS_TIME_ONE = _EUSART_TIMINGCFG_CSSETUP_ONE

SL_HAL_EUSART_CS_TIME_TWO = _EUSART_TIMINGCFG_CSSETUP_TWO

SL_HAL_EUSART_CS_TIME_THREE = _EUSART_TIMINGCFG_CSSETUP_THREE

SL_HAL_EUSART_CS_TIME_FOUR = _EUSART_TIMINGCFG_CSSETUP_FOUR

SL_HAL_EUSART_CS_TIME_FIVE = _EUSART_TIMINGCFG_CSSETUP_FIVE

SL_HAL_EUSART_CS_TIME_SIX = _EUSART_TIMINGCFG_CSSETUP_SIX

SL_HAL_EUSART_CS_TIME_SEVEN = _EUSART_TIMINGCFG_CSSETUP_SEVEN

}

Chip select assertion/de-assertion time.

enum

sl_hal_eusart_inter_character_space_t {

SL_HAL_EUSART_ICS_TIME_ZERO = _EUSART_TIMINGCFG_ICS_ZERO

SL_HAL_EUSART_ICS_TIME_ONE = _EUSART_TIMINGCFG_ICS_ONE

SL_HAL_EUSART_ICS_TIME_TWO = _EUSART_TIMINGCFG_ICS_TWO

SL_HAL_EUSART_ICS_TIME_THREE = _EUSART_TIMINGCFG_ICS_THREE

SL_HAL_EUSART_ICS_TIME_FOUR = _EUSART_TIMINGCFG_ICS_FOUR

SL_HAL_EUSART_ICS_TIME_FIVE = _EUSART_TIMINGCFG_ICS_FIVE

SL_HAL_EUSART_ICS_TIME_SIX = _EUSART_TIMINGCFG_ICS_SIX

SL_HAL_EUSART_ICS_TIME_SEVEN = _EUSART_TIMINGCFG_ICS_SEVEN

}

Inter-character spacing after each TX frame while TX FIFO is not empty.

enum

sl_hal_eusart_cs_polarity_t {

SL_HAL_EUSART_CS_ACTIVE_LOW = _EUSART_CFG2_CSINV_AL

SL_HAL_EUSART_CS_ACTIVE_HIGH = _EUSART_CFG2_CSINV_AH

}

Chip select polarity.

enum

sl_hal_eusart_clock_mode_t {

SL_HAL_EUSART_CLOCK_MODE_0 = (EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLELEADING) >> _EUSART_CFG2_CLKPOL_SHIFT

SL_HAL_EUSART_CLOCK_MODE_1 = (EUSART_CFG2_CLKPOL_IDLELOW | EUSART_CFG2_CLKPHA_SAMPLETRAILING) >> _EUSART_CFG2_CLKPOL_SHIFT

SL_HAL_EUSART_CLOCK_MODE_2 = (EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLELEADING) >> _EUSART_CFG2_CLKPOL_SHIFT

SL_HAL_EUSART_CLOCK_MODE_3 = (EUSART_CFG2_CLKPOL_IDLEHIGH | EUSART_CFG2_CLKPHA_SAMPLETRAILING) >> _EUSART_CFG2_CLKPOL_SHIFT

}

Clock polarity/phase mode.

enum

sl_hal_eusart_dali_data_bits_t {

SL_HAL_EUSART_DALI_DATA_BITS_8 = _EUSART_DALICFG_DALITXDATABITS_EIGHT

SL_HAL_EUSART_DALI_DATA_BITS_9 = _EUSART_DALICFG_DALITXDATABITS_NINE

SL_HAL_EUSART_DALI_DATA_BITS_10 = _EUSART_DALICFG_DALITXDATABITS_TEN

SL_HAL_EUSART_DALI_DATA_BITS_11 = _EUSART_DALICFG_DALITXDATABITS_ELEVEN

SL_HAL_EUSART_DALI_DATA_BITS_12 = _EUSART_DALICFG_DALITXDATABITS_TWELVE

SL_HAL_EUSART_DALI_DATA_BITS_13 = _EUSART_DALICFG_DALITXDATABITS_THIRTEEN

SL_HAL_EUSART_DALI_DATA_BITS_14 = _EUSART_DALICFG_DALITXDATABITS_FOURTEEN

SL_HAL_EUSART_DALI_DATA_BITS_15 = _EUSART_DALICFG_DALITXDATABITS_FIFTEEN

SL_HAL_EUSART_DALI_DATA_BITS_16 = _EUSART_DALICFG_DALITXDATABITS_SIXTEEN

SL_HAL_EUSART_DALI_DATA_BITS_17 = _EUSART_DALICFG_DALITXDATABITS_SEVENTEEN

SL_HAL_EUSART_DALI_DATA_BITS_18 = _EUSART_DALICFG_DALITXDATABITS_EIGHTEEN

SL_HAL_EUSART_DALI_DATA_BITS_19 = _EUSART_DALICFG_DALITXDATABITS_NINETEEN

SL_HAL_EUSART_DALI_DATA_BITS_20 = _EUSART_DALICFG_DALITXDATABITS_TWENTY

SL_HAL_EUSART_DALI_DATA_BITS_21 = _EUSART_DALICFG_DALITXDATABITS_TWENTYONE

SL_HAL_EUSART_DALI_DATA_BITS_22 = _EUSART_DALICFG_DALITXDATABITS_TWENTYTWO

SL_HAL_EUSART_DALI_DATA_BITS_23 = _EUSART_DALICFG_DALITXDATABITS_TWENTYTHREE

SL_HAL_EUSART_DALI_DATA_BITS_24 = _EUSART_DALICFG_DALITXDATABITS_TWENTYFOUR

SL_HAL_EUSART_DALI_DATA_BITS_25 = _EUSART_DALICFG_DALITXDATABITS_TWENTYFIVE

SL_HAL_EUSART_DALI_DATA_BITS_26 = _EUSART_DALICFG_DALITXDATABITS_TWENTYSIX

SL_HAL_EUSART_DALI_DATA_BITS_27 = _EUSART_DALICFG_DALITXDATABITS_TWENTYSEVEN

SL_HAL_EUSART_DALI_DATA_BITS_28 = _EUSART_DALICFG_DALITXDATABITS_TWENTYEIGHT

SL_HAL_EUSART_DALI_DATA_BITS_29 = _EUSART_DALICFG_DALITXDATABITS_TWENTYNINE

SL_HAL_EUSART_DALI_DATA_BITS_30 = _EUSART_DALICFG_DALITXDATABITS_THIRTY

SL_HAL_EUSART_DALI_DATA_BITS_31 = _EUSART_DALICFG_DALITXDATABITS_THIRTYONE

SL_HAL_EUSART_DALI_DATA_BITS_32 = _EUSART_DALICFG_DALITXDATABITS_THIRTYTWO

}

DALI RX/TX databits (8-32).

Functions#

void

sl_hal_eusart_init_uart_hf(EUSART_TypeDef *eusart, const sl_hal_eusart_uart_init_t *init)

Initialize EUSART when used in UART mode with the high frequency clock.

void

sl_hal_eusart_init_uart_lf(EUSART_TypeDef *eusart, const sl_hal_eusart_uart_init_t *init)

Initialize EUSART when used in UART mode with the low frequency clock.

void

sl_hal_eusart_init_irda(EUSART_TypeDef *eusart, const sl_hal_eusart_irda_init_t *init)

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

void

sl_hal_eusart_init_dali(EUSART_TypeDef *eusart, const sl_hal_eusart_dali_init_t *init)

Initialize EUSART when used in DALI mode with the high or low frequency clock.

void

sl_hal_eusart_init_spi(EUSART_TypeDef *eusart, const sl_hal_eusart_spi_init_t *init)

Initialize EUSART when used in SPI mode.

void

sl_hal_eusart_reset(EUSART_TypeDef *eusart)

Configure EUSART to its reset state.

uint16_t

sl_hal_eusart_rx(EUSART_TypeDef *eusart)

Receive one 8 bits frame, (or part of 9 bit frame).

uint16_t

sl_hal_eusart_rx_extended(EUSART_TypeDef *eusart)

Receive one 8-16 bit frame with extended information.

void

sl_hal_eusart_tx(EUSART_TypeDef *eusart, uint16_t data)

Transmit one 8 bits frame.

void

sl_hal_eusart_tx_extended(EUSART_TypeDef *eusart, uint16_t data)

Transmit one 8-9 bit frame with extended control.

uint16_t

sl_hal_eusart_spi_tx_rx(EUSART_TypeDef *eusart, uint16_t data)

Transmit one 8-16 bit frame and return received data.

void

sl_hal_eusart_dali_tx(EUSART_TypeDef *eusart, uint32_t data)

Transmit one DALI frame.

uint32_t

sl_hal_eusart_dali_rx(EUSART_TypeDef *eusart)

Receive one 8-32 bit DALI frame.

uint32_t

sl_hal_eusart_spi_calculate_clock_div(uint32_t ref_freq, uint32_t baudrate)

Calculate SPI clock divider using given reference frequency and baudrate.

uint32_t

sl_hal_eusart_uart_calculate_clock_div(uint32_t ref_freq, uint32_t baudrate, sl_hal_eusart_ovs_t ovs)

Calculate UART clock divider using given reference frequency, oversampling and baudrate.

uint32_t

sl_hal_eusart_uart_calculate_baudrate(uint32_t div, sl_hal_eusart_ovs_t ovs, uint32_t freq)

Get the calculated baudrate from the current EUSART configuration and clock.

uint32_t

sl_hal_eusart_spi_calculate_baudrate(uint32_t div, uint32_t freq)

Get the calculated baudrate from the current EUSART configuration and clock.

void

sl_hal_eusart_wait_sync(EUSART_TypeDef *eusart, uint32_t mask)

Wait for ongoing sync of register(s) to the low-frequency domain to complete.

void

sl_hal_eusart_enable(EUSART_TypeDef *eusart)

Enable EUSART.

void

sl_hal_eusart_disable(EUSART_TypeDef *eusart)

Disable EUSART.

void

sl_hal_eusart_wait_ready(EUSART_TypeDef *eusart)

Wait for disabling to finish.

void

sl_hal_eusart_enable_rx(EUSART_TypeDef *eusart)

Enable EUSART receiver.

void

sl_hal_eusart_disable_rx(EUSART_TypeDef *eusart)

Disable EUSART receiver.

void

sl_hal_eusart_enable_tx(EUSART_TypeDef *eusart)

Enable EUSART transmitter.

void

sl_hal_eusart_disable_tx(EUSART_TypeDef *eusart)

Disable EUSART transmitter.

void

sl_hal_eusart_enable_block_rx(EUSART_TypeDef *eusart)

Enable reception operation until the configured start frame is received.

void

sl_hal_eusart_disable_block_rx(EUSART_TypeDef *eusart)

Disable reception operation until the configured start frame is received.

void

sl_hal_eusart_enable_tx_tristate(EUSART_TypeDef *eusart)

Enable the tristating of the transmitter output.

void

sl_hal_eusart_disable_tx_tristate(EUSART_TypeDef *eusart)

Disable the tristating of the transmitter output.

void

sl_hal_eusart_clear_rx(EUSART_TypeDef *eusart)

Clear RX FIFO.

void

sl_hal_eusart_clear_tx(EUSART_TypeDef *eusart)

Clear TX FIFO.

uint32_t

sl_hal_eusart_get_status(EUSART_TypeDef *eusart)

Get EUSART STATUS register.

void

sl_hal_eusart_uart_set_clock_div(EUSART_TypeDef *eusart, uint32_t clock_divider)

Set UART mode clock divider.

uint32_t

sl_hal_eusart_uart_get_clock_div(EUSART_TypeDef *eusart)

Get UART mode clock divider.

sl_hal_eusart_ovs_t

sl_hal_eusart_uart_get_oversampling(EUSART_TypeDef *eusart)

Get UART mode oversampling value.

void

sl_hal_eusart_clear_interrupts(EUSART_TypeDef *eusart, uint32_t flags)

Clear one or more pending EUSART interrupts.

void

sl_hal_eusart_disable_interrupts(EUSART_TypeDef *eusart, uint32_t flags)

Disable one or more EUSART interrupts.

void

sl_hal_eusart_enable_interrupts(EUSART_TypeDef *eusart, uint32_t flags)

Enable one or more EUSART interrupts.

uint32_t

sl_hal_eusart_get_pending_interrupts(EUSART_TypeDef *eusart)

Get pending EUSART interrupt flags.

uint32_t

sl_hal_eusart_get_enabled_pending_interrupts(EUSART_TypeDef *eusart)

Get enabled and pending EUSART interrupt flags.

void

sl_hal_eusart_set_interrupts(EUSART_TypeDef *eusart, uint32_t flags)

Set one or more pending EUSART interrupts from SW.

Macros#

#define

SL_HAL_EUSART_REF_VALID (ref)

Check if EUSART insance is valid.

#define

SL_HAL_EUSART_UART_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in UART mode with high-frequency clock.

#define

SL_HAL_EUSART_UART_INIT_DEFAULT_LF undefined

Default configuration for EUSART initialization structure in UART mode with low-frequency clock.

#define

SL_HAL_EUSART_UART_ADVANCED_INIT_DEFAULT undefined

Default configuration for EUSART advanced initialization structure in UART mode..

#define

SL_HAL_EUSART_SPI_MASTER_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in SPI master mode with high-frequency clock.

#define

SL_HAL_EUSART_SPI_SLAVE_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in SPI slave mode with high-frequency clock.

#define

SL_HAL_EUSART_SPI_ADVANCED_INIT_DEFAULT undefined

Default advanced configuration for EUSART initialization structure in SPI mode with high-frequency clock.

#define

SL_HAL_EUSART_IRDA_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in IrDA mode with high-frequency clock.

#define

SL_HAL_EUSART_IRDA_INIT_DEFAULT_LF undefined

Default configuration for EUSART initialization structure in IrDA mode with low-frequency clock.

#define

SL_HAL_EUSART_DALI_ADVANCED_INIT_DEFAULT undefined

Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.

#define

SL_HAL_EUSART_DALI_INIT_DEFAULT_HF undefined

Default configuration for EUSART initialization structure in DALI mode with high-frequency clock.

#define

SL_HAL_EUSART_DALI_INIT_DEFAULT_LF undefined

Default configuration for EUSART initialization structure in DALI mode with low-frequency clock.

Enumeration Documentation#

sl_hal_eusart_data_bits_t#

sl_hal_eusart_data_bits_t

Data bit selection.

Enumerator
SL_HAL_EUSART_DATA_BITS_7	7 data bits.
SL_HAL_EUSART_DATA_BITS_8	8 data bits.
SL_HAL_EUSART_DATA_BITS_9	9 data bits.
SL_HAL_EUSART_DATA_BITS_10	10 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_11	11 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_12	12 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_13	13 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_14	14 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_15	15 data bits, SPI mode only.
SL_HAL_EUSART_DATA_BITS_16	16 data bits, SPI mode only.

sl_hal_eusart_parity_t#

sl_hal_eusart_parity_t

Parity selection.

Enumerator
SL_HAL_EUSART_NO_PARITY	No parity.
SL_HAL_EUSART_EVEN_PARITY	Even parity.
SL_HAL_EUSART_ODD_PARITY	Odd parity.

sl_hal_eusart_stop_bits_t#

sl_hal_eusart_stop_bits_t

Stop bits selection.

Enumerator
SL_HAL_EUSART_STOP_BITS_0P5	0.5 stop bits.
SL_HAL_EUSART_STOP_BITS_1P5	1.5 stop bits.
SL_HAL_EUSART_STOP_BITS_1	1 stop bits.
SL_HAL_EUSART_STOP_BITS_2	2 stop bits.

sl_hal_eusart_ovs_t#

sl_hal_eusart_ovs_t

Oversampling selection, used for asynchronous operation.

Enumerator
SL_HAL_EUSART_OVS_16	16x oversampling (normal).
SL_HAL_EUSART_OVS_8	8x oversampling.
SL_HAL_EUSART_OVS_6	6x oversampling.
SL_HAL_EUSART_OVS_4	4x oversampling.
SL_HAL_EUSART_OVS_0	Oversampling disabled.

sl_hal_eusart_loopback_t#

sl_hal_eusart_loopback_t

Loopback enable.

Enumerator
SL_HAL_EUSART_LOOPBACK_ENABLE	Enable loopback.
SL_HAL_EUSART_LOOPBACK_DISABLE	Disable loopback.

sl_hal_eusart_majority_vote_t#

sl_hal_eusart_majority_vote_t

Majority vote enable.

Enumerator
SL_HAL_EUSART_MAJORITY_VOTE_ENABLE	Enable majority vote for 16x, 8x and 6x oversampling modes.
SL_HAL_EUSART_MAJORITY_VOTE_DISABLE	Disable majority vote for 16x, 8x and 6x oversampling modes.

sl_hal_eusart_hw_flow_control_t#

sl_hal_eusart_hw_flow_control_t

Hardware flow control configuration.

Enumerator
SL_HAL_EUSART_HW_FLOW_CONTROL_NONE	No Hardware Flow Control.
SL_HAL_EUSART_HW_FLOW_CONTROL_CTS	CTS Hardware Flow Control.
SL_HAL_EUSART_HW_FLOW_CONTROL_RTS	RTS Hardware Flow Control.
SL_HAL_EUSART_HW_FLOW_CONTROL_CTS_RTS	CTS and RTS Hardware Flow Control.

sl_hal_eusart_invert_io_t#

sl_hal_eusart_invert_io_t

IO polarity selection.

Enumerator
SL_HAL_EUSART_INVERT_IO_DISABLE	Disable inversion on both RX and TX signals.
SL_HAL_EUSART_INVERT_IO_RX_ENABLE	Invert RX signal, before receiver.
SL_HAL_EUSART_INVERT_IO_TX_ENABLE	Invert TX signal, after transmitter.
SL_HAL_EUSART_INVERT_IO_RXTX_ENABLE	Enable trigger on both receive and transmit.

sl_hal_eusart_auto_tx_delay_t#

sl_hal_eusart_auto_tx_delay_t

Auto TX delay transmission.

Enumerator
SL_HAL_EUSART_AUTO_TX_DELAY_NONE	Frames are transmitted immediately.
SL_HAL_EUSART_AUTO_TX_DELAY_SINGLE	Transmission of new frames is delayed by a single bit period.
SL_HAL_EUSART_AUTO_TX_DELAY_DOUBLE	Transmission of new frames is delayed by a two bit periods.
SL_HAL_EUSART_AUTO_TX_DELAY_TRIPPLE	Transmission of new frames is delayed by a three bit periods.

sl_hal_eusart_fifo_interrupt_watermark_t#

sl_hal_eusart_fifo_interrupt_watermark_t

FIFO Interrupt and Status Watermark.

Enumerator
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ONE	Interrupt and status level are set after 1 frame.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWO	Interrupt and status level are set after 2 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THREE	Interrupt and status level are set after 3 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOUR	Interrupt and status level are set after 4 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIVE	Interrupt and status level are set after 5 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIX	Interrupt and status level are set after 6 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SEVEN	Interrupt and status level are set after 7 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_EIGHT	Interrupt and status level are set after 8 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_NINE	Interrupt and status level are set after 9 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TEN	Interrupt and status level are set after 10 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_ELEVEN	Interrupt and status level are set after 11 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_TWELVE	Interrupt and status level are set after 12 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_THIRTEEN	Interrupt and status level are set after 13 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FOURTEEN	Interrupt and status level are set after 14 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_FIFTEEN	Interrupt and status level are set after 15 frames.
SL_HAL_EUSART_FIFO_INTERRUPT_WATERMARK_FRAMES_SIXTEEN	Interrupt and status level are set after 16 frames.

sl_hal_eusart_irda_frequency_mode_t#

sl_hal_eusart_irda_frequency_mode_t

IrDA frequency mode (high/low frequency).

Enumerator
SL_HAL_EUSART_IRDA_MODE_HF	High frequency mode.
SL_HAL_EUSART_IRDA_MODE_LF	Low frequency mode.

sl_hal_eusart_irda_pulse_width_t#

sl_hal_eusart_irda_pulse_width_t

Pulse width selection for IrDA mode.

Enumerator
SL_HAL_EUSART_PULSE_WIDTH_ONE	IrDA pulse width is 1/16 for OVS=X16 and 1/8 for OVS=X8.
SL_HAL_EUSART_PULSE_WIDTH_TWO	IrDA pulse width is 2/16 for OVS=X16 and 2/8 for OVS=X8.
SL_HAL_EUSART_PULSE_WIDTH_THREE	IrDA pulse width is 3/16 for OVS=X16 and 3/8 for OVS=X8.
SL_HAL_EUSART_PULSE_WIDTH_FOUR	IrDA pulse width is 4/16 for OVS=X16 and 4/8 for OVS=X8.

sl_hal_eusart_cs_time_t#

sl_hal_eusart_cs_time_t

Chip select assertion/de-assertion time.

Enumerator
SL_HAL_EUSART_CS_TIME_ZERO	Chip select is asserted/de-asserted half or 1 baud-time before transmission.
SL_HAL_EUSART_CS_TIME_ONE	Chip select is asserted/de-asserted 1 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_TWO	Chip select is asserted/de-asserted 2 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_THREE	Chip select is asserted/de-asserted 3 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_FOUR	Chip select is asserted/de-asserted 4 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_FIVE	Chip select is asserted/de-asserted 5 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_SIX	Chip select is asserted/de-asserted 6 additional baud-time before transmission.
SL_HAL_EUSART_CS_TIME_SEVEN	Chip select is asserted/de-asserted 7 additional baud-time before transmission.

sl_hal_eusart_inter_character_space_t#

sl_hal_eusart_inter_character_space_t

Inter-character spacing after each TX frame while TX FIFO is not empty.

Enumerator
SL_HAL_EUSART_ICS_TIME_ZERO	There is no space between characters..
SL_HAL_EUSART_ICS_TIME_ONE	Create a space on 1 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_TWO	Create a space on 2 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_THREE	Create a space on 3 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_FOUR	Create a space on 4 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_FIVE	Create a space on 5 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_SIX	Create a space on 6 baud-times between frames.
SL_HAL_EUSART_ICS_TIME_SEVEN	Create a space on 7 baud-times between frames.

sl_hal_eusart_cs_polarity_t#

sl_hal_eusart_cs_polarity_t

Chip select polarity.

Enumerator
SL_HAL_EUSART_CS_ACTIVE_LOW	Chip select active low.
SL_HAL_EUSART_CS_ACTIVE_HIGH	Chip select active high.

sl_hal_eusart_clock_mode_t#

sl_hal_eusart_clock_mode_t

Clock polarity/phase mode.

Enumerator
SL_HAL_EUSART_CLOCK_MODE_0	Clock idle low, sample on rising edge.
SL_HAL_EUSART_CLOCK_MODE_1	Clock idle low, sample on falling edge.
SL_HAL_EUSART_CLOCK_MODE_2	Clock idle high, sample on falling edge.
SL_HAL_EUSART_CLOCK_MODE_3	Clock idle high, sample on rising edge.

sl_hal_eusart_dali_data_bits_t#

sl_hal_eusart_dali_data_bits_t

DALI RX/TX databits (8-32).

Enumerator
SL_HAL_EUSART_DALI_DATA_BITS_8	Each frame contains 8 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_9	Each frame contains 9 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_10	Each frame contains 10 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_11	Each frame contains 11 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_12	Each frame contains 12 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_13	Each frame contains 13 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_14	Each frame contains 14 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_15	Each frame contains 15 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_16	Each frame contains 16 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_17	Each frame contains 17 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_18	Each frame contains 18 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_19	Each frame contains 19 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_20	Each frame contains 20 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_21	Each frame contains 21 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_22	Each frame contains 22 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_23	Each frame contains 23 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_24	Each frame contains 24 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_25	Each frame contains 25 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_26	Each frame contains 26 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_27	Each frame contains 27 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_28	Each frame contains 28 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_29	Each frame contains 29 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_30	Each frame contains 30 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_31	Each frame contains 31 data bits.
SL_HAL_EUSART_DALI_DATA_BITS_32	Each frame contains 32 data bits.

Function Documentation#

sl_hal_eusart_init_uart_hf#

void sl_hal_eusart_init_uart_hf (EUSART_TypeDef * eusart, const sl_hal_eusart_uart_init_t * init)

Initialize EUSART when used in UART mode with the high frequency clock.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
const sl_hal_eusart_uart_init_t *	[in]	init	A pointer to the initialization structure.

sl_hal_eusart_init_uart_lf#

void sl_hal_eusart_init_uart_lf (EUSART_TypeDef * eusart, const sl_hal_eusart_uart_init_t * init)

Initialize EUSART when used in UART mode with the low frequency clock.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
const sl_hal_eusart_uart_init_t *	[in]	init	A pointer to the initialization structure.

Note

(1) When EUSART oversampling is set to SL_HAL_EUSART_OVS_0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate. Number of stop bits must be 1 or 2. Data bits must be less than 9 bits. Majority Vote must be disabled.

sl_hal_eusart_init_irda#

void sl_hal_eusart_init_irda (EUSART_TypeDef * eusart, const sl_hal_eusart_irda_init_t * init)

Initialize EUSART when used in IrDA mode with the high or low frequency clock.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
const sl_hal_eusart_irda_init_t *	[in]	init	A pointer to the initialization structure.

sl_hal_eusart_init_dali#

void sl_hal_eusart_init_dali (EUSART_TypeDef * eusart, const sl_hal_eusart_dali_init_t * init)

Initialize EUSART when used in DALI mode with the high or low frequency clock.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
const sl_hal_eusart_dali_init_t *	[in]	init	A pointer to the initialization structure.

Note

When EUSART oversampling is set to SL_HAL_EUSART_OVS_0 (Disable), the peripheral clock frequency must be at least three times higher than the chosen baud rate. In LF, max input clock is 32768 (LFXO or LFRCO), thus 32768 / 3 ~ 9600 baudrate.

sl_hal_eusart_init_spi#

void sl_hal_eusart_init_spi (EUSART_TypeDef * eusart, const sl_hal_eusart_spi_init_t * init)

Initialize EUSART when used in SPI mode.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
const sl_hal_eusart_spi_init_t *	[in]	init	A pointer to the initialization structure.

sl_hal_eusart_reset#

void sl_hal_eusart_reset (EUSART_TypeDef * eusart)

Configure EUSART to its reset state.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_rx#

uint16_t sl_hal_eusart_rx (EUSART_TypeDef * eusart)

Receive one 8 bits frame, (or part of 9 bit frame).

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Note

This function will stall if buffer is empty until data is received.

Returns

Data received.

sl_hal_eusart_rx_extended#

uint16_t sl_hal_eusart_rx_extended (EUSART_TypeDef * eusart)

Receive one 8-16 bit frame with extended information.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Note

This function is normally used to receive one frame and additional RX status information.
This function will stall if buffer is empty until data is received.

Returns

Data received and receive status.

sl_hal_eusart_tx#

void sl_hal_eusart_tx (EUSART_TypeDef * eusart, uint16_t data)

Transmit one 8 bits frame.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint16_t	[in]	data	Data to transmit.

Note

This function will stall if the 4 frame FIFO is full, until the buffer becomes available.

sl_hal_eusart_tx_extended#

void sl_hal_eusart_tx_extended (EUSART_TypeDef * eusart, uint16_t data)

Transmit one 8-9 bit frame with extended control.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint16_t	[in]	data	Data to transmit.

Note

Possible parity/stop bits in asynchronous mode are not considered part of a specified frame bit length.
This function will stall if buffer is full until the buffer becomes available.

sl_hal_eusart_spi_tx_rx#

uint16_t sl_hal_eusart_spi_tx_rx (EUSART_TypeDef * eusart, uint16_t data)

Transmit one 8-16 bit frame and return received data.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint16_t	[in]	data	Data to transmit.

Returns

Data received and receive status.

Note

SPI master mode only.
This function will stall if the TX buffer is full until the buffer becomes available.

sl_hal_eusart_dali_tx#

void sl_hal_eusart_dali_tx (EUSART_TypeDef * eusart, uint32_t data)

Transmit one DALI frame.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	data	Data to transmit.

Note

Depending on the TXdatabits configuration, N (least significant) bits from data are transmitted.
This function will stall if the 16 frame FIFO is full, until the buffer becomes available.

sl_hal_eusart_dali_rx#

uint32_t sl_hal_eusart_dali_rx (EUSART_TypeDef * eusart)

Receive one 8-32 bit DALI frame.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Note

This function is normally used to receive one DALI frame.
This function will stall if the 16 frame FIFO is empty until new data is received.

Returns

Data received. Depending on the RXdatabits configuration, N (least significant) bits are returned.

sl_hal_eusart_spi_calculate_clock_div#

uint32_t sl_hal_eusart_spi_calculate_clock_div (uint32_t ref_freq, uint32_t baudrate)

Calculate SPI clock divider using given reference frequency and baudrate.

Parameters

Type	Direction	Argument Name	Description
uint32_t	[in]	ref_freq	Peripheral clock frequency.
uint32_t	[in]	baudrate	Transmission speed of the SPI interface.

Returns

Eusart clock divider for desired baud rate.

sl_hal_eusart_uart_calculate_clock_div#

uint32_t sl_hal_eusart_uart_calculate_clock_div (uint32_t ref_freq, uint32_t baudrate, sl_hal_eusart_ovs_t ovs)

Calculate UART clock divider using given reference frequency, oversampling and baudrate.

Parameters

Type	Direction	Argument Name	Description
uint32_t	[in]	ref_freq	Peripheral clock frequency.
uint32_t	[in]	baudrate	Transmission speed of the UART interface.
sl_hal_eusart_ovs_t	[in]	ovs	Oversampling rate.

Returns

Eusart clock divider for desired baud rate.

sl_hal_eusart_uart_calculate_baudrate#

uint32_t sl_hal_eusart_uart_calculate_baudrate (uint32_t div, sl_hal_eusart_ovs_t ovs, uint32_t freq)

Get the calculated baudrate from the current EUSART configuration and clock.

Parameters

Type	Direction	Argument Name	Description
uint32_t	[in]	div	CLKDIV register value of the EUSART.
sl_hal_eusart_ovs_t	[in]	ovs	Oversample value of the EUSART.
uint32_t	[in]	freq	The clock branch frequency to calculate the baudrate.

Returns

The baudrate

sl_hal_eusart_spi_calculate_baudrate#

uint32_t sl_hal_eusart_spi_calculate_baudrate (uint32_t div, uint32_t freq)

Get the calculated baudrate from the current EUSART configuration and clock.

Parameters

Type	Direction	Argument Name	Description
uint32_t	[in]	div	clkdiv register value of the EUSART.
uint32_t	[in]	freq	The clock branch frequency to calculate the baudrate.

Returns

The baudrate.

sl_hal_eusart_wait_sync#

void sl_hal_eusart_wait_sync (EUSART_TypeDef * eusart, uint32_t mask)

Wait for ongoing sync of register(s) to the low-frequency domain to complete.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	mask	Bitmask for SYNCBUSY register - indicates which register(s) to wait for synchronization to complete

sl_hal_eusart_enable#

void sl_hal_eusart_enable (EUSART_TypeDef * eusart)

Enable EUSART.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_disable#

void sl_hal_eusart_disable (EUSART_TypeDef * eusart)

Disable EUSART.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_wait_ready#

void sl_hal_eusart_wait_ready (EUSART_TypeDef * eusart)

Wait for disabling to finish.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_enable_rx#

void sl_hal_eusart_enable_rx (EUSART_TypeDef * eusart)

Enable EUSART receiver.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_disable_rx#

void sl_hal_eusart_disable_rx (EUSART_TypeDef * eusart)

Disable EUSART receiver.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_enable_tx#

void sl_hal_eusart_enable_tx (EUSART_TypeDef * eusart)

Enable EUSART transmitter.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_disable_tx#

void sl_hal_eusart_disable_tx (EUSART_TypeDef * eusart)

Disable EUSART transmitter.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_enable_block_rx#

void sl_hal_eusart_enable_block_rx (EUSART_TypeDef * eusart)

Enable reception operation until the configured start frame is received.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_disable_block_rx#

void sl_hal_eusart_disable_block_rx (EUSART_TypeDef * eusart)

Disable reception operation until the configured start frame is received.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_enable_tx_tristate#

void sl_hal_eusart_enable_tx_tristate (EUSART_TypeDef * eusart)

Enable the tristating of the transmitter output.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_disable_tx_tristate#

void sl_hal_eusart_disable_tx_tristate (EUSART_TypeDef * eusart)

Disable the tristating of the transmitter output.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_clear_rx#

void sl_hal_eusart_clear_rx (EUSART_TypeDef * eusart)

Clear RX FIFO.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_clear_tx#

void sl_hal_eusart_clear_tx (EUSART_TypeDef * eusart)

Clear TX FIFO.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

sl_hal_eusart_get_status#

uint32_t sl_hal_eusart_get_status (EUSART_TypeDef * eusart)

Get EUSART STATUS register.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Returns

STATUS register value.

sl_hal_eusart_uart_set_clock_div#

void sl_hal_eusart_uart_set_clock_div (EUSART_TypeDef * eusart, uint32_t clock_divider)

Set UART mode clock divider.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	clock_divider	Clock divider value.

sl_hal_eusart_uart_get_clock_div#

uint32_t sl_hal_eusart_uart_get_clock_div (EUSART_TypeDef * eusart)

Get UART mode clock divider.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	ointer to the EUSART peripheral register block.

Returns

Clock divider value.

sl_hal_eusart_uart_get_oversampling#

sl_hal_eusart_ovs_t sl_hal_eusart_uart_get_oversampling (EUSART_TypeDef * eusart)

Get UART mode oversampling value.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Returns

Oversampling value.

sl_hal_eusart_clear_interrupts#

void sl_hal_eusart_clear_interrupts (EUSART_TypeDef * eusart, uint32_t flags)

Clear one or more pending EUSART interrupts.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

sl_hal_eusart_disable_interrupts#

void sl_hal_eusart_disable_interrupts (EUSART_TypeDef * eusart, uint32_t flags)

Disable one or more EUSART interrupts.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

sl_hal_eusart_enable_interrupts#

void sl_hal_eusart_enable_interrupts (EUSART_TypeDef * eusart, uint32_t flags)

Enable one or more EUSART interrupts.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	flags	Pending EUSART interrupt source to clear. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).

sl_hal_eusart_get_pending_interrupts#

uint32_t sl_hal_eusart_get_pending_interrupts (EUSART_TypeDef * eusart)

Get pending EUSART interrupt flags.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.

Returns

Pending EUSART interrupt sources.

sl_hal_eusart_get_enabled_pending_interrupts#

uint32_t sl_hal_eusart_get_enabled_pending_interrupts (EUSART_TypeDef * eusart)

Get enabled and pending EUSART interrupt flags.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	ointer to the EUSART peripheral register block.

Note

Useful for handling more interrupt sources in the same interrupt handler.

Returns

Pending and enabled EUSART interrupt sources.

sl_hal_eusart_set_interrupts#

void sl_hal_eusart_set_interrupts (EUSART_TypeDef * eusart, uint32_t flags)

Set one or more pending EUSART interrupts from SW.

Parameters

Type	Direction	Argument Name	Description
EUSART_TypeDef *	[in]	eusart	Pointer to the EUSART peripheral register block.
uint32_t	[in]	flags	Interrupt source(s) to set to pending. Use a bitwise logic OR combination of valid interrupt flags for EUSART module (EUSART_IF_nnn).