SMU - Security Management Unit#
Security Management Unit (SMU) Peripheral API.
SMU forms the control and status/reporting component of bus-level security in EFM32/EFR32 devices.
Peripheral-level protection is provided via the Peripheral Protection Unit (PPU). PPU provides hardware access barrier to any peripheral that is configured to be protected. When an attempt is made to access a peripheral without the required privilege/security level, PPU detects the fault and intercepts the access. No write or read of the peripheral register space occurs, and an all-zero value is returned if the access is a read.
Modules#
Enumerations#
SMU peripheral identifiers.
Functions#
Enable or disable PPU of SMU.
Initialize PPU of SMU.
Change access settings for a peripheral.
Get the ID of the peripheral that caused an access fault.
Clear one or more pending SMU interrupts.
Disable one or more SMU interrupts.
Enable one or more SMU interrupts.
Get pending SMU interrupts.
Get enabled and pending SMU interrupt flags.
Set one or more pending SMU interrupts from SW.
SMU secure IRQ Handler.
Macros#
Default SMU initialization structure settings.
Enumeration Documentation#
sl_hal_smu_peripheral_id_t#
sl_hal_smu_peripheral_id_t
SMU peripheral identifiers.
Enumerator | |
---|---|
SL_HAL_SMU_EMU | SMU peripheral identifier for EMU |
SL_HAL_SMU_CMU | SMU peripheral identifier for CMU |
SL_HAL_SMU_HFXO | SMU peripheral identifier for HFXO0 |
SL_HAL_SMU_HFRCO0 | SMU peripheral identifier for HFRCO0 |
SL_HAL_SMU_FSRCO | SMU peripheral identifier for FSRCO |
SL_HAL_SMU_DPLL0 | SMU peripheral identifier for DPLL0 |
SL_HAL_SMU_LFXO | SMU peripheral identifier for LFXO |
SL_HAL_SMU_LFRCO | SMU peripheral identifier for LFRCO |
SL_HAL_SMU_ULFRCO | SMU peripheral identifier for ULFRCO |
SL_HAL_SMU_MSC | SMU peripheral identifier for MSC |
SL_HAL_SMU_ICACHE0 | SMU peripheral identifier for ICACHE0 |
SL_HAL_SMU_PRS | SMU peripheral identifier for PRS |
SL_HAL_SMU_GPIO | SMU peripheral identifier for GPIO |
SL_HAL_SMU_LDMA | SMU peripheral identifier for LDMA |
SL_HAL_SMU_LDMAXBAR | SMU peripheral identifier for LDMAXBAR |
SL_HAL_SMU_TIMER0 | SMU peripheral identifier for TIMER0 |
SL_HAL_SMU_TIMER1 | SMU peripheral identifier for TIMER1 |
SL_HAL_SMU_TIMER2 | SMU peripheral identifier for TIMER2 |
SL_HAL_SMU_TIMER3 | SMU peripheral identifier for TIMER3 |
SL_HAL_SMU_TIMER4 | SMU peripheral identifier for TIMER4 |
SL_HAL_SMU_TIMER5 | SMU peripheral identifier for TIMER5 |
SL_HAL_SMU_TIMER6 | SMU peripheral identifier for TIMER6 |
SL_HAL_SMU_TIMER7 | SMU peripheral identifier for TIMER7 |
SL_HAL_SMU_BURTC | SMU peripheral identifier for BURTC |
SL_HAL_SMU_SYSCFGCFGNS | SMU peripheral identifier for SYSCFGCFGNS. |
SL_HAL_SMU_SYSCFG | SMU peripheral identifier for SYSCFG |
SL_HAL_SMU_BURAM | SMU peripheral identifier for BURAM |
SL_HAL_SMU_GPCRC | SMU peripheral identifier for GPCRC |
SL_HAL_SMU_EUSART1 | SMU peripheral identifier for EUSART1 |
SL_HAL_SMU_EUSART2 | SMU peripheral identifier for EUSART2 |
SL_HAL_SMU_EUSART3 | SMU peripheral identifier for EUSART3 |
SL_HAL_SMU_SYSRTC | SMU peripheral identifier for SYSRTC |
SL_HAL_SMU_LCD | SMU peripheral identifier for LCD |
SL_HAL_SMU_VDAC0 | SMU peripheral identifier for VDAC0 |
SL_HAL_SMU_VDAC1 | SMU peripheral identifier for VDAC1 |
SL_HAL_SMU_PCNT | SMU peripheral identifier for PCNT |
SL_HAL_SMU_HFRCO1 | SMU peripheral identifier for HFRCO1 |
SL_HAL_SMU_HFXO0 | SMU peripheral identifier for HFXO0 |
SL_HAL_SMU_DCDC | SMU peripheral identifier for DCDC |
SL_HAL_SMU_LETIMER0 | SMU peripheral identifier for LETIMER |
SL_HAL_SMU_IADC0 | SMU peripheral identifier for IADC0 |
SL_HAL_SMU_ACMP0 | SMU peripheral identifier for ACMP0 |
SL_HAL_SMU_ACMP1 | SMU peripheral identifier for ACMP1 |
SL_HAL_SMU_I2C0 | SMU peripheral identifier for I2C0 |
SL_HAL_SMU_WDOG0 | SMU peripheral identifier for WDOG0 |
SL_HAL_SMU_WDOG1 | SMU peripheral identifier for WDOG1 |
SL_HAL_SMU_AMUXCP0 | SMU peripheral identifier for AMUXCP0 |
SL_HAL_SMU_SMU | SMU peripheral identifier for SMU |
SL_HAL_SMU_SMUCFGNS | SMU peripheral identifier for SMUCFGNS |
SL_HAL_SMU_END | SMU peripheral end. |
Function Documentation#
sl_hal_smu_enable_ppu#
void sl_hal_smu_enable_ppu (bool enable)
Enable or disable PPU of SMU.
Type | Direction | Argument Name | Description |
---|---|---|---|
bool | [in] | enable | Set to true to enable PPU; set to false otherwise. |
sl_hal_smu_init#
void sl_hal_smu_init (const sl_hal_smu_init_t * init)
Initialize PPU of SMU.
Type | Direction | Argument Name | Description |
---|---|---|---|
const sl_hal_smu_init_t * | [in] | init | Pointer to initialization structure that defines which peripherals should only be accessed from privileged mode, and if PPU should be enabled. |
sl_hal_smu_set_privileged_access#
void sl_hal_smu_set_privileged_access (sl_hal_smu_peripheral_id_t peripheral, bool privileged)
Change access settings for a peripheral.
Type | Direction | Argument Name | Description |
---|---|---|---|
sl_hal_smu_peripheral_id_t | [in] | peripheral | ID of the peripheral to change access settings for. |
bool | [in] | privileged | Set to true if the peripheral should only be accessed from privileged mode; set to false otherwise. |
Set to limit access of a peripheral from privileged mode.
sl_hal_smu_get_faulting_peripheral#
sl_hal_smu_peripheral_id_t sl_hal_smu_get_faulting_peripheral (void )
Get the ID of the peripheral that caused an access fault.
Type | Direction | Argument Name | Description |
---|---|---|---|
void | N/A |
Note
The return value is only valid if SMU_IF_PPUPRIV interrupt flag is set.
Returns
ID of the peripheral that caused an access fault.
sl_hal_smu_int_clear#
void sl_hal_smu_int_clear (uint32_t flags)
Clear one or more pending SMU interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | flags | Bitwise logic OR of SMU interrupt sources to clear. |
sl_hal_smu_int_disable#
void sl_hal_smu_int_disable (uint32_t flags)
Disable one or more SMU interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | flags | SMU interrupt sources to disable. |
sl_hal_smu_int_enable#
void sl_hal_smu_int_enable (uint32_t flags)
Enable one or more SMU interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | flags | SMU interrupt sources to enable. |
Note
Depending on the use, a pending interrupt may already be set prior to enabling the interrupt. To ignore a pending interrupt, consider using SMU_IntClear() prior to enabling the interrupt.
sl_hal_smu_int_get#
uint32_t sl_hal_smu_int_get (void )
Get pending SMU interrupts.
Type | Direction | Argument Name | Description |
---|---|---|---|
void | N/A |
Returns
SMU interrupt sources pending.
sl_hal_smu_int_get_enabled#
uint32_t sl_hal_smu_int_get_enabled (void )
Get enabled and pending SMU interrupt flags.
Type | Direction | Argument Name | Description |
---|---|---|---|
void | N/A |
Note
Interrupt flags are not cleared by this function.
Returns
Pending and enabled SMU interrupt sources. The return value is the bitwise AND combination of
the OR combination of enabled interrupt sources in SMU_IEN register and
the OR combination of valid interrupt flags in SMU_IF register.
sl_hal_smu_int_set#
void sl_hal_smu_int_set (uint32_t flags)
Set one or more pending SMU interrupts from SW.
Type | Direction | Argument Name | Description |
---|---|---|---|
uint32_t | [in] | flags | SMU interrupt sources to set to pending. |
SMU_SECURE_IRQHandler#
void SMU_SECURE_IRQHandler (void )
SMU secure IRQ Handler.
Type | Direction | Argument Name | Description |
---|---|---|---|
void | N/A |
When a PPU detects an access to a secure peripheral at its non-secure address or an access to a non-secure peripheral at its secure address, PPUSECIF in SMU_IF is set and the ID of the peripheral being accessed is written to SMU_PPUFS. If PPUSECIEN is set and the SMU's Secure IRQ enabled, the CPU will be interrupted and SMU_SECURE_IRQHandler Will handle the interrupt.