channel_mode#

sl_hal_timer_channel_mode_t sl_hal_timer_channel_init_t::channel_mode

Compare/capture channel mode.

input_type#

sl_hal_timer_channel_input_type_t sl_hal_timer_channel_init_t::input_type

Select Compare/Capture channel input.

compare_match_output_action#

sl_hal_timer_channel_output_action_t sl_hal_timer_channel_init_t::compare_match_output_action

Counter match output action.

compare_underflow_output_action#

sl_hal_timer_channel_output_action_t sl_hal_timer_channel_init_t::compare_underflow_output_action

Counter underflow output action.

compare_overflow_output_action#

sl_hal_timer_channel_output_action_t sl_hal_timer_channel_init_t::compare_overflow_output_action

Counter overflow output action.

input_capture_event#

sl_hal_timer_channel_input_event_t sl_hal_timer_channel_init_t::input_capture_event

Input capture event control.

input_capture_edge#

sl_hal_timer_channel_input_edge_t sl_hal_timer_channel_init_t::input_capture_edge

Input capture edge select.

input_watermark_level#

uint8_t sl_hal_timer_channel_init_t::input_watermark_level

Sets the watermark level of generation of fifo interrupt and DMA requests.

output_initial_state#

bool sl_hal_timer_channel_init_t::output_initial_state

Compare output initial state.

Only used in Output Compare and PWM mode. When true, the compare/PWM output is set high when the counter is disabled. When counting resumes, this value will represent the initial value for the compare/PWM output. If the bit is cleared, the output will be cleared when the counter is disabled.

prs_output#

bool sl_hal_timer_channel_init_t::prs_output

PRS output configuration.

PRS output from a timer can either be a pulse output or a level output that follows the CC out value. if set, prs outputs a level that follows cc out value.

filter#

bool sl_hal_timer_channel_init_t::filter

Enable digital filter.

output_invert#

bool sl_hal_timer_channel_init_t::output_invert

Invert output from compare/capture channel.