Tamper options#

Tamper configuration options.

Levels, signals and filter options.

Macros#

#define
SL_SE_TAMPER_LEVEL_IGNORE 0

No action taken.

#define
SL_SE_TAMPER_LEVEL_INTERRUPT 1

Generate interrupt.

#define
SL_SE_TAMPER_LEVEL_FILTER 2

Increment filter counter.

#define
SL_SE_TAMPER_LEVEL_RESET 4

System reset.

#define
SL_SE_TAMPER_LEVEL_PERMANENTLY_ERASE_OTP 7

Erase OTP - THIS WILL MAKE THE DEVICE INOPERATIONAL!

#define
SL_SE_TAMPER_SIGNAL_RESERVED_1 0x0

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_FILTER_COUNTER 0x1

Filter counter exceeds threshold.

#define
SL_SE_TAMPER_SIGNAL_WATCHDOG 0x2

SE watchdog timeout.

#define
SL_SE_TAMPER_SIGNAL_CRYPTO_ERROR 0x3

Crypto error detected.

#define
SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_2 0x4

SE RAM 2-bit ECC error.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_2 0x5

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_SE_MAJOR_FAULT 0x6

SE major fault detected.

#define
SL_SE_TAMPER_SIGNAL_L2ICACHE 0x7

L2 instruction cache error.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_3 0x8

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_USER_SECURE_BOOT_FAILED 0x9

Secure boot of user code failed.

#define
SL_SE_TAMPER_SIGNAL_MAILBOX_AUTHORIZATION_ERROR 0xA

Unauthorised command received over the Mailbox interface.

#define
SL_SE_TAMPER_SIGNAL_DCI_AUTHORIZATION_ERROR 0xB

Unauthorised command received over the DCI interface.

#define
SL_SE_TAMPER_SIGNAL_SE_SOFTWARE_ASSERTION 0xC

SE software triggers an assert.

#define
SL_SE_TAMPER_SIGNAL_RESERVED_4 0xD

Reserved tamper signal.

#define
SL_SE_TAMPER_SIGNAL_SELFTEST_FAILED 0xE

Integrity error of internal storage is detected.

#define
SL_SE_TAMPER_SIGNAL_TRNG_MONITOR 0xF

TRNG monitor detected lack of entropy.

#define
SL_SE_TAMPER_SIGNAL_SECURE_LOCK_ERROR 0x10

Debug lock internal logic check failed.

#define
SL_SE_TAMPER_ATAMPDET 0x11

Any tamper detection.

#define
SL_SE_TAMPER_SIGNAL_OTP_ALARM 0x12

OTP alarm triggered.

#define
SL_SE_TAMPER_SE_ICACHE_ERROR 0x13

SE ICache RAM error.

#define
SL_SE_TAMPER_SIGNAL_SE_RAM_ECC_1 0x14

SE RAM 1-bit ECC error.

#define
SL_SE_TAMPER_SIGNAL_BOD 0x15

Brown-out-detector threshold alert.

#define
SL_SE_TAMPER_SIGNAL_TEMPERATURE_SENSOR 0x16

On-device temperature sensor.

#define
SL_SE_TAMPER_SIGNAL_DPLL_LOCK_FAIL 0x17

DPLL lock failure.

#define
SL_SE_TAMPER_SIGNAL_SOC_PLL_FAIL 0x18

SoC PLL failure.

#define
SL_SE_TAMPER_SIGNAL_ETAMPDET 0x19

External tamper detect.

#define
SL_SE_TAMPER_SIGNAL_KSU_ECC_1 0x1A

KSU ECC 1-bit error.

#define
SL_SE_TAMPER_SIGNAL_KSU_ECC_2 0x1B

KSU ECC 2-bit error.

#define
SL_SE_TAMPER_SIGNAL_QSPI_RESEED_ERR 0x1C

QSPI reseed error.

#define
SL_SE_TAMPER_SIGNAL_PRS0 0x1D

PRS channel 0 asserted.

#define
SL_SE_TAMPER_SIGNAL_PRS1 0x1E

PRS channel 1 asserted.

#define
SL_SE_TAMPER_SIGNAL_PRS2 0x1F

PRS channel 2 asserted.

#define
SL_SE_TAMPER_SIGNAL_NUM_SIGNALS 0x20

Number of tamper signals.

#define
SL_SE_TAMPER_FILTER_PERIOD_32MS 0x0

Timeout ~32ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_64MS 0x1

Timeout ~64ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_128MS 0x2

Timeout ~128ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_256MS 0x3

Timeout ~256ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_512MS 0x4

Timeout ~512ms.

#define
SL_SE_TAMPER_FILTER_PERIOD_1S 0x5

Timeout ~1s.

#define
SL_SE_TAMPER_FILTER_PERIOD_2S 0x6

Timeout ~2s.

#define
SL_SE_TAMPER_FILTER_PERIOD_4S 0x7

Timeout ~4.1s.

#define
SL_SE_TAMPER_FILTER_PERIOD_8S 0x8

Timeout ~8.2s.

#define
SL_SE_TAMPER_FILTER_PERIOD_16S 0x9

Timeout ~16.4s.

#define
SL_SE_TAMPER_FILTER_PERIOD_33S 0xA

Timeout ~32.8s.

#define
SL_SE_TAMPER_FILTER_PERIOD_1MIN 0xB

Timeout ~1.1min.

#define
SL_SE_TAMPER_FILTER_PERIOD_2MIN 0xC

Timeout ~2.2min.

#define
SL_SE_TAMPER_FILTER_PERIOD_4MIN 0xD

Timeout ~4.4min.

#define
SL_SE_TAMPER_FILTER_PERIOD_9MIN 0xE

Timeout ~8.7min.

#define
SL_SE_TAMPER_FILTER_PERIOD_18MIN 0xF

Timeout ~17.5min.

#define
SL_SE_TAMPER_FILTER_PERIOD_35MIN 0x10

Timeout ~35min.

#define
SL_SE_TAMPER_FILTER_PERIOD_1H 0x11

Timeout ~1.2h.

#define
SL_SE_TAMPER_FILTER_PERIOD_2H 0x12

Timeout ~2.3h.

#define
SL_SE_TAMPER_FILTER_PERIOD_5H 0x13

Timeout ~4.7h.

#define
SL_SE_TAMPER_FILTER_PERIOD_9H 0x14

Timeout ~9.3h.

#define
SL_SE_TAMPER_FILTER_PERIOD_19H 0x15

Timeout ~18.6h.

#define
SL_SE_TAMPER_FILTER_PERIOD_2DAYS 0x16

Timeout ~1.6days.

#define
SL_SE_TAMPER_FILTER_PERIOD_3DAYS 0x17

Timeout ~3.1days.

#define
SL_SE_TAMPER_FILTER_PERIOD_6DAYS 0x18

Timeout ~6.2days.

#define
SL_SE_TAMPER_FILTER_PERIOD_12DAYS 0x19

Timeout ~12.4days.

#define
SL_SE_TAMPER_FILTER_PERIOD_25DAYS 0x1A

Timeout ~24.9days.

#define
SL_SE_TAMPER_FILTER_PERIOD_50DAYS 0x1B

Timeout ~49.7days.

#define
SL_SE_TAMPER_FILTER_PERIOD_100DAYS 0x1C

Timeout ~99.4days.

#define
SL_SE_TAMPER_FILTER_PERIOD_199DAYS 0x1D

Timeout ~198.8days.

#define
SL_SE_TAMPER_FILTER_PERIOD_398DAYS 0x1E

Timeout ~397.7days.

#define
SL_SE_TAMPER_FILTER_PERIOD_795DAYS 0x1F

Timeout ~795.4days.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_2 0x7

Counter threshold 2.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_4 0x6

Counter threshold 4.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_8 0x5

Counter threshold 8.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_16 0x4

Counter threshold 16.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_32 0x3

Counter threshold 32.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_64 0x2

Counter threshold 64.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_128 0x1

Counter threshold 128.

#define
SL_SE_TAMPER_FILTER_THRESHOLD_256 0x0

Counter threshold 256.

#define
SL_SE_TAMPER_FLAG_DGLITCH_ALWAYS_ON (1UL << 1)

Tamper flags.

#define
SL_SE_TAMPER_FLAG_KEEP_TAMPER_ALIVE_DURING_SLEEP (1UL << 2)

Tamper is kept alive during sleep (down to EM3)