QSPI Bit FieldsDevices > QSPI

Macros

#define _QSPI_CONFIG_CRCENABLE_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_CRCENABLE_MASK   0x20000000UL
 
#define _QSPI_CONFIG_CRCENABLE_SHIFT   29
 
#define _QSPI_CONFIG_DEVRSTCONFIG_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_DEVRSTCONFIG_MASK   0x40UL
 
#define _QSPI_CONFIG_DEVRSTCONFIG_SHIFT   6
 
#define _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_DUALBYTEOPCODEEN_MASK   0x40000000UL
 
#define _QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT   30
 
#define _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENABLEAHBDECODER_MASK   0x800000UL
 
#define _QSPI_CONFIG_ENABLEAHBDECODER_SHIFT   23
 
#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK   0x1000000UL
 
#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT   24
 
#define _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENBAHBADDRREMAP_MASK   0x10000UL
 
#define _QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT   16
 
#define _QSPI_CONFIG_ENBDEVHOLD_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENBDEVHOLD_MASK   0x10UL
 
#define _QSPI_CONFIG_ENBDEVHOLD_SHIFT   4
 
#define _QSPI_CONFIG_ENBDEVRST_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENBDEVRST_MASK   0x20UL
 
#define _QSPI_CONFIG_ENBDEVRST_SHIFT   5
 
#define _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT   0x00000001UL
 
#define _QSPI_CONFIG_ENBDIRACCCTLR_MASK   0x80UL
 
#define _QSPI_CONFIG_ENBDIRACCCTLR_SHIFT   7
 
#define _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENBLEGACYIPMODE_MASK   0x100UL
 
#define _QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT   8
 
#define _QSPI_CONFIG_ENBSPI_DEFAULT   0x00000001UL
 
#define _QSPI_CONFIG_ENBSPI_MASK   0x1UL
 
#define _QSPI_CONFIG_ENBSPI_SHIFT   0
 
#define _QSPI_CONFIG_ENTERXIPMODE_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENTERXIPMODE_MASK   0x20000UL
 
#define _QSPI_CONFIG_ENTERXIPMODE_SHIFT   17
 
#define _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_ENTERXIPMODEIMM_MASK   0x40000UL
 
#define _QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT   18
 
#define _QSPI_CONFIG_IDLE_DEFAULT   0x00000001UL
 
#define _QSPI_CONFIG_IDLE_MASK   0x80000000UL
 
#define _QSPI_CONFIG_IDLE_SHIFT   31
 
#define _QSPI_CONFIG_MASK   0xE3FF4FFFUL
 
#define _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT   0x0000000FUL
 
#define _QSPI_CONFIG_MSTRBAUDDIV_MASK   0x780000UL
 
#define _QSPI_CONFIG_MSTRBAUDDIV_SHIFT   19
 
#define _QSPI_CONFIG_PERIPHCSLINES_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_PERIPHCSLINES_MASK   0xC00UL
 
#define _QSPI_CONFIG_PERIPHCSLINES_SHIFT   10
 
#define _QSPI_CONFIG_PERIPHSELDEC_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_PERIPHSELDEC_MASK   0x200UL
 
#define _QSPI_CONFIG_PERIPHSELDEC_SHIFT   9
 
#define _QSPI_CONFIG_PHYMODEENABLE_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_PHYMODEENABLE_MASK   0x8UL
 
#define _QSPI_CONFIG_PHYMODEENABLE_SHIFT   3
 
#define _QSPI_CONFIG_PIPELINEPHY_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_PIPELINEPHY_MASK   0x2000000UL
 
#define _QSPI_CONFIG_PIPELINEPHY_SHIFT   25
 
#define _QSPI_CONFIG_RESETVALUE   0x80780081UL
 
#define _QSPI_CONFIG_SELCLKPHASE_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_SELCLKPHASE_MASK   0x4UL
 
#define _QSPI_CONFIG_SELCLKPHASE_SHIFT   2
 
#define _QSPI_CONFIG_SELCLKPOL_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_SELCLKPOL_MASK   0x2UL
 
#define _QSPI_CONFIG_SELCLKPOL_SHIFT   1
 
#define _QSPI_CONFIG_WRPROTFLASH_DEFAULT   0x00000000UL
 
#define _QSPI_CONFIG_WRPROTFLASH_MASK   0x4000UL
 
#define _QSPI_CONFIG_WRPROTFLASH_SHIFT   14
 
#define _QSPI_DEVDELAY_DAFTER_DEFAULT   0x00000000UL
 
#define _QSPI_DEVDELAY_DAFTER_MASK   0xFF00UL
 
#define _QSPI_DEVDELAY_DAFTER_SHIFT   8
 
#define _QSPI_DEVDELAY_DBTWN_DEFAULT   0x00000000UL
 
#define _QSPI_DEVDELAY_DBTWN_MASK   0xFF0000UL
 
#define _QSPI_DEVDELAY_DBTWN_SHIFT   16
 
#define _QSPI_DEVDELAY_DINIT_DEFAULT   0x00000000UL
 
#define _QSPI_DEVDELAY_DINIT_MASK   0xFFUL
 
#define _QSPI_DEVDELAY_DINIT_SHIFT   0
 
#define _QSPI_DEVDELAY_DNSS_DEFAULT   0x00000000UL
 
#define _QSPI_DEVDELAY_DNSS_MASK   0xFF000000UL
 
#define _QSPI_DEVDELAY_DNSS_SHIFT   24
 
#define _QSPI_DEVDELAY_MASK   0xFFFFFFFFUL
 
#define _QSPI_DEVDELAY_RESETVALUE   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK   0x3000UL
 
#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT   12
 
#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK   0x30000UL
 
#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT   16
 
#define _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_DDREN_MASK   0x400UL
 
#define _QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT   10
 
#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK   0x1F000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT   24
 
#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK   0x300UL
 
#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT   8
 
#define _QSPI_DEVINSTRRDCONFIG_MASK   0x1F1337FFUL
 
#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK   0x100000UL
 
#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT   20
 
#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT   0x00000003UL
 
#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK   0xFFUL
 
#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT   0
 
#define _QSPI_DEVINSTRRDCONFIG_RESETVALUE   0x00000003UL
 
#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK   0x3000UL
 
#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT   12
 
#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK   0x30000UL
 
#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT   16
 
#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK   0x1F000000UL
 
#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT   24
 
#define _QSPI_DEVINSTRWRCONFIG_MASK   0x1F0331FFUL
 
#define _QSPI_DEVINSTRWRCONFIG_RESETVALUE   0x00000002UL
 
#define _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT   0x00000000UL
 
#define _QSPI_DEVINSTRWRCONFIG_WELDIS_MASK   0x100UL
 
#define _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT   8
 
#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT   0x00000002UL
 
#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK   0xFFUL
 
#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT   0
 
#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT   0x00000100UL
 
#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK   0xFFF0UL
 
#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT   4
 
#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT   0x00000010UL
 
#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK   0x1F0000UL
 
#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT   16
 
#define _QSPI_DEVSIZECONFIG_MASK   0x01FFFFFFUL
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT   0x00000000UL
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK   0x600000UL
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT   21
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT   0x00000000UL
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK   0x1800000UL
 
#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT   23
 
#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT   0x00000002UL
 
#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK   0xFUL
 
#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT   0
 
#define _QSPI_DEVSIZECONFIG_RESETVALUE   0x00101002UL
 
#define _QSPI_FLASHCMDADDR_ADDR_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDADDR_ADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHCMDADDR_ADDR_SHIFT   0
 
#define _QSPI_FLASHCMDADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHCMDADDR_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_CMDEXEC_MASK   0x1UL
 
#define _QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT   0
 
#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK   0x2UL
 
#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT   1
 
#define _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_CMDOPCODE_MASK   0xFF000000UL
 
#define _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT   24
 
#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK   0x80000UL
 
#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT   19
 
#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK   0x40000UL
 
#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT   18
 
#define _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_ENBREADDATA_MASK   0x800000UL
 
#define _QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT   23
 
#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK   0x8000UL
 
#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT   15
 
#define _QSPI_FLASHCMDCTRL_MASK   0xFFFFFF87UL
 
#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK   0x30000UL
 
#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT   16
 
#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK   0xF80UL
 
#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT   7
 
#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK   0x700000UL
 
#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT   20
 
#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK   0x7000UL
 
#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT   12
 
#define _QSPI_FLASHCMDCTRL_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK   0x4UL
 
#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT   2
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MASK   0x1FF7FF03UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK   0x1FF00000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT   20
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK   0xFF00UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT   8
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK   0x2UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT   1
 
#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK   0x70000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT   16
 
#define _QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK   0x1UL
 
#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT   0
 
#define _QSPI_FLASHRDDATALOWER_DATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHRDDATALOWER_DATA_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHRDDATALOWER_DATA_SHIFT   0
 
#define _QSPI_FLASHRDDATALOWER_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHRDDATALOWER_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHRDDATAUPPER_DATA_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHRDDATAUPPER_DATA_SHIFT   0
 
#define _QSPI_FLASHRDDATAUPPER_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHRDDATAUPPER_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHWRDATALOWER_DATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHWRDATALOWER_DATA_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHWRDATALOWER_DATA_SHIFT   0
 
#define _QSPI_FLASHWRDATALOWER_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHWRDATALOWER_RESETVALUE   0x00000000UL
 
#define _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT   0x00000000UL
 
#define _QSPI_FLASHWRDATAUPPER_DATA_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHWRDATAUPPER_DATA_SHIFT   0
 
#define _QSPI_FLASHWRDATAUPPER_MASK   0xFFFFFFFFUL
 
#define _QSPI_FLASHWRDATAUPPER_RESETVALUE   0x00000000UL
 
#define _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT   0x00000000UL
 
#define _QSPI_INDAHBADDRTRIGGER_ADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT   0
 
#define _QSPI_INDAHBADDRTRIGGER_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDAHBADDRTRIGGER_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK   0x2UL
 
#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT   1
 
#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK   0x20UL
 
#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT   5
 
#define _QSPI_INDIRECTREADXFERCTRL_MASK   0x000000FFUL
 
#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK   0xC0UL
 
#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT   6
 
#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK   0x10UL
 
#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT   4
 
#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK   0x4UL
 
#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT   2
 
#define _QSPI_INDIRECTREADXFERCTRL_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK   0x8UL
 
#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT   3
 
#define _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERCTRL_START_MASK   0x1UL
 
#define _QSPI_INDIRECTREADXFERCTRL_START_SHIFT   0
 
#define _QSPI_INDIRECTREADXFERNUMBYTES_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT   0
 
#define _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERSTART_ADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT   0
 
#define _QSPI_INDIRECTREADXFERSTART_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERSTART_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT   0
 
#define _QSPI_INDIRECTREADXFERWATERMARK_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT   0x00000004UL
 
#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK   0xFUL
 
#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT   0
 
#define _QSPI_INDIRECTTRIGGERADDRRANGE_MASK   0x0000000FUL
 
#define _QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE   0x00000004UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK   0x2UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT   1
 
#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK   0x20UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT   5
 
#define _QSPI_INDIRECTWRITEXFERCTRL_MASK   0x000000F7UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK   0xC0UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT   6
 
#define _QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_START_MASK   0x1UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT   0
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK   0x10UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT   4
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK   0x4UL
 
#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT   2
 
#define _QSPI_INDIRECTWRITEXFERNUMBYTES_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT   0
 
#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT   0
 
#define _QSPI_INDIRECTWRITEXFERSTART_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERSTART_RESETVALUE   0x00000000UL
 
#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT   0
 
#define _QSPI_INDIRECTWRITEXFERWATERMARK_MASK   0xFFFFFFFFUL
 
#define _QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE   0xFFFFFFFFUL
 
#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK   0x20UL
 
#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT   5
 
#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK   0x4UL
 
#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT   2
 
#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK   0x8UL
 
#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT   3
 
#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK   0x40UL
 
#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT   6
 
#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK   0x1000UL
 
#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT   12
 
#define _QSPI_IRQMASK_MASK   0x00077FFFUL
 
#define _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_MODEMFAILMASK_MASK   0x1UL
 
#define _QSPI_IRQMASK_MODEMFAILMASK_SHIFT   0
 
#define _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_POLLEXPINTMASK_MASK   0x2000UL
 
#define _QSPI_IRQMASK_POLLEXPINTMASK_SHIFT   13
 
#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK   0x10UL
 
#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT   4
 
#define _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_RECVOVERFLOWMASK_MASK   0x80UL
 
#define _QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT   7
 
#define _QSPI_IRQMASK_RESETVALUE   0x00000000UL
 
#define _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_RXCRCDATAERRMASK_MASK   0x10000UL
 
#define _QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT   16
 
#define _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_RXCRCDATAVALMASK_MASK   0x20000UL
 
#define _QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT   17
 
#define _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_RXFIFOFULLMASK_MASK   0x800UL
 
#define _QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT   11
 
#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK   0x400UL
 
#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT   10
 
#define _QSPI_IRQMASK_STIGREQMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_STIGREQMASK_MASK   0x4000UL
 
#define _QSPI_IRQMASK_STIGREQMASK_SHIFT   14
 
#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK   0x40000UL
 
#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT   18
 
#define _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_TXFIFOFULLMASK_MASK   0x200UL
 
#define _QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT   9
 
#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK   0x100UL
 
#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT   8
 
#define _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQMASK_UNDERFLOWDETMASK_MASK   0x2UL
 
#define _QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT   1
 
#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK   0x20UL
 
#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT   5
 
#define _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_INDIRECTOPDONE_MASK   0x4UL
 
#define _QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT   2
 
#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK   0x8UL
 
#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT   3
 
#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK   0x40UL
 
#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT   6
 
#define _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_INDRDSRAMFULL_MASK   0x1000UL
 
#define _QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT   12
 
#define _QSPI_IRQSTATUS_MASK   0x00077FFFUL
 
#define _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_MODEMFAIL_MASK   0x1UL
 
#define _QSPI_IRQSTATUS_MODEMFAIL_SHIFT   0
 
#define _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_POLLEXPINT_MASK   0x2000UL
 
#define _QSPI_IRQSTATUS_POLLEXPINT_SHIFT   13
 
#define _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_PROTWRATTEMPT_MASK   0x10UL
 
#define _QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT   4
 
#define _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_RECVOVERFLOW_MASK   0x80UL
 
#define _QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT   7
 
#define _QSPI_IRQSTATUS_RESETVALUE   0x00000000UL
 
#define _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_RXCRCDATAERR_MASK   0x10000UL
 
#define _QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT   16
 
#define _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_RXCRCDATAVAL_MASK   0x20000UL
 
#define _QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT   17
 
#define _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_RXFIFOFULL_MASK   0x800UL
 
#define _QSPI_IRQSTATUS_RXFIFOFULL_SHIFT   11
 
#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK   0x400UL
 
#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT   10
 
#define _QSPI_IRQSTATUS_STIGREQINT_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_STIGREQINT_MASK   0x4000UL
 
#define _QSPI_IRQSTATUS_STIGREQINT_SHIFT   14
 
#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK   0x40000UL
 
#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT   18
 
#define _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_TXFIFOFULL_MASK   0x200UL
 
#define _QSPI_IRQSTATUS_TXFIFOFULL_SHIFT   9
 
#define _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_TXFIFONOTFULL_MASK   0x100UL
 
#define _QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT   8
 
#define _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT   0x00000000UL
 
#define _QSPI_IRQSTATUS_UNDERFLOWDET_MASK   0x2UL
 
#define _QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT   1
 
#define _QSPI_LOWERWRPROT_MASK   0xFFFFFFFFUL
 
#define _QSPI_LOWERWRPROT_RESETVALUE   0x00000000UL
 
#define _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT   0x00000000UL
 
#define _QSPI_LOWERWRPROT_SUBSECTOR_MASK   0xFFFFFFFFUL
 
#define _QSPI_LOWERWRPROT_SUBSECTOR_SHIFT   0
 
#define _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT   0x00000002UL
 
#define _QSPI_MODEBITCONFIG_CHUNKSIZE_MASK   0x700UL
 
#define _QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT   8
 
#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT   0x00000000UL
 
#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK   0x8000UL
 
#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT   15
 
#define _QSPI_MODEBITCONFIG_MASK   0xFFFF87FFUL
 
#define _QSPI_MODEBITCONFIG_MODE_DEFAULT   0x00000000UL
 
#define _QSPI_MODEBITCONFIG_MODE_MASK   0xFFUL
 
#define _QSPI_MODEBITCONFIG_MODE_SHIFT   0
 
#define _QSPI_MODEBITCONFIG_RESETVALUE   0x00000200UL
 
#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT   0x00000000UL
 
#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK   0xFF000000UL
 
#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT   24
 
#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT   0x00000000UL
 
#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK   0xFF0000UL
 
#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT   16
 
#define _QSPI_MODULEID_CONF_DEFAULT   0x00000000UL
 
#define _QSPI_MODULEID_CONF_MASK   0x3UL
 
#define _QSPI_MODULEID_CONF_SHIFT   0
 
#define _QSPI_MODULEID_FIXPATCH_DEFAULT   0x00000004UL
 
#define _QSPI_MODULEID_FIXPATCH_MASK   0xFF000000UL
 
#define _QSPI_MODULEID_FIXPATCH_SHIFT   24
 
#define _QSPI_MODULEID_MASK   0xFFFFFF03UL
 
#define _QSPI_MODULEID_MODULEID_DEFAULT   0x00000003UL
 
#define _QSPI_MODULEID_MODULEID_MASK   0xFFFF00UL
 
#define _QSPI_MODULEID_MODULEID_SHIFT   8
 
#define _QSPI_MODULEID_RESETVALUE   0x04000300UL
 
#define _QSPI_NOOFPOLLSBEFEXP_MASK   0xFFFFFFFFUL
 
#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT   0xFFFFFFFFUL
 
#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK   0xFFFFFFFFUL
 
#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT   0
 
#define _QSPI_NOOFPOLLSBEFEXP_RESETVALUE   0xFFFFFFFFUL
 
#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT   0x000000FAUL
 
#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK   0xFF00UL
 
#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT   8
 
#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT   0x00000013UL
 
#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK   0xFF000000UL
 
#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT   24
 
#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT   0x00000000UL
 
#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK   0xFFUL
 
#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT   0
 
#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT   0x000000EDUL
 
#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK   0xFF0000UL
 
#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT   16
 
#define _QSPI_OPCODEEXTLOWER_MASK   0xFFFFFFFFUL
 
#define _QSPI_OPCODEEXTLOWER_RESETVALUE   0x13EDFA00UL
 
#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT   0x000000F9UL
 
#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK   0xFF0000UL
 
#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT   16
 
#define _QSPI_OPCODEEXTUPPER_MASK   0xFFFF0000UL
 
#define _QSPI_OPCODEEXTUPPER_RESETVALUE   0x06F90000UL
 
#define _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT   0x00000006UL
 
#define _QSPI_OPCODEEXTUPPER_WELOPCODE_MASK   0xFF000000UL
 
#define _QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT   24
 
#define _QSPI_PHYCONFIGURATION_MASK   0x807F007FUL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT   0x00000000UL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK   0x80000000UL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT   31
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT   0x00000000UL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK   0x7FUL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT   0
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT   0x00000000UL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK   0x7F0000UL
 
#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT   16
 
#define _QSPI_PHYCONFIGURATION_RESETVALUE   0x00000000UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT   0x00000000UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK   0xFFUL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT   0
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT   0x00000000UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK   0xF0000UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT   16
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT   0x00000000UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK   0x100UL
 
#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT   8
 
#define _QSPI_POLLINGFLASHSTATUS_MASK   0x000F01FFUL
 
#define _QSPI_POLLINGFLASHSTATUS_RESETVALUE   0x00000000UL
 
#define _QSPI_RDDATACAPTURE_BYPASS_DEFAULT   0x00000001UL
 
#define _QSPI_RDDATACAPTURE_BYPASS_MASK   0x1UL
 
#define _QSPI_RDDATACAPTURE_BYPASS_SHIFT   0
 
#define _QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT   0x00000000UL
 
#define _QSPI_RDDATACAPTURE_DDRREADDELAY_MASK   0xF0000UL
 
#define _QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT   16
 
#define _QSPI_RDDATACAPTURE_DELAY_DEFAULT   0x00000000UL
 
#define _QSPI_RDDATACAPTURE_DELAY_MASK   0x1EUL
 
#define _QSPI_RDDATACAPTURE_DELAY_SHIFT   1
 
#define _QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT   0x00000000UL
 
#define _QSPI_RDDATACAPTURE_DQSENABLE_MASK   0x100UL
 
#define _QSPI_RDDATACAPTURE_DQSENABLE_SHIFT   8
 
#define _QSPI_RDDATACAPTURE_MASK   0x000F011FUL
 
#define _QSPI_RDDATACAPTURE_RESETVALUE   0x00000001UL
 
#define _QSPI_REMAPADDR_MASK   0xFFFFFFFFUL
 
#define _QSPI_REMAPADDR_RESETVALUE   0x00000000UL
 
#define _QSPI_REMAPADDR_VALUE_DEFAULT   0x00000000UL
 
#define _QSPI_REMAPADDR_VALUE_MASK   0xFFFFFFFFUL
 
#define _QSPI_REMAPADDR_VALUE_SHIFT   0
 
#define _QSPI_ROUTELOC0_MASK   0x00000041UL
 
#define _QSPI_ROUTELOC0_QSPILOC_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTELOC0_QSPILOC_LOC0   0x00000000UL
 
#define _QSPI_ROUTELOC0_QSPILOC_LOC1   0x00000001UL
 
#define _QSPI_ROUTELOC0_QSPILOC_MASK   0x1UL
 
#define _QSPI_ROUTELOC0_QSPILOC_SHIFT   0
 
#define _QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTELOC0_QSPIRSTLOC_LOC0   0x00000000UL
 
#define _QSPI_ROUTELOC0_QSPIRSTLOC_LOC1   0x00000001UL
 
#define _QSPI_ROUTELOC0_QSPIRSTLOC_MASK   0x40UL
 
#define _QSPI_ROUTELOC0_QSPIRSTLOC_SHIFT   6
 
#define _QSPI_ROUTELOC0_RESETVALUE   0x00000000UL
 
#define _QSPI_ROUTEPEN_CS0PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_CS0PEN_MASK   0x2UL
 
#define _QSPI_ROUTEPEN_CS0PEN_SHIFT   1
 
#define _QSPI_ROUTEPEN_CS1PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_CS1PEN_MASK   0x4UL
 
#define _QSPI_ROUTEPEN_CS1PEN_SHIFT   2
 
#define _QSPI_ROUTEPEN_DQ0PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ0PEN_MASK   0x20UL
 
#define _QSPI_ROUTEPEN_DQ0PEN_SHIFT   5
 
#define _QSPI_ROUTEPEN_DQ1PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ1PEN_MASK   0x40UL
 
#define _QSPI_ROUTEPEN_DQ1PEN_SHIFT   6
 
#define _QSPI_ROUTEPEN_DQ2PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ2PEN_MASK   0x80UL
 
#define _QSPI_ROUTEPEN_DQ2PEN_SHIFT   7
 
#define _QSPI_ROUTEPEN_DQ3PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ3PEN_MASK   0x100UL
 
#define _QSPI_ROUTEPEN_DQ3PEN_SHIFT   8
 
#define _QSPI_ROUTEPEN_DQ4PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ4PEN_MASK   0x200UL
 
#define _QSPI_ROUTEPEN_DQ4PEN_SHIFT   9
 
#define _QSPI_ROUTEPEN_DQ5PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ5PEN_MASK   0x400UL
 
#define _QSPI_ROUTEPEN_DQ5PEN_SHIFT   10
 
#define _QSPI_ROUTEPEN_DQ6PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ6PEN_MASK   0x800UL
 
#define _QSPI_ROUTEPEN_DQ6PEN_SHIFT   11
 
#define _QSPI_ROUTEPEN_DQ7PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQ7PEN_MASK   0x1000UL
 
#define _QSPI_ROUTEPEN_DQ7PEN_SHIFT   12
 
#define _QSPI_ROUTEPEN_DQSPEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_DQSPEN_MASK   0x2000UL
 
#define _QSPI_ROUTEPEN_DQSPEN_SHIFT   13
 
#define _QSPI_ROUTEPEN_MASK   0x00037FE7UL
 
#define _QSPI_ROUTEPEN_RESETVALUE   0x00000000UL
 
#define _QSPI_ROUTEPEN_RST0PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_RST0PEN_MASK   0x10000UL
 
#define _QSPI_ROUTEPEN_RST0PEN_SHIFT   16
 
#define _QSPI_ROUTEPEN_RST1PEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_RST1PEN_MASK   0x20000UL
 
#define _QSPI_ROUTEPEN_RST1PEN_SHIFT   17
 
#define _QSPI_ROUTEPEN_SCLKINPEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_SCLKINPEN_MASK   0x4000UL
 
#define _QSPI_ROUTEPEN_SCLKINPEN_SHIFT   14
 
#define _QSPI_ROUTEPEN_SCLKPEN_DEFAULT   0x00000000UL
 
#define _QSPI_ROUTEPEN_SCLKPEN_MASK   0x1UL
 
#define _QSPI_ROUTEPEN_SCLKPEN_SHIFT   0
 
#define _QSPI_RXTHRESH_LEVEL_DEFAULT   0x00000001UL
 
#define _QSPI_RXTHRESH_LEVEL_MASK   0x1FUL
 
#define _QSPI_RXTHRESH_LEVEL_SHIFT   0
 
#define _QSPI_RXTHRESH_MASK   0x0000001FUL
 
#define _QSPI_RXTHRESH_RESETVALUE   0x00000001UL
 
#define _QSPI_SRAMFILL_MASK   0xFFFFFFFFUL
 
#define _QSPI_SRAMFILL_RESETVALUE   0x00000000UL
 
#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT   0x00000000UL
 
#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK   0xFFFFUL
 
#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT   0
 
#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT   0x00000000UL
 
#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK   0xFFFF0000UL
 
#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT   16
 
#define _QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT   0x00000080UL
 
#define _QSPI_SRAMPARTITIONCFG_ADDR_MASK   0xFFUL
 
#define _QSPI_SRAMPARTITIONCFG_ADDR_SHIFT   0
 
#define _QSPI_SRAMPARTITIONCFG_MASK   0x000000FFUL
 
#define _QSPI_SRAMPARTITIONCFG_RESETVALUE   0x00000080UL
 
#define _QSPI_TXTHRESH_LEVEL_DEFAULT   0x00000001UL
 
#define _QSPI_TXTHRESH_LEVEL_MASK   0x1FUL
 
#define _QSPI_TXTHRESH_LEVEL_SHIFT   0
 
#define _QSPI_TXTHRESH_MASK   0x0000001FUL
 
#define _QSPI_TXTHRESH_RESETVALUE   0x00000001UL
 
#define _QSPI_UPPERWRPROT_MASK   0xFFFFFFFFUL
 
#define _QSPI_UPPERWRPROT_RESETVALUE   0x00000000UL
 
#define _QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT   0x00000000UL
 
#define _QSPI_UPPERWRPROT_SUBSECTOR_MASK   0xFFFFFFFFUL
 
#define _QSPI_UPPERWRPROT_SUBSECTOR_SHIFT   0
 
#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT   0x00000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK   0x4000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT   14
 
#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT   0x00000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK   0x8000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT   15
 
#define _QSPI_WRITECOMPLETIONCTRL_MASK   0xFFFFE7FFUL
 
#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT   0x00000005UL
 
#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK   0xFFUL
 
#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT   0
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT   0x00000001UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK   0xFF0000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT   16
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT   0x00000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK   0x700UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT   8
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT   0x00000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK   0x2000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT   13
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT   0x00000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK   0xFF000000UL
 
#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT   24
 
#define _QSPI_WRITECOMPLETIONCTRL_RESETVALUE   0x00010005UL
 
#define _QSPI_WRPROTCTRL_ENB_DEFAULT   0x00000000UL
 
#define _QSPI_WRPROTCTRL_ENB_MASK   0x2UL
 
#define _QSPI_WRPROTCTRL_ENB_SHIFT   1
 
#define _QSPI_WRPROTCTRL_INV_DEFAULT   0x00000000UL
 
#define _QSPI_WRPROTCTRL_INV_MASK   0x1UL
 
#define _QSPI_WRPROTCTRL_INV_SHIFT   0
 
#define _QSPI_WRPROTCTRL_MASK   0x00000003UL
 
#define _QSPI_WRPROTCTRL_RESETVALUE   0x00000000UL
 
#define QSPI_CONFIG_CRCENABLE   (0x1UL << 29)
 
#define QSPI_CONFIG_CRCENABLE_DEFAULT   (_QSPI_CONFIG_CRCENABLE_DEFAULT << 29)
 
#define QSPI_CONFIG_DEVRSTCONFIG   (0x1UL << 6)
 
#define QSPI_CONFIG_DEVRSTCONFIG_DEFAULT   (_QSPI_CONFIG_DEVRSTCONFIG_DEFAULT << 6)
 
#define QSPI_CONFIG_DUALBYTEOPCODEEN   (0x1UL << 30)
 
#define QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT   (_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30)
 
#define QSPI_CONFIG_ENABLEAHBDECODER   (0x1UL << 23)
 
#define QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT   (_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23)
 
#define QSPI_CONFIG_ENABLEDTRPROTOCOL   (0x1UL << 24)
 
#define QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT   (_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24)
 
#define QSPI_CONFIG_ENBAHBADDRREMAP   (0x1UL << 16)
 
#define QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT   (_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16)
 
#define QSPI_CONFIG_ENBDEVHOLD   (0x1UL << 4)
 
#define QSPI_CONFIG_ENBDEVHOLD_DEFAULT   (_QSPI_CONFIG_ENBDEVHOLD_DEFAULT << 4)
 
#define QSPI_CONFIG_ENBDEVRST   (0x1UL << 5)
 
#define QSPI_CONFIG_ENBDEVRST_DEFAULT   (_QSPI_CONFIG_ENBDEVRST_DEFAULT << 5)
 
#define QSPI_CONFIG_ENBDIRACCCTLR   (0x1UL << 7)
 
#define QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT   (_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7)
 
#define QSPI_CONFIG_ENBLEGACYIPMODE   (0x1UL << 8)
 
#define QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT   (_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8)
 
#define QSPI_CONFIG_ENBSPI   (0x1UL << 0)
 
#define QSPI_CONFIG_ENBSPI_DEFAULT   (_QSPI_CONFIG_ENBSPI_DEFAULT << 0)
 
#define QSPI_CONFIG_ENTERXIPMODE   (0x1UL << 17)
 
#define QSPI_CONFIG_ENTERXIPMODE_DEFAULT   (_QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17)
 
#define QSPI_CONFIG_ENTERXIPMODEIMM   (0x1UL << 18)
 
#define QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT   (_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18)
 
#define QSPI_CONFIG_IDLE   (0x1UL << 31)
 
#define QSPI_CONFIG_IDLE_DEFAULT   (_QSPI_CONFIG_IDLE_DEFAULT << 31)
 
#define QSPI_CONFIG_MSTRBAUDDIV_DEFAULT   (_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19)
 
#define QSPI_CONFIG_PERIPHCSLINES_DEFAULT   (_QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10)
 
#define QSPI_CONFIG_PERIPHSELDEC   (0x1UL << 9)
 
#define QSPI_CONFIG_PERIPHSELDEC_DEFAULT   (_QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9)
 
#define QSPI_CONFIG_PHYMODEENABLE   (0x1UL << 3)
 
#define QSPI_CONFIG_PHYMODEENABLE_DEFAULT   (_QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3)
 
#define QSPI_CONFIG_PIPELINEPHY   (0x1UL << 25)
 
#define QSPI_CONFIG_PIPELINEPHY_DEFAULT   (_QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25)
 
#define QSPI_CONFIG_SELCLKPHASE   (0x1UL << 2)
 
#define QSPI_CONFIG_SELCLKPHASE_DEFAULT   (_QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2)
 
#define QSPI_CONFIG_SELCLKPOL   (0x1UL << 1)
 
#define QSPI_CONFIG_SELCLKPOL_DEFAULT   (_QSPI_CONFIG_SELCLKPOL_DEFAULT << 1)
 
#define QSPI_CONFIG_WRPROTFLASH   (0x1UL << 14)
 
#define QSPI_CONFIG_WRPROTFLASH_DEFAULT   (_QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14)
 
#define QSPI_DEVDELAY_DAFTER_DEFAULT   (_QSPI_DEVDELAY_DAFTER_DEFAULT << 8)
 
#define QSPI_DEVDELAY_DBTWN_DEFAULT   (_QSPI_DEVDELAY_DBTWN_DEFAULT << 16)
 
#define QSPI_DEVDELAY_DINIT_DEFAULT   (_QSPI_DEVDELAY_DINIT_DEFAULT << 0)
 
#define QSPI_DEVDELAY_DNSS_DEFAULT   (_QSPI_DEVDELAY_DNSS_DEFAULT << 24)
 
#define QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)
 
#define QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)
 
#define QSPI_DEVINSTRRDCONFIG_DDREN   (0x1UL << 10)
 
#define QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10)
 
#define QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24)
 
#define QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8)
 
#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE   (0x1UL << 20)
 
#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20)
 
#define QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0)
 
#define QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)
 
#define QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)
 
#define QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24)
 
#define QSPI_DEVINSTRWRCONFIG_WELDIS   (0x1UL << 8)
 
#define QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8)
 
#define QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0)
 
#define QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT   (_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4)
 
#define QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT   (_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16)
 
#define QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT   (_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21)
 
#define QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT   (_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23)
 
#define QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT   (_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0)
 
#define QSPI_FLASHCMDADDR_ADDR_DEFAULT   (_QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0)
 
#define QSPI_FLASHCMDCTRL_CMDEXEC   (0x1UL << 0)
 
#define QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0)
 
#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS   (0x1UL << 1)
 
#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1)
 
#define QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24)
 
#define QSPI_FLASHCMDCTRL_ENBCOMDADDR   (0x1UL << 19)
 
#define QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19)
 
#define QSPI_FLASHCMDCTRL_ENBMODEBIT   (0x1UL << 18)
 
#define QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18)
 
#define QSPI_FLASHCMDCTRL_ENBREADDATA   (0x1UL << 23)
 
#define QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23)
 
#define QSPI_FLASHCMDCTRL_ENBWRITEDATA   (0x1UL << 15)
 
#define QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15)
 
#define QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16)
 
#define QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7)
 
#define QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20)
 
#define QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12)
 
#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN   (0x1UL << 2)
 
#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT   (_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2)
 
#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20)
 
#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8)
 
#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS   (0x1UL << 1)
 
#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1)
 
#define QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16)
 
#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ   (0x1UL << 0)
 
#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0)
 
#define QSPI_FLASHRDDATALOWER_DATA_DEFAULT   (_QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0)
 
#define QSPI_FLASHRDDATAUPPER_DATA_DEFAULT   (_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0)
 
#define QSPI_FLASHWRDATALOWER_DATA_DEFAULT   (_QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0)
 
#define QSPI_FLASHWRDATAUPPER_DATA_DEFAULT   (_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0)
 
#define QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT   (_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0)
 
#define QSPI_INDIRECTREADXFERCTRL_CANCEL   (0x1UL << 1)
 
#define QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1)
 
#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS   (0x1UL << 5)
 
#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)
 
#define QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)
 
#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED   (0x1UL << 4)
 
#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4)
 
#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS   (0x1UL << 2)
 
#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2)
 
#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL   (0x1UL << 3)
 
#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3)
 
#define QSPI_INDIRECTREADXFERCTRL_START   (0x1UL << 0)
 
#define QSPI_INDIRECTREADXFERCTRL_START_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0)
 
#define QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT   (_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0)
 
#define QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT   (_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0)
 
#define QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT   (_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0)
 
#define QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT   (_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0)
 
#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL   (0x1UL << 1)
 
#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1)
 
#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS   (0x1UL << 5)
 
#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)
 
#define QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)
 
#define QSPI_INDIRECTWRITEXFERCTRL_START   (0x1UL << 0)
 
#define QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0)
 
#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED   (0x1UL << 4)
 
#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4)
 
#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS   (0x1UL << 2)
 
#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2)
 
#define QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT   (_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0)
 
#define QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT   (_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0)
 
#define QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT   (_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0)
 
#define QSPI_IRQMASK_ILLEGALACCESSDETMASK   (0x1UL << 5)
 
#define QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT   (_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5)
 
#define QSPI_IRQMASK_INDIRECTOPDONEMASK   (0x1UL << 2)
 
#define QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2)
 
#define QSPI_IRQMASK_INDIRECTREADREJECTMASK   (0x1UL << 3)
 
#define QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3)
 
#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK   (0x1UL << 6)
 
#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6)
 
#define QSPI_IRQMASK_INDRDSRAMFULLMASK   (0x1UL << 12)
 
#define QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT   (_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12)
 
#define QSPI_IRQMASK_MODEMFAILMASK   (0x1UL << 0)
 
#define QSPI_IRQMASK_MODEMFAILMASK_DEFAULT   (_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0)
 
#define QSPI_IRQMASK_POLLEXPINTMASK   (0x1UL << 13)
 
#define QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT   (_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13)
 
#define QSPI_IRQMASK_PROTWRATTEMPTMASK   (0x1UL << 4)
 
#define QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT   (_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4)
 
#define QSPI_IRQMASK_RECVOVERFLOWMASK   (0x1UL << 7)
 
#define QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT   (_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7)
 
#define QSPI_IRQMASK_RXCRCDATAERRMASK   (0x1UL << 16)
 
#define QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT   (_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16)
 
#define QSPI_IRQMASK_RXCRCDATAVALMASK   (0x1UL << 17)
 
#define QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT   (_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17)
 
#define QSPI_IRQMASK_RXFIFOFULLMASK   (0x1UL << 11)
 
#define QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT   (_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11)
 
#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK   (0x1UL << 10)
 
#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT   (_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10)
 
#define QSPI_IRQMASK_STIGREQMASK   (0x1UL << 14)
 
#define QSPI_IRQMASK_STIGREQMASK_DEFAULT   (_QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14)
 
#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK   (0x1UL << 18)
 
#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT   (_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18)
 
#define QSPI_IRQMASK_TXFIFOFULLMASK   (0x1UL << 9)
 
#define QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT   (_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9)
 
#define QSPI_IRQMASK_TXFIFONOTFULLMASK   (0x1UL << 8)
 
#define QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT   (_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8)
 
#define QSPI_IRQMASK_UNDERFLOWDETMASK   (0x1UL << 1)
 
#define QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT   (_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1)
 
#define QSPI_IRQSTATUS_ILLEGALACCESSDET   (0x1UL << 5)
 
#define QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT   (_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5)
 
#define QSPI_IRQSTATUS_INDIRECTOPDONE   (0x1UL << 2)
 
#define QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2)
 
#define QSPI_IRQSTATUS_INDIRECTREADREJECT   (0x1UL << 3)
 
#define QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3)
 
#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH   (0x1UL << 6)
 
#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6)
 
#define QSPI_IRQSTATUS_INDRDSRAMFULL   (0x1UL << 12)
 
#define QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT   (_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12)
 
#define QSPI_IRQSTATUS_MODEMFAIL   (0x1UL << 0)
 
#define QSPI_IRQSTATUS_MODEMFAIL_DEFAULT   (_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0)
 
#define QSPI_IRQSTATUS_POLLEXPINT   (0x1UL << 13)
 
#define QSPI_IRQSTATUS_POLLEXPINT_DEFAULT   (_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13)
 
#define QSPI_IRQSTATUS_PROTWRATTEMPT   (0x1UL << 4)
 
#define QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT   (_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4)
 
#define QSPI_IRQSTATUS_RECVOVERFLOW   (0x1UL << 7)
 
#define QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT   (_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7)
 
#define QSPI_IRQSTATUS_RXCRCDATAERR   (0x1UL << 16)
 
#define QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT   (_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16)
 
#define QSPI_IRQSTATUS_RXCRCDATAVAL   (0x1UL << 17)
 
#define QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT   (_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17)
 
#define QSPI_IRQSTATUS_RXFIFOFULL   (0x1UL << 11)
 
#define QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT   (_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11)
 
#define QSPI_IRQSTATUS_RXFIFONOTEMPTY   (0x1UL << 10)
 
#define QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT   (_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10)
 
#define QSPI_IRQSTATUS_STIGREQINT   (0x1UL << 14)
 
#define QSPI_IRQSTATUS_STIGREQINT_DEFAULT   (_QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14)
 
#define QSPI_IRQSTATUS_TXCRCCHUNKBRK   (0x1UL << 18)
 
#define QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT   (_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18)
 
#define QSPI_IRQSTATUS_TXFIFOFULL   (0x1UL << 9)
 
#define QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT   (_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9)
 
#define QSPI_IRQSTATUS_TXFIFONOTFULL   (0x1UL << 8)
 
#define QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT   (_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8)
 
#define QSPI_IRQSTATUS_UNDERFLOWDET   (0x1UL << 1)
 
#define QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT   (_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1)
 
#define QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT   (_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0)
 
#define QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT   (_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8)
 
#define QSPI_MODEBITCONFIG_CRCOUTENABLE   (0x1UL << 15)
 
#define QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT   (_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15)
 
#define QSPI_MODEBITCONFIG_MODE_DEFAULT   (_QSPI_MODEBITCONFIG_MODE_DEFAULT << 0)
 
#define QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT   (_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24)
 
#define QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT   (_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16)
 
#define QSPI_MODULEID_CONF_DEFAULT   (_QSPI_MODULEID_CONF_DEFAULT << 0)
 
#define QSPI_MODULEID_FIXPATCH_DEFAULT   (_QSPI_MODULEID_FIXPATCH_DEFAULT << 24)
 
#define QSPI_MODULEID_MODULEID_DEFAULT   (_QSPI_MODULEID_MODULEID_DEFAULT << 8)
 
#define QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT   (_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0)
 
#define QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8)
 
#define QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24)
 
#define QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0)
 
#define QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16)
 
#define QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT   (_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16)
 
#define QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT   (_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24)
 
#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC   (0x1UL << 31)
 
#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31)
 
#define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0)
 
#define QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16)
 
#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT << 0)
 
#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT << 16)
 
#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID   (0x1UL << 8)
 
#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT << 8)
 
#define QSPI_RDDATACAPTURE_BYPASS   (0x1UL << 0)
 
#define QSPI_RDDATACAPTURE_BYPASS_DEFAULT   (_QSPI_RDDATACAPTURE_BYPASS_DEFAULT << 0)
 
#define QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT   (_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT << 16)
 
#define QSPI_RDDATACAPTURE_DELAY_DEFAULT   (_QSPI_RDDATACAPTURE_DELAY_DEFAULT << 1)
 
#define QSPI_RDDATACAPTURE_DQSENABLE   (0x1UL << 8)
 
#define QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT   (_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT << 8)
 
#define QSPI_REMAPADDR_VALUE_DEFAULT   (_QSPI_REMAPADDR_VALUE_DEFAULT << 0)
 
#define QSPI_ROUTELOC0_QSPILOC_DEFAULT   (_QSPI_ROUTELOC0_QSPILOC_DEFAULT << 0)
 
#define QSPI_ROUTELOC0_QSPILOC_LOC0   (_QSPI_ROUTELOC0_QSPILOC_LOC0 << 0)
 
#define QSPI_ROUTELOC0_QSPILOC_LOC1   (_QSPI_ROUTELOC0_QSPILOC_LOC1 << 0)
 
#define QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT   (_QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT << 6)
 
#define QSPI_ROUTELOC0_QSPIRSTLOC_LOC0   (_QSPI_ROUTELOC0_QSPIRSTLOC_LOC0 << 6)
 
#define QSPI_ROUTELOC0_QSPIRSTLOC_LOC1   (_QSPI_ROUTELOC0_QSPIRSTLOC_LOC1 << 6)
 
#define QSPI_ROUTEPEN_CS0PEN   (0x1UL << 1)
 
#define QSPI_ROUTEPEN_CS0PEN_DEFAULT   (_QSPI_ROUTEPEN_CS0PEN_DEFAULT << 1)
 
#define QSPI_ROUTEPEN_CS1PEN   (0x1UL << 2)
 
#define QSPI_ROUTEPEN_CS1PEN_DEFAULT   (_QSPI_ROUTEPEN_CS1PEN_DEFAULT << 2)
 
#define QSPI_ROUTEPEN_DQ0PEN   (0x1UL << 5)
 
#define QSPI_ROUTEPEN_DQ0PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ0PEN_DEFAULT << 5)
 
#define QSPI_ROUTEPEN_DQ1PEN   (0x1UL << 6)
 
#define QSPI_ROUTEPEN_DQ1PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ1PEN_DEFAULT << 6)
 
#define QSPI_ROUTEPEN_DQ2PEN   (0x1UL << 7)
 
#define QSPI_ROUTEPEN_DQ2PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ2PEN_DEFAULT << 7)
 
#define QSPI_ROUTEPEN_DQ3PEN   (0x1UL << 8)
 
#define QSPI_ROUTEPEN_DQ3PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ3PEN_DEFAULT << 8)
 
#define QSPI_ROUTEPEN_DQ4PEN   (0x1UL << 9)
 
#define QSPI_ROUTEPEN_DQ4PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ4PEN_DEFAULT << 9)
 
#define QSPI_ROUTEPEN_DQ5PEN   (0x1UL << 10)
 
#define QSPI_ROUTEPEN_DQ5PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ5PEN_DEFAULT << 10)
 
#define QSPI_ROUTEPEN_DQ6PEN   (0x1UL << 11)
 
#define QSPI_ROUTEPEN_DQ6PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ6PEN_DEFAULT << 11)
 
#define QSPI_ROUTEPEN_DQ7PEN   (0x1UL << 12)
 
#define QSPI_ROUTEPEN_DQ7PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ7PEN_DEFAULT << 12)
 
#define QSPI_ROUTEPEN_DQSPEN   (0x1UL << 13)
 
#define QSPI_ROUTEPEN_DQSPEN_DEFAULT   (_QSPI_ROUTEPEN_DQSPEN_DEFAULT << 13)
 
#define QSPI_ROUTEPEN_RST0PEN   (0x1UL << 16)
 
#define QSPI_ROUTEPEN_RST0PEN_DEFAULT   (_QSPI_ROUTEPEN_RST0PEN_DEFAULT << 16)
 
#define QSPI_ROUTEPEN_RST1PEN   (0x1UL << 17)
 
#define QSPI_ROUTEPEN_RST1PEN_DEFAULT   (_QSPI_ROUTEPEN_RST1PEN_DEFAULT << 17)
 
#define QSPI_ROUTEPEN_SCLKINPEN   (0x1UL << 14)
 
#define QSPI_ROUTEPEN_SCLKINPEN_DEFAULT   (_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT << 14)
 
#define QSPI_ROUTEPEN_SCLKPEN   (0x1UL << 0)
 
#define QSPI_ROUTEPEN_SCLKPEN_DEFAULT   (_QSPI_ROUTEPEN_SCLKPEN_DEFAULT << 0)
 
#define QSPI_RXTHRESH_LEVEL_DEFAULT   (_QSPI_RXTHRESH_LEVEL_DEFAULT << 0)
 
#define QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT   (_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT << 0)
 
#define QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT   (_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT << 16)
 
#define QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT   (_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT << 0)
 
#define QSPI_TXTHRESH_LEVEL_DEFAULT   (_QSPI_TXTHRESH_LEVEL_DEFAULT << 0)
 
#define QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT   (_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT << 0)
 
#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING   (0x1UL << 14)
 
#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT << 14)
 
#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP   (0x1UL << 15)
 
#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT << 15)
 
#define QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT << 0)
 
#define QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT << 16)
 
#define QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT << 8)
 
#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY   (0x1UL << 13)
 
#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT << 13)
 
#define QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT << 24)
 
#define QSPI_WRPROTCTRL_ENB   (0x1UL << 1)
 
#define QSPI_WRPROTCTRL_ENB_DEFAULT   (_QSPI_WRPROTCTRL_ENB_DEFAULT << 1)
 
#define QSPI_WRPROTCTRL_INV   (0x1UL << 0)
 
#define QSPI_WRPROTCTRL_INV_DEFAULT   (_QSPI_WRPROTCTRL_INV_DEFAULT << 0)
 

Macro Definition Documentation

#define _QSPI_CONFIG_CRCENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 210 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_CRCENABLE_MASK   0x20000000UL

Bit mask for QSPI_CRCENABLE

Definition at line 209 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_CRCENABLE_SHIFT   29

Shift value for QSPI_CRCENABLE

Definition at line 208 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DEVRSTCONFIG_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 147 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DEVRSTCONFIG_MASK   0x40UL

Bit mask for QSPI_DEVRSTCONFIG

Definition at line 146 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DEVRSTCONFIG_SHIFT   6

Shift value for QSPI_DEVRSTCONFIG

Definition at line 145 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 215 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DUALBYTEOPCODEEN_MASK   0x40000000UL

Bit mask for QSPI_DUALBYTEOPCODEEN

Definition at line 214 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_DUALBYTEOPCODEEN_SHIFT   30

Shift value for QSPI_DUALBYTEOPCODEEN

Definition at line 213 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 195 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEAHBDECODER_MASK   0x800000UL

Bit mask for QSPI_ENABLEAHBDECODER

Definition at line 194 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEAHBDECODER_SHIFT   23

Shift value for QSPI_ENABLEAHBDECODER

Definition at line 193 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 200 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_MASK   0x1000000UL

Bit mask for QSPI_ENABLEDTRPROTOCOL

Definition at line 199 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENABLEDTRPROTOCOL_SHIFT   24

Shift value for QSPI_ENABLEDTRPROTOCOL

Definition at line 198 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 176 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBAHBADDRREMAP_MASK   0x10000UL

Bit mask for QSPI_ENBAHBADDRREMAP

Definition at line 175 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBAHBADDRREMAP_SHIFT   16

Shift value for QSPI_ENBAHBADDRREMAP

Definition at line 174 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVHOLD_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 137 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVHOLD_MASK   0x10UL

Bit mask for QSPI_ENBDEVHOLD

Definition at line 136 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVHOLD_SHIFT   4

Shift value for QSPI_ENBDEVHOLD

Definition at line 135 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVRST_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 142 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVRST_MASK   0x20UL

Bit mask for QSPI_ENBDEVRST

Definition at line 141 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDEVRST_SHIFT   5

Shift value for QSPI_ENBDEVRST

Definition at line 140 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 152 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDIRACCCTLR_MASK   0x80UL

Bit mask for QSPI_ENBDIRACCCTLR

Definition at line 151 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBDIRACCCTLR_SHIFT   7

Shift value for QSPI_ENBDIRACCCTLR

Definition at line 150 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 157 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBLEGACYIPMODE_MASK   0x100UL

Bit mask for QSPI_ENBLEGACYIPMODE

Definition at line 156 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBLEGACYIPMODE_SHIFT   8

Shift value for QSPI_ENBLEGACYIPMODE

Definition at line 155 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBSPI_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 117 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBSPI_MASK   0x1UL

Bit mask for QSPI_ENBSPI

Definition at line 116 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENBSPI_SHIFT   0

Shift value for QSPI_ENBSPI

Definition at line 115 of file efm32gg12b_qspi.h.

Referenced by QSPI_Enable().

#define _QSPI_CONFIG_ENTERXIPMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 181 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENTERXIPMODE_MASK   0x20000UL

Bit mask for QSPI_ENTERXIPMODE

Definition at line 180 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENTERXIPMODE_SHIFT   17

Shift value for QSPI_ENTERXIPMODE

Definition at line 179 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 186 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENTERXIPMODEIMM_MASK   0x40000UL

Bit mask for QSPI_ENTERXIPMODEIMM

Definition at line 185 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_ENTERXIPMODEIMM_SHIFT   18

Shift value for QSPI_ENTERXIPMODEIMM

Definition at line 184 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_IDLE_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 220 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_IDLE_MASK   0x80000000UL

Bit mask for QSPI_IDLE

Definition at line 219 of file efm32gg12b_qspi.h.

Referenced by QSPI_WaitForIdle().

#define _QSPI_CONFIG_IDLE_SHIFT   31

Shift value for QSPI_IDLE

Definition at line 218 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_MASK   0xE3FF4FFFUL

Mask for QSPI_CONFIG

Definition at line 113 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_MSTRBAUDDIV_DEFAULT   0x0000000FUL

Mode DEFAULT for QSPI_CONFIG

Definition at line 190 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_MSTRBAUDDIV_MASK   0x780000UL

Bit mask for QSPI_MSTRBAUDDIV

Definition at line 189 of file efm32gg12b_qspi.h.

Referenced by QSPI_Init().

#define _QSPI_CONFIG_MSTRBAUDDIV_SHIFT   19

Shift value for QSPI_MSTRBAUDDIV

Definition at line 188 of file efm32gg12b_qspi.h.

Referenced by QSPI_Init().

#define _QSPI_CONFIG_PERIPHCSLINES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 166 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PERIPHCSLINES_MASK   0xC00UL

Bit mask for QSPI_PERIPHCSLINES

Definition at line 165 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PERIPHCSLINES_SHIFT   10

Shift value for QSPI_PERIPHCSLINES

Definition at line 164 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PERIPHSELDEC_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 162 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PERIPHSELDEC_MASK   0x200UL

Bit mask for QSPI_PERIPHSELDEC

Definition at line 161 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PERIPHSELDEC_SHIFT   9

Shift value for QSPI_PERIPHSELDEC

Definition at line 160 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PHYMODEENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 132 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PHYMODEENABLE_MASK   0x8UL

Bit mask for QSPI_PHYMODEENABLE

Definition at line 131 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PHYMODEENABLE_SHIFT   3

Shift value for QSPI_PHYMODEENABLE

Definition at line 130 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PIPELINEPHY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 205 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PIPELINEPHY_MASK   0x2000000UL

Bit mask for QSPI_PIPELINEPHY

Definition at line 204 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_PIPELINEPHY_SHIFT   25

Shift value for QSPI_PIPELINEPHY

Definition at line 203 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_RESETVALUE   0x80780081UL

Default value for QSPI_CONFIG

Definition at line 112 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPHASE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 127 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPHASE_MASK   0x4UL

Bit mask for QSPI_SELCLKPHASE

Definition at line 126 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPHASE_SHIFT   2

Shift value for QSPI_SELCLKPHASE

Definition at line 125 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPOL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 122 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPOL_MASK   0x2UL

Bit mask for QSPI_SELCLKPOL

Definition at line 121 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_SELCLKPOL_SHIFT   1

Shift value for QSPI_SELCLKPOL

Definition at line 120 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_WRPROTFLASH_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_CONFIG

Definition at line 171 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_WRPROTFLASH_MASK   0x4000UL

Bit mask for QSPI_WRPROTFLASH

Definition at line 170 of file efm32gg12b_qspi.h.

#define _QSPI_CONFIG_WRPROTFLASH_SHIFT   14

Shift value for QSPI_WRPROTFLASH

Definition at line 169 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DAFTER_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVDELAY

Definition at line 291 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DAFTER_MASK   0xFF00UL

Bit mask for QSPI_DAFTER

Definition at line 290 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DAFTER_SHIFT   8

Shift value for QSPI_DAFTER

Definition at line 289 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DBTWN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVDELAY

Definition at line 295 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DBTWN_MASK   0xFF0000UL

Bit mask for QSPI_DBTWN

Definition at line 294 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DBTWN_SHIFT   16

Shift value for QSPI_DBTWN

Definition at line 293 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DINIT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVDELAY

Definition at line 287 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DINIT_MASK   0xFFUL

Bit mask for QSPI_DINIT

Definition at line 286 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DINIT_SHIFT   0

Shift value for QSPI_DINIT

Definition at line 285 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DNSS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVDELAY

Definition at line 299 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DNSS_MASK   0xFF000000UL

Bit mask for QSPI_DNSS

Definition at line 298 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_DNSS_SHIFT   24

Shift value for QSPI_DNSS

Definition at line 297 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_MASK   0xFFFFFFFFUL

Mask for QSPI_DEVDELAY

Definition at line 284 of file efm32gg12b_qspi.h.

#define _QSPI_DEVDELAY_RESETVALUE   0x00000000UL

Default value for QSPI_DEVDELAY

Definition at line 283 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 241 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_MASK   0x3000UL

Bit mask for QSPI_ADDRXFERTYPESTDMODE

Definition at line 240 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_SHIFT   12

Shift value for QSPI_ADDRXFERTYPESTDMODE

Definition at line 239 of file efm32gg12b_qspi.h.

Referenced by QSPI_ReadConfig().

#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 245 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_MASK   0x30000UL

Bit mask for QSPI_DATAXFERTYPEEXTMODE

Definition at line 244 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_SHIFT   16

Shift value for QSPI_DATAXFERTYPEEXTMODE

Definition at line 243 of file efm32gg12b_qspi.h.

Referenced by QSPI_ReadConfig().

#define _QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 237 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DDREN_MASK   0x400UL

Bit mask for QSPI_DDREN

Definition at line 236 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DDREN_SHIFT   10

Shift value for QSPI_DDREN

Definition at line 235 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 254 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_MASK   0x1F000000UL

Bit mask for QSPI_DUMMYRDCLKCYCLES

Definition at line 253 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_SHIFT   24

Shift value for QSPI_DUMMYRDCLKCYCLES

Definition at line 252 of file efm32gg12b_qspi.h.

Referenced by QSPI_ReadConfig().

#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 232 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_MASK   0x300UL

Bit mask for QSPI_INSTRTYPE

Definition at line 231 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_INSTRTYPE_SHIFT   8

Shift value for QSPI_INSTRTYPE

Definition at line 230 of file efm32gg12b_qspi.h.

Referenced by QSPI_ReadConfig().

#define _QSPI_DEVINSTRRDCONFIG_MASK   0x1F1337FFUL

Mask for QSPI_DEVINSTRRDCONFIG

Definition at line 225 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 250 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_MASK   0x100000UL

Bit mask for QSPI_MODEBITENABLE

Definition at line 249 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_SHIFT   20

Shift value for QSPI_MODEBITENABLE

Definition at line 248 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT   0x00000003UL

Mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 228 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_MASK   0xFFUL

Bit mask for QSPI_RDOPCODENONXIP

Definition at line 227 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_SHIFT   0

Shift value for QSPI_RDOPCODENONXIP

Definition at line 226 of file efm32gg12b_qspi.h.

Referenced by QSPI_ReadConfig().

#define _QSPI_DEVINSTRRDCONFIG_RESETVALUE   0x00000003UL

Default value for QSPI_DEVINSTRRDCONFIG

Definition at line 224 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 271 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_MASK   0x3000UL

Bit mask for QSPI_ADDRXFERTYPESTDMODE

Definition at line 270 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_SHIFT   12

Shift value for QSPI_ADDRXFERTYPESTDMODE

Definition at line 269 of file efm32gg12b_qspi.h.

Referenced by QSPI_WriteConfig().

#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 275 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_MASK   0x30000UL

Bit mask for QSPI_DATAXFERTYPEEXTMODE

Definition at line 274 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_SHIFT   16

Shift value for QSPI_DATAXFERTYPEEXTMODE

Definition at line 273 of file efm32gg12b_qspi.h.

Referenced by QSPI_WriteConfig().

#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 279 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_MASK   0x1F000000UL

Bit mask for QSPI_DUMMYWRCLKCYCLES

Definition at line 278 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_SHIFT   24

Shift value for QSPI_DUMMYWRCLKCYCLES

Definition at line 277 of file efm32gg12b_qspi.h.

Referenced by QSPI_WriteConfig().

#define _QSPI_DEVINSTRWRCONFIG_MASK   0x1F0331FFUL

Mask for QSPI_DEVINSTRWRCONFIG

Definition at line 259 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_RESETVALUE   0x00000002UL

Default value for QSPI_DEVINSTRWRCONFIG

Definition at line 258 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 267 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_WELDIS_MASK   0x100UL

Bit mask for QSPI_WELDIS

Definition at line 266 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_WELDIS_SHIFT   8

Shift value for QSPI_WELDIS

Definition at line 265 of file efm32gg12b_qspi.h.

Referenced by QSPI_WriteConfig().

#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT   0x00000002UL

Mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 262 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_MASK   0xFFUL

Bit mask for QSPI_WROPCODE

Definition at line 261 of file efm32gg12b_qspi.h.

#define _QSPI_DEVINSTRWRCONFIG_WROPCODE_SHIFT   0

Shift value for QSPI_WROPCODE

Definition at line 260 of file efm32gg12b_qspi.h.

Referenced by QSPI_WriteConfig().

#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT   0x00000100UL

Mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 333 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_MASK   0xFFF0UL

Bit mask for QSPI_BYTESPERDEVICEPAGE

Definition at line 332 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_SHIFT   4

Shift value for QSPI_BYTESPERDEVICEPAGE

Definition at line 331 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT   0x00000010UL

Mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 337 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_MASK   0x1F0000UL

Bit mask for QSPI_BYTESPERSUBSECTOR

Definition at line 336 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_SHIFT   16

Shift value for QSPI_BYTESPERSUBSECTOR

Definition at line 335 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MASK   0x01FFFFFFUL

Mask for QSPI_DEVSIZECONFIG

Definition at line 326 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 341 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_MASK   0x600000UL

Bit mask for QSPI_MEMSIZEONCS0

Definition at line 340 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS0_SHIFT   21

Shift value for QSPI_MEMSIZEONCS0

Definition at line 339 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 345 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_MASK   0x1800000UL

Bit mask for QSPI_MEMSIZEONCS1

Definition at line 344 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_MEMSIZEONCS1_SHIFT   23

Shift value for QSPI_MEMSIZEONCS1

Definition at line 343 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT   0x00000002UL

Mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 329 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_MASK   0xFUL

Bit mask for QSPI_NUMADDRBYTES

Definition at line 328 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_NUMADDRBYTES_SHIFT   0

Shift value for QSPI_NUMADDRBYTES

Definition at line 327 of file efm32gg12b_qspi.h.

#define _QSPI_DEVSIZECONFIG_RESETVALUE   0x00101002UL

Default value for QSPI_DEVSIZECONFIG

Definition at line 325 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDADDR_ADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDADDR

Definition at line 903 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDADDR_ADDR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_ADDR

Definition at line 902 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDADDR_ADDR_SHIFT   0

Shift value for QSPI_ADDR

Definition at line 901 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDADDR_MASK   0xFFFFFFFFUL

Mask for QSPI_FLASHCMDADDR

Definition at line 900 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDADDR_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHCMDADDR

Definition at line 899 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 845 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXEC_MASK   0x1UL

Bit mask for QSPI_CMDEXEC

Definition at line 844 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXEC_SHIFT   0

Shift value for QSPI_CMDEXEC

Definition at line 843 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 850 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_MASK   0x2UL

Bit mask for QSPI_CMDEXECSTATUS

Definition at line 849 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDEXECSTATUS_SHIFT   1

Shift value for QSPI_CMDEXECSTATUS

Definition at line 848 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 895 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDOPCODE_MASK   0xFF000000UL

Bit mask for QSPI_CMDOPCODE

Definition at line 894 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_CMDOPCODE_SHIFT   24

Shift value for QSPI_CMDOPCODE

Definition at line 893 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 882 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_MASK   0x80000UL

Bit mask for QSPI_ENBCOMDADDR

Definition at line 881 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBCOMDADDR_SHIFT   19

Shift value for QSPI_ENBCOMDADDR

Definition at line 880 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 877 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_MASK   0x40000UL

Bit mask for QSPI_ENBMODEBIT

Definition at line 876 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBMODEBIT_SHIFT   18

Shift value for QSPI_ENBMODEBIT

Definition at line 875 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 891 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBREADDATA_MASK   0x800000UL

Bit mask for QSPI_ENBREADDATA

Definition at line 890 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBREADDATA_SHIFT   23

Shift value for QSPI_ENBREADDATA

Definition at line 889 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 868 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_MASK   0x8000UL

Bit mask for QSPI_ENBWRITEDATA

Definition at line 867 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_ENBWRITEDATA_SHIFT   15

Shift value for QSPI_ENBWRITEDATA

Definition at line 866 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_MASK   0xFFFFFF87UL

Mask for QSPI_FLASHCMDCTRL

Definition at line 841 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 872 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_MASK   0x30000UL

Bit mask for QSPI_NUMADDRBYTES

Definition at line 871 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMADDRBYTES_SHIFT   16

Shift value for QSPI_NUMADDRBYTES

Definition at line 870 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 859 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_MASK   0xF80UL

Bit mask for QSPI_NUMDUMMYCYCLES

Definition at line 858 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_SHIFT   7

Shift value for QSPI_NUMDUMMYCYCLES

Definition at line 857 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 886 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_MASK   0x700000UL

Bit mask for QSPI_NUMRDDATABYTES

Definition at line 885 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMRDDATABYTES_SHIFT   20

Shift value for QSPI_NUMRDDATABYTES

Definition at line 884 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 863 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_MASK   0x7000UL

Bit mask for QSPI_NUMWRDATABYTES

Definition at line 862 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_NUMWRDATABYTES_SHIFT   12

Shift value for QSPI_NUMWRDATABYTES

Definition at line 861 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define _QSPI_FLASHCMDCTRL_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHCMDCTRL

Definition at line 840 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 855 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_MASK   0x4UL

Bit mask for QSPI_STIGMEMBANKEN

Definition at line 854 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCMDCTRL_STIGMEMBANKEN_SHIFT   2

Shift value for QSPI_STIGMEMBANKEN

Definition at line 853 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MASK   0x1FF7FF03UL

Mask for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 815 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 836 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_MASK   0x1FF00000UL

Bit mask for QSPI_MEMBANKADDR

Definition at line 835 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_SHIFT   20

Shift value for QSPI_MEMBANKADDR

Definition at line 834 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 828 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_MASK   0xFF00UL

Bit mask for QSPI_MEMBANKREADDATA

Definition at line 827 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_SHIFT   8

Shift value for QSPI_MEMBANKREADDATA

Definition at line 826 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 824 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_MASK   0x2UL

Bit mask for QSPI_MEMBANKREQINPROGRESS

Definition at line 823 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_SHIFT   1

Shift value for QSPI_MEMBANKREQINPROGRESS

Definition at line 822 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 832 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_MASK   0x70000UL

Bit mask for QSPI_NBOFSTIGREADBYTES

Definition at line 831 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_SHIFT   16

Shift value for QSPI_NBOFSTIGREADBYTES

Definition at line 830 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 814 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 819 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_MASK   0x1UL

Bit mask for QSPI_TRIGGERMEMBANKREQ

Definition at line 818 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_SHIFT   0

Shift value for QSPI_TRIGGERMEMBANKREQ

Definition at line 817 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATALOWER_DATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHRDDATALOWER

Definition at line 911 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATALOWER_DATA_MASK   0xFFFFFFFFUL

Bit mask for QSPI_DATA

Definition at line 910 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATALOWER_DATA_SHIFT   0

Shift value for QSPI_DATA

Definition at line 909 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATALOWER_MASK   0xFFFFFFFFUL

Mask for QSPI_FLASHRDDATALOWER

Definition at line 908 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATALOWER_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHRDDATALOWER

Definition at line 907 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATAUPPER_DATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHRDDATAUPPER

Definition at line 919 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATAUPPER_DATA_MASK   0xFFFFFFFFUL

Bit mask for QSPI_DATA

Definition at line 918 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATAUPPER_DATA_SHIFT   0

Shift value for QSPI_DATA

Definition at line 917 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATAUPPER_MASK   0xFFFFFFFFUL

Mask for QSPI_FLASHRDDATAUPPER

Definition at line 916 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHRDDATAUPPER_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHRDDATAUPPER

Definition at line 915 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATALOWER_DATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHWRDATALOWER

Definition at line 927 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATALOWER_DATA_MASK   0xFFFFFFFFUL

Bit mask for QSPI_DATA

Definition at line 926 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATALOWER_DATA_SHIFT   0

Shift value for QSPI_DATA

Definition at line 925 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATALOWER_MASK   0xFFFFFFFFUL

Mask for QSPI_FLASHWRDATALOWER

Definition at line 924 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATALOWER_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHWRDATALOWER

Definition at line 923 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATAUPPER_DATA_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_FLASHWRDATAUPPER

Definition at line 935 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATAUPPER_DATA_MASK   0xFFFFFFFFUL

Bit mask for QSPI_DATA

Definition at line 934 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATAUPPER_DATA_SHIFT   0

Shift value for QSPI_DATA

Definition at line 933 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATAUPPER_MASK   0xFFFFFFFFUL

Mask for QSPI_FLASHWRDATAUPPER

Definition at line 932 of file efm32gg12b_qspi.h.

#define _QSPI_FLASHWRDATAUPPER_RESETVALUE   0x00000000UL

Default value for QSPI_FLASHWRDATAUPPER

Definition at line 931 of file efm32gg12b_qspi.h.

#define _QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDAHBADDRTRIGGER

Definition at line 361 of file efm32gg12b_qspi.h.

#define _QSPI_INDAHBADDRTRIGGER_ADDR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_ADDR

Definition at line 360 of file efm32gg12b_qspi.h.

#define _QSPI_INDAHBADDRTRIGGER_ADDR_SHIFT   0

Shift value for QSPI_ADDR

Definition at line 359 of file efm32gg12b_qspi.h.

#define _QSPI_INDAHBADDRTRIGGER_MASK   0xFFFFFFFFUL

Mask for QSPI_INDAHBADDRTRIGGER

Definition at line 358 of file efm32gg12b_qspi.h.

#define _QSPI_INDAHBADDRTRIGGER_RESETVALUE   0x00000000UL

Default value for QSPI_INDAHBADDRTRIGGER

Definition at line 357 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 697 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_MASK   0x2UL

Bit mask for QSPI_CANCEL

Definition at line 696 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_CANCEL_SHIFT   1

Shift value for QSPI_CANCEL

Definition at line 695 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 717 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_MASK   0x20UL

Bit mask for QSPI_INDOPSDONESTATUS

Definition at line 716 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_SHIFT   5

Shift value for QSPI_INDOPSDONESTATUS

Definition at line 715 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_MASK   0x000000FFUL

Mask for QSPI_INDIRECTREADXFERCTRL

Definition at line 688 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 721 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_MASK   0xC0UL

Bit mask for QSPI_NUMINDOPSDONE

Definition at line 720 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_SHIFT   6

Shift value for QSPI_NUMINDOPSDONE

Definition at line 719 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 712 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_MASK   0x10UL

Bit mask for QSPI_RDQUEUED

Definition at line 711 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDQUEUED_SHIFT   4

Shift value for QSPI_RDQUEUED

Definition at line 710 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 702 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_MASK   0x4UL

Bit mask for QSPI_RDSTATUS

Definition at line 701 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RDSTATUS_SHIFT   2

Shift value for QSPI_RDSTATUS

Definition at line 700 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTREADXFERCTRL

Definition at line 687 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 707 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_MASK   0x8UL

Bit mask for QSPI_SRAMFULL

Definition at line 706 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_SRAMFULL_SHIFT   3

Shift value for QSPI_SRAMFULL

Definition at line 705 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_START_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 692 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_START_MASK   0x1UL

Bit mask for QSPI_START

Definition at line 691 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERCTRL_START_SHIFT   0

Shift value for QSPI_START

Definition at line 690 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERNUMBYTES_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTREADXFERNUMBYTES

Definition at line 742 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERNUMBYTES_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTREADXFERNUMBYTES

Definition at line 741 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES

Definition at line 745 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_MASK   0xFFFFFFFFUL

Bit mask for QSPI_VALUE

Definition at line 744 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERNUMBYTES_VALUE_SHIFT   0

Shift value for QSPI_VALUE

Definition at line 743 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERSTART

Definition at line 737 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERSTART_ADDR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_ADDR

Definition at line 736 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERSTART_ADDR_SHIFT   0

Shift value for QSPI_ADDR

Definition at line 735 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERSTART_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTREADXFERSTART

Definition at line 734 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERSTART_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTREADXFERSTART

Definition at line 733 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK

Definition at line 729 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_MASK   0xFFFFFFFFUL

Bit mask for QSPI_LEVEL

Definition at line 728 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERWATERMARK_LEVEL_SHIFT   0

Shift value for QSPI_LEVEL

Definition at line 727 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERWATERMARK_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTREADXFERWATERMARK

Definition at line 726 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTREADXFERWATERMARK_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTREADXFERWATERMARK

Definition at line 725 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT   0x00000004UL

Mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE

Definition at line 810 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_MASK   0xFUL

Bit mask for QSPI_INDRANGEWIDTH

Definition at line 809 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_SHIFT   0

Shift value for QSPI_INDRANGEWIDTH

Definition at line 808 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTTRIGGERADDRRANGE_MASK   0x0000000FUL

Mask for QSPI_INDIRECTTRIGGERADDRRANGE

Definition at line 807 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTTRIGGERADDRRANGE_RESETVALUE   0x00000004UL

Default value for QSPI_INDIRECTTRIGGERADDRRANGE

Definition at line 806 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 759 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_MASK   0x2UL

Bit mask for QSPI_CANCEL

Definition at line 758 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_CANCEL_SHIFT   1

Shift value for QSPI_CANCEL

Definition at line 757 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 774 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_MASK   0x20UL

Bit mask for QSPI_INDOPSDONESTATUS

Definition at line 773 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_SHIFT   5

Shift value for QSPI_INDOPSDONESTATUS

Definition at line 772 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_MASK   0x000000F7UL

Mask for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 750 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 778 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_MASK   0xC0UL

Bit mask for QSPI_NUMINDOPSDONE

Definition at line 777 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_SHIFT   6

Shift value for QSPI_NUMINDOPSDONE

Definition at line 776 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 749 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 754 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_START_MASK   0x1UL

Bit mask for QSPI_START

Definition at line 753 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_START_SHIFT   0

Shift value for QSPI_START

Definition at line 752 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 769 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_MASK   0x10UL

Bit mask for QSPI_WRQUEUED

Definition at line 768 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_SHIFT   4

Shift value for QSPI_WRQUEUED

Definition at line 767 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 764 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_MASK   0x4UL

Bit mask for QSPI_WRSTATUS

Definition at line 763 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_SHIFT   2

Shift value for QSPI_WRSTATUS

Definition at line 762 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERNUMBYTES_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTWRITEXFERNUMBYTES

Definition at line 799 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERNUMBYTES_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTWRITEXFERNUMBYTES

Definition at line 798 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES

Definition at line 802 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_MASK   0xFFFFFFFFUL

Bit mask for QSPI_VALUE

Definition at line 801 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_SHIFT   0

Shift value for QSPI_VALUE

Definition at line 800 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART

Definition at line 794 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_ADDR

Definition at line 793 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERSTART_ADDR_SHIFT   0

Shift value for QSPI_ADDR

Definition at line 792 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERSTART_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTWRITEXFERSTART

Definition at line 791 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERSTART_RESETVALUE   0x00000000UL

Default value for QSPI_INDIRECTWRITEXFERSTART

Definition at line 790 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT   0xFFFFFFFFUL

Mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK

Definition at line 786 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_MASK   0xFFFFFFFFUL

Bit mask for QSPI_LEVEL

Definition at line 785 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_SHIFT   0

Shift value for QSPI_LEVEL

Definition at line 784 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERWATERMARK_MASK   0xFFFFFFFFUL

Mask for QSPI_INDIRECTWRITEXFERWATERMARK

Definition at line 783 of file efm32gg12b_qspi.h.

#define _QSPI_INDIRECTWRITEXFERWATERMARK_RESETVALUE   0xFFFFFFFFUL

Default value for QSPI_INDIRECTWRITEXFERWATERMARK

Definition at line 782 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 593 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_MASK   0x20UL

Bit mask for QSPI_ILLEGALACCESSDETMASK

Definition at line 592 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_ILLEGALACCESSDETMASK_SHIFT   5

Shift value for QSPI_ILLEGALACCESSDETMASK

Definition at line 591 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 578 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_MASK   0x4UL

Bit mask for QSPI_INDIRECTOPDONEMASK

Definition at line 577 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTOPDONEMASK_SHIFT   2

Shift value for QSPI_INDIRECTOPDONEMASK

Definition at line 576 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 583 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_MASK   0x8UL

Bit mask for QSPI_INDIRECTREADREJECTMASK

Definition at line 582 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTREADREJECTMASK_SHIFT   3

Shift value for QSPI_INDIRECTREADREJECTMASK

Definition at line 581 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 598 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_MASK   0x40UL

Bit mask for QSPI_INDIRECTXFERLEVELBREACHMASK

Definition at line 597 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_SHIFT   6

Shift value for QSPI_INDIRECTXFERLEVELBREACHMASK

Definition at line 596 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 628 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_MASK   0x1000UL

Bit mask for QSPI_INDRDSRAMFULLMASK

Definition at line 627 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_INDRDSRAMFULLMASK_SHIFT   12

Shift value for QSPI_INDRDSRAMFULLMASK

Definition at line 626 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_MASK   0x00077FFFUL

Mask for QSPI_IRQMASK

Definition at line 564 of file efm32gg12b_qspi.h.

Referenced by QSPI_IntDisable(), and QSPI_IntEnable().

#define _QSPI_IRQMASK_MODEMFAILMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 568 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_MODEMFAILMASK_MASK   0x1UL

Bit mask for QSPI_MODEMFAILMASK

Definition at line 567 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_MODEMFAILMASK_SHIFT   0

Shift value for QSPI_MODEMFAILMASK

Definition at line 566 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 633 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_POLLEXPINTMASK_MASK   0x2000UL

Bit mask for QSPI_POLLEXPINTMASK

Definition at line 632 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_POLLEXPINTMASK_SHIFT   13

Shift value for QSPI_POLLEXPINTMASK

Definition at line 631 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 588 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_MASK   0x10UL

Bit mask for QSPI_PROTWRATTEMPTMASK

Definition at line 587 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_PROTWRATTEMPTMASK_SHIFT   4

Shift value for QSPI_PROTWRATTEMPTMASK

Definition at line 586 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 603 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RECVOVERFLOWMASK_MASK   0x80UL

Bit mask for QSPI_RECVOVERFLOWMASK

Definition at line 602 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RECVOVERFLOWMASK_SHIFT   7

Shift value for QSPI_RECVOVERFLOWMASK

Definition at line 601 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RESETVALUE   0x00000000UL

Default value for QSPI_IRQMASK

Definition at line 563 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 643 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAERRMASK_MASK   0x10000UL

Bit mask for QSPI_RXCRCDATAERRMASK

Definition at line 642 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAERRMASK_SHIFT   16

Shift value for QSPI_RXCRCDATAERRMASK

Definition at line 641 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 648 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAVALMASK_MASK   0x20000UL

Bit mask for QSPI_RXCRCDATAVALMASK

Definition at line 647 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXCRCDATAVALMASK_SHIFT   17

Shift value for QSPI_RXCRCDATAVALMASK

Definition at line 646 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 623 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFOFULLMASK_MASK   0x800UL

Bit mask for QSPI_RXFIFOFULLMASK

Definition at line 622 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFOFULLMASK_SHIFT   11

Shift value for QSPI_RXFIFOFULLMASK

Definition at line 621 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 618 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_MASK   0x400UL

Bit mask for QSPI_RXFIFONOTEMPTYMASK

Definition at line 617 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_RXFIFONOTEMPTYMASK_SHIFT   10

Shift value for QSPI_RXFIFONOTEMPTYMASK

Definition at line 616 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_STIGREQMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 638 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_STIGREQMASK_MASK   0x4000UL

Bit mask for QSPI_STIGREQMASK

Definition at line 637 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_STIGREQMASK_SHIFT   14

Shift value for QSPI_STIGREQMASK

Definition at line 636 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 653 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_MASK   0x40000UL

Bit mask for QSPI_TXCRCCHUNKBRKMASK

Definition at line 652 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXCRCCHUNKBRKMASK_SHIFT   18

Shift value for QSPI_TXCRCCHUNKBRKMASK

Definition at line 651 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 613 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFOFULLMASK_MASK   0x200UL

Bit mask for QSPI_TXFIFOFULLMASK

Definition at line 612 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFOFULLMASK_SHIFT   9

Shift value for QSPI_TXFIFOFULLMASK

Definition at line 611 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 608 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_MASK   0x100UL

Bit mask for QSPI_TXFIFONOTFULLMASK

Definition at line 607 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_TXFIFONOTFULLMASK_SHIFT   8

Shift value for QSPI_TXFIFONOTFULLMASK

Definition at line 606 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQMASK

Definition at line 573 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_UNDERFLOWDETMASK_MASK   0x2UL

Bit mask for QSPI_UNDERFLOWDETMASK

Definition at line 572 of file efm32gg12b_qspi.h.

#define _QSPI_IRQMASK_UNDERFLOWDETMASK_SHIFT   1

Shift value for QSPI_UNDERFLOWDETMASK

Definition at line 571 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 499 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_MASK   0x20UL

Bit mask for QSPI_ILLEGALACCESSDET

Definition at line 498 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_ILLEGALACCESSDET_SHIFT   5

Shift value for QSPI_ILLEGALACCESSDET

Definition at line 497 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 484 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTOPDONE_MASK   0x4UL

Bit mask for QSPI_INDIRECTOPDONE

Definition at line 483 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTOPDONE_SHIFT   2

Shift value for QSPI_INDIRECTOPDONE

Definition at line 482 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 489 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_MASK   0x8UL

Bit mask for QSPI_INDIRECTREADREJECT

Definition at line 488 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTREADREJECT_SHIFT   3

Shift value for QSPI_INDIRECTREADREJECT

Definition at line 487 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 504 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_MASK   0x40UL

Bit mask for QSPI_INDIRECTXFERLEVELBREACH

Definition at line 503 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_SHIFT   6

Shift value for QSPI_INDIRECTXFERLEVELBREACH

Definition at line 502 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 534 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDRDSRAMFULL_MASK   0x1000UL

Bit mask for QSPI_INDRDSRAMFULL

Definition at line 533 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_INDRDSRAMFULL_SHIFT   12

Shift value for QSPI_INDRDSRAMFULL

Definition at line 532 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_MASK   0x00077FFFUL

Mask for QSPI_IRQSTATUS

Definition at line 470 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_MODEMFAIL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 474 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_MODEMFAIL_MASK   0x1UL

Bit mask for QSPI_MODEMFAIL

Definition at line 473 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_MODEMFAIL_SHIFT   0

Shift value for QSPI_MODEMFAIL

Definition at line 472 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_POLLEXPINT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 539 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_POLLEXPINT_MASK   0x2000UL

Bit mask for QSPI_POLLEXPINT

Definition at line 538 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_POLLEXPINT_SHIFT   13

Shift value for QSPI_POLLEXPINT

Definition at line 537 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 494 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_PROTWRATTEMPT_MASK   0x10UL

Bit mask for QSPI_PROTWRATTEMPT

Definition at line 493 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_PROTWRATTEMPT_SHIFT   4

Shift value for QSPI_PROTWRATTEMPT

Definition at line 492 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 509 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RECVOVERFLOW_MASK   0x80UL

Bit mask for QSPI_RECVOVERFLOW

Definition at line 508 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RECVOVERFLOW_SHIFT   7

Shift value for QSPI_RECVOVERFLOW

Definition at line 507 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RESETVALUE   0x00000000UL

Default value for QSPI_IRQSTATUS

Definition at line 469 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 549 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAERR_MASK   0x10000UL

Bit mask for QSPI_RXCRCDATAERR

Definition at line 548 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAERR_SHIFT   16

Shift value for QSPI_RXCRCDATAERR

Definition at line 547 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 554 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAVAL_MASK   0x20000UL

Bit mask for QSPI_RXCRCDATAVAL

Definition at line 553 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXCRCDATAVAL_SHIFT   17

Shift value for QSPI_RXCRCDATAVAL

Definition at line 552 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 529 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFOFULL_MASK   0x800UL

Bit mask for QSPI_RXFIFOFULL

Definition at line 528 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFOFULL_SHIFT   11

Shift value for QSPI_RXFIFOFULL

Definition at line 527 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 524 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_MASK   0x400UL

Bit mask for QSPI_RXFIFONOTEMPTY

Definition at line 523 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_RXFIFONOTEMPTY_SHIFT   10

Shift value for QSPI_RXFIFONOTEMPTY

Definition at line 522 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_STIGREQINT_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 544 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_STIGREQINT_MASK   0x4000UL

Bit mask for QSPI_STIGREQINT

Definition at line 543 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_STIGREQINT_SHIFT   14

Shift value for QSPI_STIGREQINT

Definition at line 542 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 559 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_MASK   0x40000UL

Bit mask for QSPI_TXCRCCHUNKBRK

Definition at line 558 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXCRCCHUNKBRK_SHIFT   18

Shift value for QSPI_TXCRCCHUNKBRK

Definition at line 557 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 519 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFOFULL_MASK   0x200UL

Bit mask for QSPI_TXFIFOFULL

Definition at line 518 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFOFULL_SHIFT   9

Shift value for QSPI_TXFIFOFULL

Definition at line 517 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 514 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFONOTFULL_MASK   0x100UL

Bit mask for QSPI_TXFIFONOTFULL

Definition at line 513 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_TXFIFONOTFULL_SHIFT   8

Shift value for QSPI_TXFIFONOTFULL

Definition at line 512 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_IRQSTATUS

Definition at line 479 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_UNDERFLOWDET_MASK   0x2UL

Bit mask for QSPI_UNDERFLOWDET

Definition at line 478 of file efm32gg12b_qspi.h.

#define _QSPI_IRQSTATUS_UNDERFLOWDET_SHIFT   1

Shift value for QSPI_UNDERFLOWDET

Definition at line 477 of file efm32gg12b_qspi.h.

#define _QSPI_LOWERWRPROT_MASK   0xFFFFFFFFUL

Mask for QSPI_LOWERWRPROT

Definition at line 658 of file efm32gg12b_qspi.h.

#define _QSPI_LOWERWRPROT_RESETVALUE   0x00000000UL

Default value for QSPI_LOWERWRPROT

Definition at line 657 of file efm32gg12b_qspi.h.

#define _QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_LOWERWRPROT

Definition at line 661 of file efm32gg12b_qspi.h.

#define _QSPI_LOWERWRPROT_SUBSECTOR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_SUBSECTOR

Definition at line 660 of file efm32gg12b_qspi.h.

#define _QSPI_LOWERWRPROT_SUBSECTOR_SHIFT   0

Shift value for QSPI_SUBSECTOR

Definition at line 659 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT   0x00000002UL

Mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 381 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CHUNKSIZE_MASK   0x700UL

Bit mask for QSPI_CHUNKSIZE

Definition at line 380 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CHUNKSIZE_SHIFT   8

Shift value for QSPI_CHUNKSIZE

Definition at line 379 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 386 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_MASK   0x8000UL

Bit mask for QSPI_CRCOUTENABLE

Definition at line 385 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_CRCOUTENABLE_SHIFT   15

Shift value for QSPI_CRCOUTENABLE

Definition at line 384 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_MASK   0xFFFF87FFUL

Mask for QSPI_MODEBITCONFIG

Definition at line 374 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_MODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 377 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_MODE_MASK   0xFFUL

Bit mask for QSPI_MODE

Definition at line 376 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_MODE_SHIFT   0

Shift value for QSPI_MODE

Definition at line 375 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RESETVALUE   0x00000200UL

Default value for QSPI_MODEBITCONFIG

Definition at line 373 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 394 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_MASK   0xFF000000UL

Bit mask for QSPI_RXCRCDATALOW

Definition at line 393 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATALOW_SHIFT   24

Shift value for QSPI_RXCRCDATALOW

Definition at line 392 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 390 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_MASK   0xFF0000UL

Bit mask for QSPI_RXCRCDATAUP

Definition at line 389 of file efm32gg12b_qspi.h.

#define _QSPI_MODEBITCONFIG_RXCRCDATAUP_SHIFT   16

Shift value for QSPI_RXCRCDATAUP

Definition at line 388 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_CONF_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_MODULEID

Definition at line 1009 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_CONF_MASK   0x3UL

Bit mask for QSPI_CONF

Definition at line 1008 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_CONF_SHIFT   0

Shift value for QSPI_CONF

Definition at line 1007 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_FIXPATCH_DEFAULT   0x00000004UL

Mode DEFAULT for QSPI_MODULEID

Definition at line 1017 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_FIXPATCH_MASK   0xFF000000UL

Bit mask for QSPI_FIXPATCH

Definition at line 1016 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_FIXPATCH_SHIFT   24

Shift value for QSPI_FIXPATCH

Definition at line 1015 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_MASK   0xFFFFFF03UL

Mask for QSPI_MODULEID

Definition at line 1006 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_MODULEID_DEFAULT   0x00000003UL

Mode DEFAULT for QSPI_MODULEID

Definition at line 1013 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_MODULEID_MASK   0xFFFF00UL

Bit mask for QSPI_MODULEID

Definition at line 1012 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_MODULEID_SHIFT   8

Shift value for QSPI_MODULEID

Definition at line 1011 of file efm32gg12b_qspi.h.

#define _QSPI_MODULEID_RESETVALUE   0x04000300UL

Default value for QSPI_MODULEID

Definition at line 1005 of file efm32gg12b_qspi.h.

#define _QSPI_NOOFPOLLSBEFEXP_MASK   0xFFFFFFFFUL

Mask for QSPI_NOOFPOLLSBEFEXP

Definition at line 462 of file efm32gg12b_qspi.h.

#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT   0xFFFFFFFFUL

Mode DEFAULT for QSPI_NOOFPOLLSBEFEXP

Definition at line 465 of file efm32gg12b_qspi.h.

#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_MASK   0xFFFFFFFFUL

Bit mask for QSPI_NOOFPOLLSBEFEXP

Definition at line 464 of file efm32gg12b_qspi.h.

#define _QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_SHIFT   0

Shift value for QSPI_NOOFPOLLSBEFEXP

Definition at line 463 of file efm32gg12b_qspi.h.

#define _QSPI_NOOFPOLLSBEFEXP_RESETVALUE   0xFFFFFFFFUL

Default value for QSPI_NOOFPOLLSBEFEXP

Definition at line 461 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT   0x000000FAUL

Mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 981 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_MASK   0xFF00UL

Bit mask for QSPI_EXTPOLLOPCODE

Definition at line 980 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_SHIFT   8

Shift value for QSPI_EXTPOLLOPCODE

Definition at line 979 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT   0x00000013UL

Mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 989 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_MASK   0xFF000000UL

Bit mask for QSPI_EXTREADOPCODE

Definition at line 988 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTREADOPCODE_SHIFT   24

Shift value for QSPI_EXTREADOPCODE

Definition at line 987 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 977 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_MASK   0xFFUL

Bit mask for QSPI_EXTSTIGOPCODE

Definition at line 976 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_SHIFT   0

Shift value for QSPI_EXTSTIGOPCODE

Definition at line 975 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT   0x000000EDUL

Mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 985 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_MASK   0xFF0000UL

Bit mask for QSPI_EXTWRITEOPCODE

Definition at line 984 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_SHIFT   16

Shift value for QSPI_EXTWRITEOPCODE

Definition at line 983 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_MASK   0xFFFFFFFFUL

Mask for QSPI_OPCODEEXTLOWER

Definition at line 974 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTLOWER_RESETVALUE   0x13EDFA00UL

Default value for QSPI_OPCODEEXTLOWER

Definition at line 973 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT   0x000000F9UL

Mode DEFAULT for QSPI_OPCODEEXTUPPER

Definition at line 997 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_MASK   0xFF0000UL

Bit mask for QSPI_EXTWELOPCODE

Definition at line 996 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_EXTWELOPCODE_SHIFT   16

Shift value for QSPI_EXTWELOPCODE

Definition at line 995 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_MASK   0xFFFF0000UL

Mask for QSPI_OPCODEEXTUPPER

Definition at line 994 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_RESETVALUE   0x06F90000UL

Default value for QSPI_OPCODEEXTUPPER

Definition at line 993 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT   0x00000006UL

Mode DEFAULT for QSPI_OPCODEEXTUPPER

Definition at line 1001 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_WELOPCODE_MASK   0xFF000000UL

Bit mask for QSPI_WELOPCODE

Definition at line 1000 of file efm32gg12b_qspi.h.

#define _QSPI_OPCODEEXTUPPER_WELOPCODE_SHIFT   24

Shift value for QSPI_WELOPCODE

Definition at line 999 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_MASK   0x807F007FUL

Mask for QSPI_PHYCONFIGURATION

Definition at line 957 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 969 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_MASK   0x80000000UL

Bit mask for QSPI_PHYCONFIGRESYNC

Definition at line 968 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_SHIFT   31

Shift value for QSPI_PHYCONFIGRESYNC

Definition at line 967 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 960 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_MASK   0x7FUL

Bit mask for QSPI_PHYCONFIGRXDLLDELAY

Definition at line 959 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_SHIFT   0

Shift value for QSPI_PHYCONFIGRXDLLDELAY

Definition at line 958 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 964 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_MASK   0x7F0000UL

Bit mask for QSPI_PHYCONFIGTXDLLDELAY

Definition at line 963 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_SHIFT   16

Shift value for QSPI_PHYCONFIGTXDLLDELAY

Definition at line 962 of file efm32gg12b_qspi.h.

#define _QSPI_PHYCONFIGURATION_RESETVALUE   0x00000000UL

Default value for QSPI_PHYCONFIGURATION

Definition at line 956 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 943 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_MASK   0xFFUL

Bit mask for QSPI_DEVICESTATUS

Definition at line 942 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_SHIFT   0

Shift value for QSPI_DEVICESTATUS

Definition at line 941 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 952 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_MASK   0xF0000UL

Bit mask for QSPI_DEVICESTATUSNBDUMMY

Definition at line 951 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_SHIFT   16

Shift value for QSPI_DEVICESTATUSNBDUMMY

Definition at line 950 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 948 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_MASK   0x100UL

Bit mask for QSPI_DEVICESTATUSVALID

Definition at line 947 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_SHIFT   8

Shift value for QSPI_DEVICESTATUSVALID

Definition at line 946 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_MASK   0x000F01FFUL

Mask for QSPI_POLLINGFLASHSTATUS

Definition at line 940 of file efm32gg12b_qspi.h.

#define _QSPI_POLLINGFLASHSTATUS_RESETVALUE   0x00000000UL

Default value for QSPI_POLLINGFLASHSTATUS

Definition at line 939 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_BYPASS_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 308 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_BYPASS_MASK   0x1UL

Bit mask for QSPI_BYPASS

Definition at line 307 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_BYPASS_SHIFT   0

Shift value for QSPI_BYPASS

Definition at line 306 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 321 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DDRREADDELAY_MASK   0xF0000UL

Bit mask for QSPI_DDRREADDELAY

Definition at line 320 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DDRREADDELAY_SHIFT   16

Shift value for QSPI_DDRREADDELAY

Definition at line 319 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DELAY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 312 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DELAY_MASK   0x1EUL

Bit mask for QSPI_DELAY

Definition at line 311 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DELAY_SHIFT   1

Shift value for QSPI_DELAY

Definition at line 310 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 317 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DQSENABLE_MASK   0x100UL

Bit mask for QSPI_DQSENABLE

Definition at line 316 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_DQSENABLE_SHIFT   8

Shift value for QSPI_DQSENABLE

Definition at line 315 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_MASK   0x000F011FUL

Mask for QSPI_RDDATACAPTURE

Definition at line 304 of file efm32gg12b_qspi.h.

#define _QSPI_RDDATACAPTURE_RESETVALUE   0x00000001UL

Default value for QSPI_RDDATACAPTURE

Definition at line 303 of file efm32gg12b_qspi.h.

#define _QSPI_REMAPADDR_MASK   0xFFFFFFFFUL

Mask for QSPI_REMAPADDR

Definition at line 366 of file efm32gg12b_qspi.h.

#define _QSPI_REMAPADDR_RESETVALUE   0x00000000UL

Default value for QSPI_REMAPADDR

Definition at line 365 of file efm32gg12b_qspi.h.

#define _QSPI_REMAPADDR_VALUE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_REMAPADDR

Definition at line 369 of file efm32gg12b_qspi.h.

#define _QSPI_REMAPADDR_VALUE_MASK   0xFFFFFFFFUL

Bit mask for QSPI_VALUE

Definition at line 368 of file efm32gg12b_qspi.h.

#define _QSPI_REMAPADDR_VALUE_SHIFT   0

Shift value for QSPI_VALUE

Definition at line 367 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_MASK   0x00000041UL

Mask for QSPI_ROUTELOC0

Definition at line 1101 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPILOC_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTELOC0

Definition at line 1105 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPILOC_LOC0   0x00000000UL

Mode LOC0 for QSPI_ROUTELOC0

Definition at line 1104 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPILOC_LOC1   0x00000001UL

Mode LOC1 for QSPI_ROUTELOC0

Definition at line 1106 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPILOC_MASK   0x1UL

Bit mask for QSPI_QSPILOC

Definition at line 1103 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPILOC_SHIFT   0

Shift value for QSPI_QSPILOC

Definition at line 1102 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTELOC0

Definition at line 1113 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPIRSTLOC_LOC0   0x00000000UL

Mode LOC0 for QSPI_ROUTELOC0

Definition at line 1112 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPIRSTLOC_LOC1   0x00000001UL

Mode LOC1 for QSPI_ROUTELOC0

Definition at line 1114 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPIRSTLOC_MASK   0x40UL

Bit mask for QSPI_QSPIRSTLOC

Definition at line 1111 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_QSPIRSTLOC_SHIFT   6

Shift value for QSPI_QSPIRSTLOC

Definition at line 1110 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTELOC0_RESETVALUE   0x00000000UL

Default value for QSPI_ROUTELOC0

Definition at line 1100 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS0PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1031 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS0PEN_MASK   0x2UL

Bit mask for QSPI_CS0PEN

Definition at line 1030 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS0PEN_SHIFT   1

Shift value for QSPI_CS0PEN

Definition at line 1029 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS1PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1036 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS1PEN_MASK   0x4UL

Bit mask for QSPI_CS1PEN

Definition at line 1035 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_CS1PEN_SHIFT   2

Shift value for QSPI_CS1PEN

Definition at line 1034 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ0PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1041 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ0PEN_MASK   0x20UL

Bit mask for QSPI_DQ0PEN

Definition at line 1040 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ0PEN_SHIFT   5

Shift value for QSPI_DQ0PEN

Definition at line 1039 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ1PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1046 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ1PEN_MASK   0x40UL

Bit mask for QSPI_DQ1PEN

Definition at line 1045 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ1PEN_SHIFT   6

Shift value for QSPI_DQ1PEN

Definition at line 1044 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ2PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1051 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ2PEN_MASK   0x80UL

Bit mask for QSPI_DQ2PEN

Definition at line 1050 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ2PEN_SHIFT   7

Shift value for QSPI_DQ2PEN

Definition at line 1049 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ3PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1056 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ3PEN_MASK   0x100UL

Bit mask for QSPI_DQ3PEN

Definition at line 1055 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ3PEN_SHIFT   8

Shift value for QSPI_DQ3PEN

Definition at line 1054 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ4PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1061 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ4PEN_MASK   0x200UL

Bit mask for QSPI_DQ4PEN

Definition at line 1060 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ4PEN_SHIFT   9

Shift value for QSPI_DQ4PEN

Definition at line 1059 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ5PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1066 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ5PEN_MASK   0x400UL

Bit mask for QSPI_DQ5PEN

Definition at line 1065 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ5PEN_SHIFT   10

Shift value for QSPI_DQ5PEN

Definition at line 1064 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ6PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1071 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ6PEN_MASK   0x800UL

Bit mask for QSPI_DQ6PEN

Definition at line 1070 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ6PEN_SHIFT   11

Shift value for QSPI_DQ6PEN

Definition at line 1069 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ7PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1076 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ7PEN_MASK   0x1000UL

Bit mask for QSPI_DQ7PEN

Definition at line 1075 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQ7PEN_SHIFT   12

Shift value for QSPI_DQ7PEN

Definition at line 1074 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQSPEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1081 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQSPEN_MASK   0x2000UL

Bit mask for QSPI_DQSPEN

Definition at line 1080 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_DQSPEN_SHIFT   13

Shift value for QSPI_DQSPEN

Definition at line 1079 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_MASK   0x00037FE7UL

Mask for QSPI_ROUTEPEN

Definition at line 1022 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RESETVALUE   0x00000000UL

Default value for QSPI_ROUTEPEN

Definition at line 1021 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST0PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1091 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST0PEN_MASK   0x10000UL

Bit mask for QSPI_RST0PEN

Definition at line 1090 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST0PEN_SHIFT   16

Shift value for QSPI_RST0PEN

Definition at line 1089 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST1PEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1096 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST1PEN_MASK   0x20000UL

Bit mask for QSPI_RST1PEN

Definition at line 1095 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_RST1PEN_SHIFT   17

Shift value for QSPI_RST1PEN

Definition at line 1094 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKINPEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1086 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKINPEN_MASK   0x4000UL

Bit mask for QSPI_SCLKINPEN

Definition at line 1085 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKINPEN_SHIFT   14

Shift value for QSPI_SCLKINPEN

Definition at line 1084 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKPEN_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1026 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKPEN_MASK   0x1UL

Bit mask for QSPI_SCLKPEN

Definition at line 1025 of file efm32gg12b_qspi.h.

#define _QSPI_ROUTEPEN_SCLKPEN_SHIFT   0

Shift value for QSPI_SCLKPEN

Definition at line 1024 of file efm32gg12b_qspi.h.

#define _QSPI_RXTHRESH_LEVEL_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_RXTHRESH

Definition at line 422 of file efm32gg12b_qspi.h.

#define _QSPI_RXTHRESH_LEVEL_MASK   0x1FUL

Bit mask for QSPI_LEVEL

Definition at line 421 of file efm32gg12b_qspi.h.

#define _QSPI_RXTHRESH_LEVEL_SHIFT   0

Shift value for QSPI_LEVEL

Definition at line 420 of file efm32gg12b_qspi.h.

#define _QSPI_RXTHRESH_MASK   0x0000001FUL

Mask for QSPI_RXTHRESH

Definition at line 419 of file efm32gg12b_qspi.h.

#define _QSPI_RXTHRESH_RESETVALUE   0x00000001UL

Default value for QSPI_RXTHRESH

Definition at line 418 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMFILL_MASK   0xFFFFFFFFUL

Mask for QSPI_SRAMFILL

Definition at line 399 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMFILL_RESETVALUE   0x00000000UL

Default value for QSPI_SRAMFILL

Definition at line 398 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_SRAMFILL

Definition at line 402 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_MASK   0xFFFFUL

Bit mask for QSPI_SRAMFILLINDACREAD

Definition at line 401 of file efm32gg12b_qspi.h.

Referenced by QSPI_GetReadLevel().

#define _QSPI_SRAMFILL_SRAMFILLINDACREAD_SHIFT   0

Shift value for QSPI_SRAMFILLINDACREAD

Definition at line 400 of file efm32gg12b_qspi.h.

Referenced by QSPI_GetReadLevel().

#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_SRAMFILL

Definition at line 406 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_MASK   0xFFFF0000UL

Bit mask for QSPI_SRAMFILLINDACWRITE

Definition at line 405 of file efm32gg12b_qspi.h.

Referenced by QSPI_GetWriteLevel().

#define _QSPI_SRAMFILL_SRAMFILLINDACWRITE_SHIFT   16

Shift value for QSPI_SRAMFILLINDACWRITE

Definition at line 404 of file efm32gg12b_qspi.h.

Referenced by QSPI_GetWriteLevel().

#define _QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT   0x00000080UL

Mode DEFAULT for QSPI_SRAMPARTITIONCFG

Definition at line 353 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMPARTITIONCFG_ADDR_MASK   0xFFUL

Bit mask for QSPI_ADDR

Definition at line 352 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMPARTITIONCFG_ADDR_SHIFT   0

Shift value for QSPI_ADDR

Definition at line 351 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMPARTITIONCFG_MASK   0x000000FFUL

Mask for QSPI_SRAMPARTITIONCFG

Definition at line 350 of file efm32gg12b_qspi.h.

#define _QSPI_SRAMPARTITIONCFG_RESETVALUE   0x00000080UL

Default value for QSPI_SRAMPARTITIONCFG

Definition at line 349 of file efm32gg12b_qspi.h.

#define _QSPI_TXTHRESH_LEVEL_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_TXTHRESH

Definition at line 414 of file efm32gg12b_qspi.h.

#define _QSPI_TXTHRESH_LEVEL_MASK   0x1FUL

Bit mask for QSPI_LEVEL

Definition at line 413 of file efm32gg12b_qspi.h.

#define _QSPI_TXTHRESH_LEVEL_SHIFT   0

Shift value for QSPI_LEVEL

Definition at line 412 of file efm32gg12b_qspi.h.

#define _QSPI_TXTHRESH_MASK   0x0000001FUL

Mask for QSPI_TXTHRESH

Definition at line 411 of file efm32gg12b_qspi.h.

#define _QSPI_TXTHRESH_RESETVALUE   0x00000001UL

Default value for QSPI_TXTHRESH

Definition at line 410 of file efm32gg12b_qspi.h.

#define _QSPI_UPPERWRPROT_MASK   0xFFFFFFFFUL

Mask for QSPI_UPPERWRPROT

Definition at line 666 of file efm32gg12b_qspi.h.

#define _QSPI_UPPERWRPROT_RESETVALUE   0x00000000UL

Default value for QSPI_UPPERWRPROT

Definition at line 665 of file efm32gg12b_qspi.h.

#define _QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_UPPERWRPROT

Definition at line 669 of file efm32gg12b_qspi.h.

#define _QSPI_UPPERWRPROT_SUBSECTOR_MASK   0xFFFFFFFFUL

Bit mask for QSPI_SUBSECTOR

Definition at line 668 of file efm32gg12b_qspi.h.

#define _QSPI_UPPERWRPROT_SUBSECTOR_SHIFT   0

Shift value for QSPI_SUBSECTOR

Definition at line 667 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 444 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_MASK   0x4000UL

Bit mask for QSPI_DISABLEPOLLING

Definition at line 443 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_SHIFT   14

Shift value for QSPI_DISABLEPOLLING

Definition at line 442 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 449 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_MASK   0x8000UL

Bit mask for QSPI_ENABLEPOLLINGEXP

Definition at line 448 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_SHIFT   15

Shift value for QSPI_ENABLEPOLLINGEXP

Definition at line 447 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_MASK   0xFFFFE7FFUL

Mask for QSPI_WRITECOMPLETIONCTRL

Definition at line 427 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT   0x00000005UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 430 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_MASK   0xFFUL

Bit mask for QSPI_OPCODE

Definition at line 429 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_OPCODE_SHIFT   0

Shift value for QSPI_OPCODE

Definition at line 428 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT   0x00000001UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 453 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_MASK   0xFF0000UL

Bit mask for QSPI_POLLCOUNT

Definition at line 452 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_SHIFT   16

Shift value for QSPI_POLLCOUNT

Definition at line 451 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 434 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_MASK   0x700UL

Bit mask for QSPI_POLLINGBITINDEX

Definition at line 433 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_SHIFT   8

Shift value for QSPI_POLLINGBITINDEX

Definition at line 432 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 439 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_MASK   0x2000UL

Bit mask for QSPI_POLLINGPOLARITY

Definition at line 438 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_SHIFT   13

Shift value for QSPI_POLLINGPOLARITY

Definition at line 437 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 457 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_MASK   0xFF000000UL

Bit mask for QSPI_POLLREPDELAY

Definition at line 456 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_SHIFT   24

Shift value for QSPI_POLLREPDELAY

Definition at line 455 of file efm32gg12b_qspi.h.

#define _QSPI_WRITECOMPLETIONCTRL_RESETVALUE   0x00010005UL

Default value for QSPI_WRITECOMPLETIONCTRL

Definition at line 426 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_ENB_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRPROTCTRL

Definition at line 683 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_ENB_MASK   0x2UL

Bit mask for QSPI_ENB

Definition at line 682 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_ENB_SHIFT   1

Shift value for QSPI_ENB

Definition at line 681 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_INV_DEFAULT   0x00000000UL

Mode DEFAULT for QSPI_WRPROTCTRL

Definition at line 678 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_INV_MASK   0x1UL

Bit mask for QSPI_INV

Definition at line 677 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_INV_SHIFT   0

Shift value for QSPI_INV

Definition at line 676 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_MASK   0x00000003UL

Mask for QSPI_WRPROTCTRL

Definition at line 674 of file efm32gg12b_qspi.h.

#define _QSPI_WRPROTCTRL_RESETVALUE   0x00000000UL

Default value for QSPI_WRPROTCTRL

Definition at line 673 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_CRCENABLE   (0x1UL << 29)

CRC Enable Bit

Definition at line 207 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_CRCENABLE_DEFAULT   (_QSPI_CONFIG_CRCENABLE_DEFAULT << 29)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 211 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_DEVRSTCONFIG   (0x1UL << 6)

Device Reset Configuration

Definition at line 144 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_DEVRSTCONFIG_DEFAULT   (_QSPI_CONFIG_DEVRSTCONFIG_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 148 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_DUALBYTEOPCODEEN   (0x1UL << 30)

Dual-byte Opcode Mode Enable Bit

Definition at line 212 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT   (_QSPI_CONFIG_DUALBYTEOPCODEEN_DEFAULT << 30)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 216 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENABLEAHBDECODER   (0x1UL << 23)

Enable Address Decoder

Definition at line 192 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT   (_QSPI_CONFIG_ENABLEAHBDECODER_DEFAULT << 23)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 196 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENABLEDTRPROTOCOL   (0x1UL << 24)

Enable DTR Protocol

Definition at line 197 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT   (_QSPI_CONFIG_ENABLEDTRPROTOCOL_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 201 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBAHBADDRREMAP   (0x1UL << 16)

Enable Address Remapping

Definition at line 173 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT   (_QSPI_CONFIG_ENBAHBADDRREMAP_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 177 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDEVHOLD   (0x1UL << 4)

Enable Device Hold

Definition at line 134 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDEVHOLD_DEFAULT   (_QSPI_CONFIG_ENBDEVHOLD_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 138 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDEVRST   (0x1UL << 5)

Enable Device Reset

Definition at line 139 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDEVRST_DEFAULT   (_QSPI_CONFIG_ENBDEVRST_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 143 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDIRACCCTLR   (0x1UL << 7)

Enable Direct Access Controller

Definition at line 149 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT   (_QSPI_CONFIG_ENBDIRACCCTLR_DEFAULT << 7)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 153 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBLEGACYIPMODE   (0x1UL << 8)

Legacy IP Mode Enable

Definition at line 154 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT   (_QSPI_CONFIG_ENBLEGACYIPMODE_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 158 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBSPI   (0x1UL << 0)

QSPI Enable

Definition at line 114 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENBSPI_DEFAULT   (_QSPI_CONFIG_ENBSPI_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 118 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENTERXIPMODE   (0x1UL << 17)

Enter XIP Mode on Next READ

Definition at line 178 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENTERXIPMODE_DEFAULT   (_QSPI_CONFIG_ENTERXIPMODE_DEFAULT << 17)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 182 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENTERXIPMODEIMM   (0x1UL << 18)

Enter XIP Mode Immediately

Definition at line 183 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT   (_QSPI_CONFIG_ENTERXIPMODEIMM_DEFAULT << 18)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 187 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_IDLE   (0x1UL << 31)

Serial Interface and Low Level SPI Pipeline is IDLE

Definition at line 217 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_IDLE_DEFAULT   (_QSPI_CONFIG_IDLE_DEFAULT << 31)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 221 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_MSTRBAUDDIV_DEFAULT   (_QSPI_CONFIG_MSTRBAUDDIV_DEFAULT << 19)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 191 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PERIPHCSLINES_DEFAULT   (_QSPI_CONFIG_PERIPHCSLINES_DEFAULT << 10)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 167 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PERIPHSELDEC   (0x1UL << 9)

Peripheral Select Decode

Definition at line 159 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PERIPHSELDEC_DEFAULT   (_QSPI_CONFIG_PERIPHSELDEC_DEFAULT << 9)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 163 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PHYMODEENABLE   (0x1UL << 3)

PHY Mode Enable

Definition at line 129 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PHYMODEENABLE_DEFAULT   (_QSPI_CONFIG_PHYMODEENABLE_DEFAULT << 3)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 133 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PIPELINEPHY   (0x1UL << 25)

Pipeline PHY Mode Enable

Definition at line 202 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_PIPELINEPHY_DEFAULT   (_QSPI_CONFIG_PIPELINEPHY_DEFAULT << 25)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 206 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_SELCLKPHASE   (0x1UL << 2)

Clock Phase, CPHA

Definition at line 124 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_SELCLKPHASE_DEFAULT   (_QSPI_CONFIG_SELCLKPHASE_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 128 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_SELCLKPOL   (0x1UL << 1)

Clock Polarity, CPOL

Definition at line 119 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_SELCLKPOL_DEFAULT   (_QSPI_CONFIG_SELCLKPOL_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 123 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_WRPROTFLASH   (0x1UL << 14)

Write Protect Flash Pin

Definition at line 168 of file efm32gg12b_qspi.h.

#define QSPI_CONFIG_WRPROTFLASH_DEFAULT   (_QSPI_CONFIG_WRPROTFLASH_DEFAULT << 14)

Shifted mode DEFAULT for QSPI_CONFIG

Definition at line 172 of file efm32gg12b_qspi.h.

#define QSPI_DEVDELAY_DAFTER_DEFAULT   (_QSPI_DEVDELAY_DAFTER_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_DEVDELAY

Definition at line 292 of file efm32gg12b_qspi.h.

#define QSPI_DEVDELAY_DBTWN_DEFAULT   (_QSPI_DEVDELAY_DBTWN_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_DEVDELAY

Definition at line 296 of file efm32gg12b_qspi.h.

#define QSPI_DEVDELAY_DINIT_DEFAULT   (_QSPI_DEVDELAY_DINIT_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_DEVDELAY

Definition at line 288 of file efm32gg12b_qspi.h.

#define QSPI_DEVDELAY_DNSS_DEFAULT   (_QSPI_DEVDELAY_DNSS_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_DEVDELAY

Definition at line 300 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 242 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 246 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_DDREN   (0x1UL << 10)

DDR Enable

Definition at line 234 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DDREN_DEFAULT << 10)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 238 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_DUMMYRDCLKCYCLES_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 255 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_INSTRTYPE_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 233 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE   (0x1UL << 20)

Mode Bit Enable

Definition at line 247 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_MODEBITENABLE_DEFAULT << 20)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 251 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT   (_QSPI_DEVINSTRRDCONFIG_RDOPCODENONXIP_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_DEVINSTRRDCONFIG

Definition at line 229 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_ADDRXFERTYPESTDMODE_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 272 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_DATAXFERTYPEEXTMODE_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 276 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_DUMMYWRCLKCYCLES_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 280 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_WELDIS   (0x1UL << 8)

WEL Disable

Definition at line 264 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_WELDIS_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 268 of file efm32gg12b_qspi.h.

#define QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT   (_QSPI_DEVINSTRWRCONFIG_WROPCODE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_DEVINSTRWRCONFIG

Definition at line 263 of file efm32gg12b_qspi.h.

#define QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT   (_QSPI_DEVSIZECONFIG_BYTESPERDEVICEPAGE_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 334 of file efm32gg12b_qspi.h.

#define QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT   (_QSPI_DEVSIZECONFIG_BYTESPERSUBSECTOR_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 338 of file efm32gg12b_qspi.h.

#define QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT   (_QSPI_DEVSIZECONFIG_MEMSIZEONCS0_DEFAULT << 21)

Shifted mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 342 of file efm32gg12b_qspi.h.

#define QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT   (_QSPI_DEVSIZECONFIG_MEMSIZEONCS1_DEFAULT << 23)

Shifted mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 346 of file efm32gg12b_qspi.h.

#define QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT   (_QSPI_DEVSIZECONFIG_NUMADDRBYTES_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_DEVSIZECONFIG

Definition at line 330 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDADDR_ADDR_DEFAULT   (_QSPI_FLASHCMDADDR_ADDR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHCMDADDR

Definition at line 904 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_CMDEXEC   (0x1UL << 0)

Execute the Command

Definition at line 842 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDEXEC_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 846 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS   (0x1UL << 1)

Command Execution in Progress

Definition at line 847 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDEXECSTATUS_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 851 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT   (_QSPI_FLASHCMDCTRL_CMDOPCODE_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 896 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_ENBCOMDADDR   (0x1UL << 19)

Command Address Enable

Definition at line 879 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBCOMDADDR_DEFAULT << 19)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 883 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_ENBMODEBIT   (0x1UL << 18)

Mode Bit Enable

Definition at line 874 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBMODEBIT_DEFAULT << 18)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 878 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_ENBREADDATA   (0x1UL << 23)

Read Data Enable

Definition at line 888 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBREADDATA_DEFAULT << 23)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 892 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_ENBWRITEDATA   (0x1UL << 15)

Write Data Enable

Definition at line 865 of file efm32gg12b_qspi.h.

Referenced by QSPI_ExecStigCmd().

#define QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT   (_QSPI_FLASHCMDCTRL_ENBWRITEDATA_DEFAULT << 15)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 869 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMADDRBYTES_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 873 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMDUMMYCYCLES_DEFAULT << 7)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 860 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMRDDATABYTES_DEFAULT << 20)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 887 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT   (_QSPI_FLASHCMDCTRL_NUMWRDATABYTES_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 864 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN   (0x1UL << 2)

STIG Memory Bank Enable Bit

Definition at line 852 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT   (_QSPI_FLASHCMDCTRL_STIGMEMBANKEN_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_FLASHCMDCTRL

Definition at line 856 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKADDR_DEFAULT << 20)

Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 837 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREADDATA_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 829 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS   (0x1UL << 1)

Memory Bank Data Request in Progress

Definition at line 821 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_MEMBANKREQINPROGRESS_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 825 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_NBOFSTIGREADBYTES_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 833 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ   (0x1UL << 0)

Trigger the Memory Bank Data Request

Definition at line 816 of file efm32gg12b_qspi.h.

#define QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT   (_QSPI_FLASHCOMMANDCTRLMEM_TRIGGERMEMBANKREQ_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHCOMMANDCTRLMEM

Definition at line 820 of file efm32gg12b_qspi.h.

#define QSPI_FLASHRDDATALOWER_DATA_DEFAULT   (_QSPI_FLASHRDDATALOWER_DATA_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHRDDATALOWER

Definition at line 912 of file efm32gg12b_qspi.h.

#define QSPI_FLASHRDDATAUPPER_DATA_DEFAULT   (_QSPI_FLASHRDDATAUPPER_DATA_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHRDDATAUPPER

Definition at line 920 of file efm32gg12b_qspi.h.

#define QSPI_FLASHWRDATALOWER_DATA_DEFAULT   (_QSPI_FLASHWRDATALOWER_DATA_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHWRDATALOWER

Definition at line 928 of file efm32gg12b_qspi.h.

#define QSPI_FLASHWRDATAUPPER_DATA_DEFAULT   (_QSPI_FLASHWRDATAUPPER_DATA_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_FLASHWRDATAUPPER

Definition at line 936 of file efm32gg12b_qspi.h.

#define QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT   (_QSPI_INDAHBADDRTRIGGER_ADDR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDAHBADDRTRIGGER

Definition at line 362 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_CANCEL   (0x1UL << 1)

Cancel Indirect Read

Definition at line 694 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_CANCEL_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 698 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS   (0x1UL << 5)

Indirect Completion Status

Definition at line 714 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 718 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 722 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED   (0x1UL << 4)

Two Indirect Read Operations Have Been Queued

Definition at line 709 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_RDQUEUED_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 713 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS   (0x1UL << 2)

Indirect Read Status

Definition at line 699 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_RDSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 703 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL   (0x1UL << 3)

SRAM Full

Definition at line 704 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_SRAMFULL_DEFAULT << 3)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 708 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_START   (0x1UL << 0)

Start Indirect Read

Definition at line 689 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERCTRL_START_DEFAULT   (_QSPI_INDIRECTREADXFERCTRL_START_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERCTRL

Definition at line 693 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT   (_QSPI_INDIRECTREADXFERNUMBYTES_VALUE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERNUMBYTES

Definition at line 746 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT   (_QSPI_INDIRECTREADXFERSTART_ADDR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERSTART

Definition at line 738 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT   (_QSPI_INDIRECTREADXFERWATERMARK_LEVEL_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTREADXFERWATERMARK

Definition at line 730 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT   (_QSPI_INDIRECTTRIGGERADDRRANGE_INDRANGEWIDTH_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTTRIGGERADDRRANGE

Definition at line 811 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL   (0x1UL << 1)

Cancel Indirect Write

Definition at line 756 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_CANCEL_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 760 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS   (0x1UL << 5)

Indirect Completion Status

Definition at line 771 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_INDOPSDONESTATUS_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 775 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_NUMINDOPSDONE_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 779 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_START   (0x1UL << 0)

Start Indirect Write

Definition at line 751 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_START_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 755 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED   (0x1UL << 4)

Two Indirect Write Operations Have Been Queued

Definition at line 766 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_WRQUEUED_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 770 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS   (0x1UL << 2)

Indirect Write Status

Definition at line 761 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT   (_QSPI_INDIRECTWRITEXFERCTRL_WRSTATUS_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERCTRL

Definition at line 765 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT   (_QSPI_INDIRECTWRITEXFERNUMBYTES_VALUE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERNUMBYTES

Definition at line 803 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT   (_QSPI_INDIRECTWRITEXFERSTART_ADDR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERSTART

Definition at line 795 of file efm32gg12b_qspi.h.

#define QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT   (_QSPI_INDIRECTWRITEXFERWATERMARK_LEVEL_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_INDIRECTWRITEXFERWATERMARK

Definition at line 787 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_ILLEGALACCESSDETMASK   (0x1UL << 5)

Illegal Access Detected Mask

Definition at line 590 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT   (_QSPI_IRQMASK_ILLEGALACCESSDETMASK_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 594 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTOPDONEMASK   (0x1UL << 2)

Indirect Complete Mask

Definition at line 575 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTOPDONEMASK_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 579 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTREADREJECTMASK   (0x1UL << 3)

Indirect Read Reject Mask

Definition at line 580 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTREADREJECTMASK_DEFAULT << 3)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 584 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK   (0x1UL << 6)

Transfer Watermark Breach Mask

Definition at line 595 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT   (_QSPI_IRQMASK_INDIRECTXFERLEVELBREACHMASK_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 599 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDRDSRAMFULLMASK   (0x1UL << 12)

Indirect Read Partition Overflow Mask

Definition at line 625 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT   (_QSPI_IRQMASK_INDRDSRAMFULLMASK_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 629 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_MODEMFAILMASK   (0x1UL << 0)

Mode M Failure Mask

Definition at line 565 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_MODEMFAILMASK_DEFAULT   (_QSPI_IRQMASK_MODEMFAILMASK_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 569 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_POLLEXPINTMASK   (0x1UL << 13)

Polling Expiration Detected Mask

Definition at line 630 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT   (_QSPI_IRQMASK_POLLEXPINTMASK_DEFAULT << 13)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 634 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_PROTWRATTEMPTMASK   (0x1UL << 4)

Protected Area Write Attempt Mask

Definition at line 585 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT   (_QSPI_IRQMASK_PROTWRATTEMPTMASK_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 589 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RECVOVERFLOWMASK   (0x1UL << 7)

Receive Overflow Mask

Definition at line 600 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT   (_QSPI_IRQMASK_RECVOVERFLOWMASK_DEFAULT << 7)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 604 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXCRCDATAERRMASK   (0x1UL << 16)

RX CRC Data Error Mask

Definition at line 640 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT   (_QSPI_IRQMASK_RXCRCDATAERRMASK_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 644 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXCRCDATAVALMASK   (0x1UL << 17)

RX CRC Data Valid Mask

Definition at line 645 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT   (_QSPI_IRQMASK_RXCRCDATAVALMASK_DEFAULT << 17)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 649 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXFIFOFULLMASK   (0x1UL << 11)

Small RX FIFO Full Mask

Definition at line 620 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT   (_QSPI_IRQMASK_RXFIFOFULLMASK_DEFAULT << 11)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 624 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK   (0x1UL << 10)

Small RX FIFO Not Empty Mask

Definition at line 615 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT   (_QSPI_IRQMASK_RXFIFONOTEMPTYMASK_DEFAULT << 10)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 619 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_STIGREQMASK   (0x1UL << 14)

STIG Request Completion Mask

Definition at line 635 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_STIGREQMASK_DEFAULT   (_QSPI_IRQMASK_STIGREQMASK_DEFAULT << 14)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 639 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK   (0x1UL << 18)

TX CRC Chunk Was Broken Mask

Definition at line 650 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT   (_QSPI_IRQMASK_TXCRCCHUNKBRKMASK_DEFAULT << 18)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 654 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXFIFOFULLMASK   (0x1UL << 9)

Small TX FIFO Full Mask

Definition at line 610 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT   (_QSPI_IRQMASK_TXFIFOFULLMASK_DEFAULT << 9)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 614 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXFIFONOTFULLMASK   (0x1UL << 8)

Small TX FIFO Not Full Mask

Definition at line 605 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT   (_QSPI_IRQMASK_TXFIFONOTFULLMASK_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 609 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_UNDERFLOWDETMASK   (0x1UL << 1)

Underflow Detected Mask

Definition at line 570 of file efm32gg12b_qspi.h.

#define QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT   (_QSPI_IRQMASK_UNDERFLOWDETMASK_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_IRQMASK

Definition at line 574 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_ILLEGALACCESSDET   (0x1UL << 5)

Illegal Memory Access Has Been Detected

Definition at line 496 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT   (_QSPI_IRQSTATUS_ILLEGALACCESSDET_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 500 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTOPDONE   (0x1UL << 2)

Indirect Operation Complete

Definition at line 481 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTOPDONE_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 485 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTREADREJECT   (0x1UL << 3)

Indirect Operation Was Requested but Could Not Be Accepted

Definition at line 486 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTREADREJECT_DEFAULT << 3)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 490 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH   (0x1UL << 6)

Indirect Transfer Watermark Level Breached

Definition at line 501 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT   (_QSPI_IRQSTATUS_INDIRECTXFERLEVELBREACH_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 505 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDRDSRAMFULL   (0x1UL << 12)

Indirect Read Partition Overflow

Definition at line 531 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT   (_QSPI_IRQSTATUS_INDRDSRAMFULL_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 535 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_MODEMFAIL   (0x1UL << 0)

Mode M Failure

Definition at line 471 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_MODEMFAIL_DEFAULT   (_QSPI_IRQSTATUS_MODEMFAIL_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 475 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_POLLEXPINT   (0x1UL << 13)

The Maximum Number of Programmed Polls Cycles is Expired

Definition at line 536 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_POLLEXPINT_DEFAULT   (_QSPI_IRQSTATUS_POLLEXPINT_DEFAULT << 13)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 540 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_PROTWRATTEMPT   (0x1UL << 4)

Write to Protected Area Was Attempted and Rejected

Definition at line 491 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT   (_QSPI_IRQSTATUS_PROTWRATTEMPT_DEFAULT << 4)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 495 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RECVOVERFLOW   (0x1UL << 7)

Receive Overflow

Definition at line 506 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT   (_QSPI_IRQSTATUS_RECVOVERFLOW_DEFAULT << 7)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 510 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXCRCDATAERR   (0x1UL << 16)

RX CRC Data Error

Definition at line 546 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT   (_QSPI_IRQSTATUS_RXCRCDATAERR_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 550 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXCRCDATAVAL   (0x1UL << 17)

RX CRC Data Valid

Definition at line 551 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT   (_QSPI_IRQSTATUS_RXCRCDATAVAL_DEFAULT << 17)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 555 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXFIFOFULL   (0x1UL << 11)

Small RX FIFO Full

Definition at line 526 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT   (_QSPI_IRQSTATUS_RXFIFOFULL_DEFAULT << 11)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 530 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXFIFONOTEMPTY   (0x1UL << 10)

Small RX FIFO Not Empty

Definition at line 521 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT   (_QSPI_IRQSTATUS_RXFIFONOTEMPTY_DEFAULT << 10)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 525 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_STIGREQINT   (0x1UL << 14)

The Controller is Ready for Getting Another STIG Request

Definition at line 541 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_STIGREQINT_DEFAULT   (_QSPI_IRQSTATUS_STIGREQINT_DEFAULT << 14)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 545 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXCRCCHUNKBRK   (0x1UL << 18)

TX CRC Chunk Was Broken

Definition at line 556 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT   (_QSPI_IRQSTATUS_TXCRCCHUNKBRK_DEFAULT << 18)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 560 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXFIFOFULL   (0x1UL << 9)

Small TX FIFO Full

Definition at line 516 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT   (_QSPI_IRQSTATUS_TXFIFOFULL_DEFAULT << 9)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 520 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXFIFONOTFULL   (0x1UL << 8)

Small TX FIFO Not Full

Definition at line 511 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT   (_QSPI_IRQSTATUS_TXFIFONOTFULL_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 515 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_UNDERFLOWDET   (0x1UL << 1)

Underflow Detected

Definition at line 476 of file efm32gg12b_qspi.h.

#define QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT   (_QSPI_IRQSTATUS_UNDERFLOWDET_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_IRQSTATUS

Definition at line 480 of file efm32gg12b_qspi.h.

#define QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT   (_QSPI_LOWERWRPROT_SUBSECTOR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_LOWERWRPROT

Definition at line 662 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT   (_QSPI_MODEBITCONFIG_CHUNKSIZE_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 382 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_CRCOUTENABLE   (0x1UL << 15)

CRC# Output Enable Bit

Definition at line 383 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT   (_QSPI_MODEBITCONFIG_CRCOUTENABLE_DEFAULT << 15)

Shifted mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 387 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_MODE_DEFAULT   (_QSPI_MODEBITCONFIG_MODE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 378 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT   (_QSPI_MODEBITCONFIG_RXCRCDATALOW_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 395 of file efm32gg12b_qspi.h.

#define QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT   (_QSPI_MODEBITCONFIG_RXCRCDATAUP_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_MODEBITCONFIG

Definition at line 391 of file efm32gg12b_qspi.h.

#define QSPI_MODULEID_CONF_DEFAULT   (_QSPI_MODULEID_CONF_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_MODULEID

Definition at line 1010 of file efm32gg12b_qspi.h.

#define QSPI_MODULEID_FIXPATCH_DEFAULT   (_QSPI_MODULEID_FIXPATCH_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_MODULEID

Definition at line 1018 of file efm32gg12b_qspi.h.

#define QSPI_MODULEID_MODULEID_DEFAULT   (_QSPI_MODULEID_MODULEID_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_MODULEID

Definition at line 1014 of file efm32gg12b_qspi.h.

#define QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT   (_QSPI_NOOFPOLLSBEFEXP_NOOFPOLLSBEFEXP_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_NOOFPOLLSBEFEXP

Definition at line 466 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTPOLLOPCODE_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 982 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTREADOPCODE_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 990 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTSTIGOPCODE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 978 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT   (_QSPI_OPCODEEXTLOWER_EXTWRITEOPCODE_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_OPCODEEXTLOWER

Definition at line 986 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT   (_QSPI_OPCODEEXTUPPER_EXTWELOPCODE_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER

Definition at line 998 of file efm32gg12b_qspi.h.

#define QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT   (_QSPI_OPCODEEXTUPPER_WELOPCODE_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_OPCODEEXTUPPER

Definition at line 1002 of file efm32gg12b_qspi.h.

#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC   (0x1UL << 31)

PHY Config Resync

Definition at line 966 of file efm32gg12b_qspi.h.

#define QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGRESYNC_DEFAULT << 31)

Shifted mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 970 of file efm32gg12b_qspi.h.

#define QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGRXDLLDELAY_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 961 of file efm32gg12b_qspi.h.

#define QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT   (_QSPI_PHYCONFIGURATION_PHYCONFIGTXDLLDELAY_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_PHYCONFIGURATION

Definition at line 965 of file efm32gg12b_qspi.h.

#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUS_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 944 of file efm32gg12b_qspi.h.

#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSNBDUMMY_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 953 of file efm32gg12b_qspi.h.

#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID   (0x1UL << 8)

Device Status Valid

Definition at line 945 of file efm32gg12b_qspi.h.

#define QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT   (_QSPI_POLLINGFLASHSTATUS_DEVICESTATUSVALID_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_POLLINGFLASHSTATUS

Definition at line 949 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_BYPASS   (0x1UL << 0)

Bypass the Adapted Loopback Clock Circuit

Definition at line 305 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_BYPASS_DEFAULT   (_QSPI_RDDATACAPTURE_BYPASS_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 309 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT   (_QSPI_RDDATACAPTURE_DDRREADDELAY_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 322 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_DELAY_DEFAULT   (_QSPI_RDDATACAPTURE_DELAY_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 313 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_DQSENABLE   (0x1UL << 8)

DQS Enable Bit

Definition at line 314 of file efm32gg12b_qspi.h.

#define QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT   (_QSPI_RDDATACAPTURE_DQSENABLE_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_RDDATACAPTURE

Definition at line 318 of file efm32gg12b_qspi.h.

#define QSPI_REMAPADDR_VALUE_DEFAULT   (_QSPI_REMAPADDR_VALUE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_REMAPADDR

Definition at line 370 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPILOC_DEFAULT   (_QSPI_ROUTELOC0_QSPILOC_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_ROUTELOC0

Definition at line 1108 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPILOC_LOC0   (_QSPI_ROUTELOC0_QSPILOC_LOC0 << 0)

Shifted mode LOC0 for QSPI_ROUTELOC0

Definition at line 1107 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPILOC_LOC1   (_QSPI_ROUTELOC0_QSPILOC_LOC1 << 0)

Shifted mode LOC1 for QSPI_ROUTELOC0

Definition at line 1109 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT   (_QSPI_ROUTELOC0_QSPIRSTLOC_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_ROUTELOC0

Definition at line 1116 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPIRSTLOC_LOC0   (_QSPI_ROUTELOC0_QSPIRSTLOC_LOC0 << 6)

Shifted mode LOC0 for QSPI_ROUTELOC0

Definition at line 1115 of file efm32gg12b_qspi.h.

#define QSPI_ROUTELOC0_QSPIRSTLOC_LOC1   (_QSPI_ROUTELOC0_QSPIRSTLOC_LOC1 << 6)

Shifted mode LOC1 for QSPI_ROUTELOC0

Definition at line 1117 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_CS0PEN   (0x1UL << 1)

CS0 Pin Enable

Definition at line 1028 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_CS0PEN_DEFAULT   (_QSPI_ROUTEPEN_CS0PEN_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1032 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_CS1PEN   (0x1UL << 2)

CS1 Pin Enable

Definition at line 1033 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_CS1PEN_DEFAULT   (_QSPI_ROUTEPEN_CS1PEN_DEFAULT << 2)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1037 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ0PEN   (0x1UL << 5)

DQ0 Pin Enable

Definition at line 1038 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ0PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ0PEN_DEFAULT << 5)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1042 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ1PEN   (0x1UL << 6)

DQ1 Pin Enable

Definition at line 1043 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ1PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ1PEN_DEFAULT << 6)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1047 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ2PEN   (0x1UL << 7)

DQ2 Pin Enable

Definition at line 1048 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ2PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ2PEN_DEFAULT << 7)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1052 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ3PEN   (0x1UL << 8)

DQ3 Pin Enable

Definition at line 1053 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ3PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ3PEN_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1057 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ4PEN   (0x1UL << 9)

DQ4 Pin Enable

Definition at line 1058 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ4PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ4PEN_DEFAULT << 9)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1062 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ5PEN   (0x1UL << 10)

DQ5 Pin Enable

Definition at line 1063 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ5PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ5PEN_DEFAULT << 10)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1067 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ6PEN   (0x1UL << 11)

DQ6 Pin Enable

Definition at line 1068 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ6PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ6PEN_DEFAULT << 11)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1072 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ7PEN   (0x1UL << 12)

DQ7 Pin Enable

Definition at line 1073 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQ7PEN_DEFAULT   (_QSPI_ROUTEPEN_DQ7PEN_DEFAULT << 12)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1077 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQSPEN   (0x1UL << 13)

DQS Pin Enable

Definition at line 1078 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_DQSPEN_DEFAULT   (_QSPI_ROUTEPEN_DQSPEN_DEFAULT << 13)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1082 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_RST0PEN   (0x1UL << 16)

RST0 Pin Enable

Definition at line 1088 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_RST0PEN_DEFAULT   (_QSPI_ROUTEPEN_RST0PEN_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1092 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_RST1PEN   (0x1UL << 17)

RST1 Pin Enable

Definition at line 1093 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_RST1PEN_DEFAULT   (_QSPI_ROUTEPEN_RST1PEN_DEFAULT << 17)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1097 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_SCLKINPEN   (0x1UL << 14)

SCLKIN Pin Enable

Definition at line 1083 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_SCLKINPEN_DEFAULT   (_QSPI_ROUTEPEN_SCLKINPEN_DEFAULT << 14)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1087 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_SCLKPEN   (0x1UL << 0)

SCLK Pin Enable

Definition at line 1023 of file efm32gg12b_qspi.h.

#define QSPI_ROUTEPEN_SCLKPEN_DEFAULT   (_QSPI_ROUTEPEN_SCLKPEN_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_ROUTEPEN

Definition at line 1027 of file efm32gg12b_qspi.h.

#define QSPI_RXTHRESH_LEVEL_DEFAULT   (_QSPI_RXTHRESH_LEVEL_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_RXTHRESH

Definition at line 423 of file efm32gg12b_qspi.h.

#define QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT   (_QSPI_SRAMFILL_SRAMFILLINDACREAD_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_SRAMFILL

Definition at line 403 of file efm32gg12b_qspi.h.

#define QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT   (_QSPI_SRAMFILL_SRAMFILLINDACWRITE_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_SRAMFILL

Definition at line 407 of file efm32gg12b_qspi.h.

#define QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT   (_QSPI_SRAMPARTITIONCFG_ADDR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_SRAMPARTITIONCFG

Definition at line 354 of file efm32gg12b_qspi.h.

#define QSPI_TXTHRESH_LEVEL_DEFAULT   (_QSPI_TXTHRESH_LEVEL_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_TXTHRESH

Definition at line 415 of file efm32gg12b_qspi.h.

#define QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT   (_QSPI_UPPERWRPROT_SUBSECTOR_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_UPPERWRPROT

Definition at line 670 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING   (0x1UL << 14)

Disable Polling

Definition at line 441 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_DISABLEPOLLING_DEFAULT << 14)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 445 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP   (0x1UL << 15)

Enable Polling Expiration

Definition at line 446 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_ENABLEPOLLINGEXP_DEFAULT << 15)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 450 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_OPCODE_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 431 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLCOUNT_DEFAULT << 16)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 454 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLINGBITINDEX_DEFAULT << 8)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 435 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY   (0x1UL << 13)

Polling Polarity

Definition at line 436 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLINGPOLARITY_DEFAULT << 13)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 440 of file efm32gg12b_qspi.h.

#define QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT   (_QSPI_WRITECOMPLETIONCTRL_POLLREPDELAY_DEFAULT << 24)

Shifted mode DEFAULT for QSPI_WRITECOMPLETIONCTRL

Definition at line 458 of file efm32gg12b_qspi.h.

#define QSPI_WRPROTCTRL_ENB   (0x1UL << 1)

Write Protection Enable Bit

Definition at line 680 of file efm32gg12b_qspi.h.

#define QSPI_WRPROTCTRL_ENB_DEFAULT   (_QSPI_WRPROTCTRL_ENB_DEFAULT << 1)

Shifted mode DEFAULT for QSPI_WRPROTCTRL

Definition at line 684 of file efm32gg12b_qspi.h.

#define QSPI_WRPROTCTRL_INV   (0x1UL << 0)

Write Protection Inversion Bit

Definition at line 675 of file efm32gg12b_qspi.h.

#define QSPI_WRPROTCTRL_INV_DEFAULT   (_QSPI_WRPROTCTRL_INV_DEFAULT << 0)

Shifted mode DEFAULT for QSPI_WRPROTCTRL

Definition at line 679 of file efm32gg12b_qspi.h.