This file contains the type definitions for efr32xg1x chip-specific aspects of RAIL.

License#

Copyright 2020 Silicon Laboratories Inc. www.silabs.com

SPDX-License-Identifier: Zlib

The licensor of this software is Silicon Laboratories Inc.

This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software.

Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions:

  1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required.

  2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software.

  3. This notice may not be removed or altered from any source distribution.

Modules#

RAIL_ChannelConfigEntryAttr

Macros#

#define

SLI_LIBRARY_BUILD.

#define
RAIL_ENUM (name)

The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.

#define
RAIL_ENUM_GENERIC (name, type)

This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.

#define

Time it takes to take care of protocol switching.

#define

Indicates the number of RF Paths supported.

#define

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.

#define

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.

#define

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.

#define

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.

#define

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.

#define

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.

#define
RAIL_TX_POWER_LEVEL_LP_MAX RAIL_TX_POWER_LEVEL_2P4_LP_MAX

Backwards compatibility define.

#define
RAIL_TX_POWER_LEVEL_HP_MAX RAIL_TX_POWER_LEVEL_2P4_HP_MAX

Backwards compatibility define.

#define
RAIL_TX_POWER_LEVEL_SUBGIG_MAX RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX

Backwards compatibility define.

#define
RAIL_TX_POWER_LEVEL_LP_MIN RAIL_TX_POWER_LEVEL_2P4_LP_MIN

Backwards compatibility define.

#define
RAIL_TX_POWER_LEVEL_HP_MIN RAIL_TX_POWER_LEVEL_2P4_HP_MIN

Backwards compatibility define.

#define
RAIL_TX_POWER_LEVEL_SUBGIG_MIN RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN

Backwards compatibility define.

#define

The number of PA's on this chip.

#define

The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.

#define

Default PRS channel to use when configuring sleep.

#define

Default RTCC channel to use when configuring sleep.

#define

Default timer synchronization configuration.

#define

The minimum value for a consistent RAIL transition.

#define

The maximum value for a consistent RAIL transition.

Macro Definition Documentation#

__RAIL_CHIP_SPECIFIC_H_#

#define __RAIL_CHIP_SPECIFIC_H_

SLI_LIBRARY_BUILD.

Include guard


Definition at line 44 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_ENUM#

#define RAIL_ENUM
Value:
(name)

The RAIL library does not use enumerations because the ARM EABI leaves their size ambiguous, which causes problems if the application is built with different flags than the library.

Instead, uint8_t typedefs are used in compiled code for all enumerations. For documentation purposes, this is converted to an actual enumeration since it's much easier to read in Doxygen.


Definition at line 55 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_ENUM_GENERIC#

#define RAIL_ENUM_GENERIC
Value:
(name, type)

This macro is a more generic version of the RAIL_ENUM() macro that allows the size of the type to be overridden instead of forcing the use of a uint8_t.

See RAIL_ENUM() for more information.


Definition at line 59 of file chip/efr32/efr32xg1x/rail_chip_specific.h

TRANSITION_TIME_US#

#define TRANSITION_TIME_US
Value:
430

Time it takes to take care of protocol switching.


Definition at line 191 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_RF_PATHS#

#define RAIL_RF_PATHS
Value:
1

Indicates the number of RF Paths supported.


Definition at line 209 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_2P4_LP_MAX#

#define RAIL_TX_POWER_LEVEL_2P4_LP_MAX
Value:
(7U)

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.


Definition at line 241 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_2P4_HP_MAX#

#define RAIL_TX_POWER_LEVEL_2P4_HP_MAX
Value:
(252U)

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.


Definition at line 246 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX#

#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX
Value:
(248U)

The maximum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.


Definition at line 251 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_2P4_LP_MIN#

#define RAIL_TX_POWER_LEVEL_2P4_LP_MIN
Value:
(1U)

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_LP mode.


Definition at line 256 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_2P4_HP_MIN#

#define RAIL_TX_POWER_LEVEL_2P4_HP_MIN
Value:
(0U)

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_2P4_HP mode.


Definition at line 261 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN#

#define RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN
Value:
(0U)

The minimum valid value for the RAIL_TxPowerLevel_t when in RAIL_TX_POWER_MODE_SUBGIG mode.


Definition at line 266 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_LP_MAX#

#define RAIL_TX_POWER_LEVEL_LP_MAX
Value:
RAIL_TX_POWER_LEVEL_2P4_LP_MAX

Backwards compatibility define.


Definition at line 269 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_HP_MAX#

#define RAIL_TX_POWER_LEVEL_HP_MAX
Value:
RAIL_TX_POWER_LEVEL_2P4_HP_MAX

Backwards compatibility define.


Definition at line 271 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_SUBGIG_MAX#

#define RAIL_TX_POWER_LEVEL_SUBGIG_MAX
Value:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MAX

Backwards compatibility define.


Definition at line 273 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_LP_MIN#

#define RAIL_TX_POWER_LEVEL_LP_MIN
Value:
RAIL_TX_POWER_LEVEL_2P4_LP_MIN

Backwards compatibility define.


Definition at line 275 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_HP_MIN#

#define RAIL_TX_POWER_LEVEL_HP_MIN
Value:
RAIL_TX_POWER_LEVEL_2P4_HP_MIN

Backwards compatibility define.


Definition at line 277 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TX_POWER_LEVEL_SUBGIG_MIN#

#define RAIL_TX_POWER_LEVEL_SUBGIG_MIN
Value:
RAIL_TX_POWER_LEVEL_SUBGIG_HP_MIN

Backwards compatibility define.


Definition at line 279 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_NUM_PA#

#define RAIL_NUM_PA
Value:
(3U)

The number of PA's on this chip.

(Including Virtual PAs)


Definition at line 284 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL#

#define RAIL_CHANNEL_HOPPING_BUFFER_SIZE_PER_CHANNEL
Value:
(55U)

The static amount of memory needed per channel for channel hopping, measured in 32 bit words, regardless of the size of radio configuration structures.


Definition at line 310 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT#

#define RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT
Value:
(7U)

Default PRS channel to use when configuring sleep.


Definition at line 325 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT#

#define RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT
Value:
(0U)

Default RTCC channel to use when configuring sleep.


Definition at line 332 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_TIMER_SYNC_DEFAULT#

#define RAIL_TIMER_SYNC_DEFAULT
Value:
{ \
RAIL_TIMER_SYNC_PRS_CHANNEL_DEFAULT, \
RAIL_TIMER_SYNC_RTCC_CHANNEL_DEFAULT, \
RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED, \
}

Default timer synchronization configuration.


Definition at line 336 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_MINIMUM_TRANSITION_US#

#define RAIL_MINIMUM_TRANSITION_US
Value:
(100U)

The minimum value for a consistent RAIL transition.

Note


Definition at line 356 of file chip/efr32/efr32xg1x/rail_chip_specific.h

RAIL_MAXIMUM_TRANSITION_US#

#define RAIL_MAXIMUM_TRANSITION_US
Value:
(1000000U)

The maximum value for a consistent RAIL transition.

(_SILICON_LABS_32B_SERIES_1_CONFIG == 1)


Definition at line 365 of file chip/efr32/efr32xg1x/rail_chip_specific.h