Simplicity SDK Platform - CMSIS Device Version 5.2.2 (September 24, 2025) - Release Notes#

Simplicity SDK Platform Version 5.2.2

Simplicity SDK Version 2025.6.2

Release Summary#

Key Features | API Changes | Bug Fixes | Chip Enablement

Key Features#

Added in 5.2.2#

  • New Clock Manager PCLK divider auto-configuration option

Added in 5.2.1#

None.

Added in 5.2.0#

  • FreeRTOS kernel upgraded to LTS version 11.1.0.

  • New sl_main component for device initialization sequence.

  • Added Memory Protection and Attribute (MPA) Manager.

  • Added Peripheral HAL hardware abstraction library for Series 2 and 3 devices.

  • sl_gpio components for GPIO enabled with production quality.

  • New common_token_manager component for storing/retrieving tokens is added with evaluation quality.

  • Added support for GCC Link Time Optimization (LTO).

API Changes#

Added in 5.2.2#

None.

Added in 5.2.1#

None.

Added in 5.2.0#

  • Power/Clock Manager: New APIs for runtime clock changes and SYSCLK source control.

  • Clock Manager: oscillator calibration override via NVM3.

  • Memory Manager: Multi-heap operations.

Bug Fixes#

Fixed in 5.2.2#

  • Clock Manager bug fixes and validation improvements.

  • EMLIB EM4 entry bug fix.

  • IOStream EUSART EM2 bug fix.

Fixed in 5.2.1#

Fixed the HFRCO default clock for some series 2 device parts that are limited to 38.4MHz.

Fixed in 5.2.0#

  • Fixes in Memory Manager.

  • Fixes in Pin Tool SPI support.

  • Fixes in IOStream.

Chip Enablement#

Added in 5.2.2#

  • Added support for the SiXG301 family of devices (Series 3). Note that the SiXG301 devices are only supported with GCC (no IAR support), see the Known Issues and Limitations section for more details.

  • Added support for EFR32BG22L and EFR32FG23L device families

Added in 5.2.1#

None.

Added in 5.2.0#

  • Added support for the EFR32BG29 and EFR32MG29 devices (Series 2).

  • Added support for the EFR32BG22L devices (EFR32BG22L122F352GM32).

  • Added support for the EFR32BG24L devices (EFR32BG24L010F768IM40 and EFR32BG24L210F768IM40).

  • Added support for the MGM260P devices (MGM260PD32VNA, MGM260PD32VNN, MGM260PD22VNA, MGM260PB32VNA, MGM260PB32VNN, MGM260PB22VNA).

  • Added support for the BGM260P devices (BGM260PB22VNA, BGM260PB32VNA).

Key Features#

New Features | Enhancements | Removed Features | Deprecated Features

New Features#

Added in 5.2.2#

  • NVM3: Improved NVM3 host-crypto performance by moving AES-GCM execution to RAM.

  • Token Manager:

    • Static secure tokens are now secured using AES-GCM 128-bit authenticated encryption on Series-3 device.

    • Static secure tokens are configurable. Change in the default static secure configuration size would result in change in NVM3 start and end address.

    • Static tokens can be overridden and stored in custom storage space like NVM3.

Added in 5.2.1#

None.

Added in 5.2.0#

  • Upgraded FreeRTOS kernel to LTS version 11.1.0. The CMSIS OS2 layer and Segger SystemView components were also upgraded to support FreeRTOS 11.1.0.

  • Added the MPA Manager component to the Simplicity SDK. The Memory Protection and Attribute Manager provides a service to configure a variety of memory regions with different qualifiers which are referred to as MPA manager attributes using the Memory Protection Unit (MPU). For example, it is possible to configure a memory region as read-only, non-executable, non-shareable or non-cacheable.

  • System Setup: Added a new sl_main component to manage the device initialization process. This component supports both baremetal and kernel-based applications, replacing the sl_system component. More information is available in the component documentation. For RTOS applications, a migration guide is available. Baremetal applications will be migrated automatically using Simplicity Studio or the SLC CLI: the sl_system_compatibility component will be added to the migrated projects.

    For RTOS applications, the initialization sequence is different and the main() function now operates within the context of an RTOS task.

  • Power Manager and Clock Manager: Introduced new APIs to support advanced use cases involving runtime clock configuration changes.

    • Added slx_power_manager_update_clock_info(), an advanced Power Manager API that refreshes internal oscillator usage data by reading the current CMU clock tree. This is intended for scenarios where the system clock (SYSCLK) is modified at runtime, which is not typically recommended but required by some applications.

    • Added sl_clock_manager_get_sysclk_source() and slx_clock_manager_set_sysclk_source() to retrieve and configure the SYSCLK source oscillator.

  • Clock manager:

    • Added the SL_CLOCK_MANAGER_CTUNE_MFG_HFXO_EN option, allowing users to enable or disable the use of CTUNE values from Manufacturing tokens in the User Data page for LFXO and HFXO calibration.

    • Added a new Clock Manager component, clock_manager_oscillator_calibration_override, which enables overriding default oscillator calibration values with those stored in NVM3. Currently, this feature supports the HFXO oscillator. The component provides new APIs to read, write, and delete HFXO oscillator override calibration values in NVM.

  • Peripheral HAL: Peripheral HAL is an alternative to EMLIB. Peripheral HAL supports Series 3 devices while EMLIB does not. HAL Peripheral also supports Series 2 devices. Note that for Series 2 devices, both EMLIB and Peripheral HAL components can co-exist in the same application (at the cost of increased code size). EMLIB components are not being deprecated and are still supported.

    • The following components and associated source files have been added: hal_acmp, hal_adc, hal_burtc, hal_dcdc_coulomb_counter, hal_emu, hal_eusart, hal_gpcrc, hal_iadc, hal_ldma, hal_leddrv, hal_letimer, hal_pcnt, hal_pixelrz, hal_prs, hal_sysrtc, hal_smu, hal_syscfg, hal_system, hal_timer, hal_usart and hal_wdog.

    • Refer to the documentation for more details.

  • Memory Manager: Added support for managing multiple heaps.

  • UARTDRV: Added a user callback parameter for the UARTDRV_Transmit() and UARTDRV_Receive() functions.

  • NVM3:

    • Enabled secure NVM3 write and read operations using the Host crypto engine instead of the SE crypto engine.

    • Users can use the nvm3_registerCallback() API to register a callback function, which is triggered when the NVM3 instance detects low memory conditions or a cache overflow. The callback allows the application to handle conditions such as freeing up memory by triggering repack. It is recommended that the callback be registered before calling any NVM3 APIs. Additionally, users can deregister the callback using the nvm3_deregisterCallback() API.

    • Users can query the cache size and memory information using the nvm3_getMemInfo() API. This API provides details about the current memory state, including available memory, cache status, and additional cache requirements.

  • Added support for GCC Link Time Optimization (LTO) (using the toolchain_gcc_lto component).

Enhancements#

Added in 5.2.2#

  • Clock Manager: A new configuration option was added to the Clock Manager configuration SL_CLOCK_MANAGER_PCLK_DIVIDER . It can now be set to SL_CLOCK_MANAGER_PCLK_DIV_MIN which will automatically choose the PCLK divider value to get a PCLK frequency respecting the datasheet's operating conditions for it. This configuration option also becomes the default configuration.

  • Clock Manager: Added additional SLC validation for the Clock Manager configurations. The Clock Manager component's validation script now verifies that SYSCLK, HCLK and PCLK respect the datasheet's operating conditions.

Added in 5.2.1#

None.

Added in 5.2.0#

  • Device Headers: Added instance macros LDMA_NUM, GPCRC_NUM and LDMAXBAR_NUM in Series 2 device headers.

  • Device Headers: Improved code quality in the startup and system files.

  • Device Headers: Added the device_supports_wisun provides feature for FG23 and ZG23 slcc components variants with 512kB flash and 64kB RAM.

  • The startup code now sets the MSPLIM register to help detect main stack overflows by triggering a UsageFault, including for non-TrustZone applications.

  • UARTDRV: Added an assertion to validate the baud rate before calculating ticks.

  • Updated the register operations for setting and clearing bits to use their corresponding alias for Series 2 devices and later to improve code size.

Removed Features#

Added in 5.2.2#

None.

Added in 5.2.1#

None.

Added in 5.2.0#

Removed Feature Was Deprecated?
The sl_memory.h file has been removed. Yes
The sl_memory_region.h file has been removed. Yes
The sl_memory_config.h file has been removed. Yes
The emlib_core_debug_config.h file has been removed. Yes
The device_init_nvic component and its associated files have been removed. The interrupt_manager component is available as a replacement. Yes
The ram_interrupt_vector_init component and its associated files have been removed. The interrupt_manager component is available as a replacement. Yes
The silabs_core_sl_malloc component and its associated files have been removed. The memory_manager component is available as a replacement. Yes
The Power Manager has removed two features:
  • Transition events for entering and exiting EM3, along with the ability to subscribe to these events.
  • Requirements for EM2 as the lowest Energy Mode.
On Series 2 devices, the hardware fully manages the transition between EM2 and EM3. The device will enter EM3 if possible (i.e., no hardware requests are active on low-frequency oscillators that cannot operate in EM3); otherwise, it will enter EM2. Consequently, the Power Manager no longer differentiates between EM2 and EM3, treating both as EM2. The hardware autonomously optimizes power savings by shutting down components as needed, whether transitioning to EM3 or not. 		Yes
The AWS software components is removed as it's a thirdparty and deprecated by it's author. Yes

Deprecated Features#

Deprecated in 5.2.2#

None.

Deprecated in 5.2.1#

None.

Deprecated in 5.2.0#

Deprecated Feature Planned Removal Date
System Setup (sl_system) has been deprecated. The new System Setup component (sl_main) should be used when starting a new project. For existing projects:
  • Bare-metal applications can use the System Setup Compatibility Layer. This compatibility layer provides aliased functions, allowing existing applications to use the new System Setup (sl_main) with calls originally written for System Setup (sl_system). When upgrading an existing project to Simplicity SDK 2025.6 using Simplicity Studio or the SLC CLI, the migration will occur automatically.
  • Applications with an RTOS will eventually need to migrate to System Setup (sl_main) manually. Please refer to the sl_system to sl_main migration guide to migrate your application. Note that sl_system remains in the Simplicity SDK and is still supported. The deprecation warning can be suppressed by defining the SL_SUPPRESS_DEPRECATION_WARNINGS_SDK_2025_6 macro in your project. This will allow the project to compile without warnings and defer migration to sl_main.
 June 21, 2026
The sl_memory component was deprecated and replaced with memory_manager_region. June 21, 2026
Interrupt Manager: The SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM configuration has been deprecated in favor of the interrupt_manager_vector_table_in_ram component. Adding the component to a project will result in the same behavior as having SL_INTERRUPT_MANAGER_S2_INTERRUPTS_IN_RAM set to 1. Project upgrade to Simplicity SDK 2025.6 thanks to Simplicity Studio or SLC CLI will automatically be updated. June 21, 2026

API Changes#

New APIs | Modified APIs | Removed APIs | Deprecated APIs

New APIs#

Changed in 5.2.2#

None.

Changed in 5.2.1#

None.

Changed in 5.2.0#

New API Signature

Deprecated API replaced by this (if any)

void slx_power_manager_update_clock_info(void)

None

sl_status_t sl_clock_manager_get_sysclk_source(sl_oscillator_t *oscillator)

None

sl_status_t slx_clock_manager_set_sysclk_source(sl_oscillator_t oscillator)*

None

sl_status_t sl_memory_heap_alloc(sl_memory_heap_t *heap, size_t size, sl_memory_block_type_t type, void **block)

None

sl_status_t sl_memory_heap_alloc_advanced(sl_memory_heap_t *heap, size_t size, size_t align, sl_memory_block_type_t type, void **block)

None

sl_status_t sl_memory_heap_free(sl_memory_heap_t *heap, void *block)

None

sl_status_t sl_memory_heap_calloc(sl_memory_heap_t *heap, size_t item_count, size_t size, sl_memory_block_type_t type, void **block)

None

sl_status_t sl_memory_heap_realloc(sl_memory_heap_t *heap, void *ptr, size_t size, void **block)

None

sl_status_t sl_memory_heap_reserve_block(sl_memory_heap_t *heap, size_t size, size_t align, sl_memory_reservation_t *handle, void **block)

None

sl_status_t sl_memory_heap_create_pool(sl_memory_heap_t *heap, size_t block_size, uint32_t block_count, sl_memory_pool_t *pool_handle)

None

void sl_main_init(void)

None

void sl_main_second_stage_init(void)

None

void sl_main_kernel_start(void)

None

bool sl_main_start_task_should_continue(void)

None

void sl_main_process_action(void)

None

sl_status_t sl_token_manager_init(void)

None

sl_status_t sl_token_manager_get_data(uint32_t token, void *data, uint32_t length)

None

sl_status_t sl_token_manager_set_data(uint32_t token, void *data, uint32_t length)

None

sl_status_t sl_token_manager_get_partial_data(uint32_t token, void *data, uint32_t offset, uint32_t length)

None

sl_status_t sl_token_manager_delete_dynamic_token(uint32_t token)

None

sl_status_t sl_token_manager_increment_counter(uint32_t token)

None

sl_status_t sl_token_manager_get_size(uint32_t token, uint32_t *size_out)

None

sl_status_t sl_i2c_init(const sl_i2c_init_params_t *init_params, sl_i2c_handle_t *i2c_handle)

None

sl_status_t sl_i2c_deinit(sl_i2c_handle_t i2c_handle)

None

sl_status_t sl_i2c_set_frequency(sl_i2c_handle_t i2c_handle, sl_i2c_freq_mode_t freq_mode)

None

sl_status_t sl_i2c_get_frequency(sl_i2c_handle_t i2c_handle, uint32_t *frequency)

None

sl_status_t sl_i2c_set_follower_address(sl_i2c_handle_t i2c_handle, uint16_t follower_address)

None

sl_status_t sl_i2c_configure_dma(sl_i2c_handle_t i2c_handle, sl_i2c_dma_channel_info_t dma_channel)

None

sl_status_t sl_i2c_send_blocking(sl_i2c_handle_t i2c_handle, const uint8_t *tx_buffer, uint16_t tx_len, uint32_t timeout)

None

sl_status_t sl_i2c_receive_blocking(sl_i2c_handle_t i2c_handle, uint8_t *rx_buffer, uint16_t rx_len, uint32_t timeout)

None

sl_status_t sl_i2c_transfer(sl_i2c_handle_t i2c_handle, const uint8_t *tx_buffer, uint16_t tx_len, uint8_t *rx_buffer, uint16_t rx_len)

None

sl_status_t sl_i2c_send_non_blocking(sl_i2c_handle_t i2c_handle, const uint8_t *tx_buffer, uint16_t tx_len, sl_i2c_irq_callback_t i2c_callback, void *context)

None

sl_status_t sl_i2c_receive_non_blocking(sl_i2c_handle_t i2c_handle, uint8_t *rx_buffer, uint16_t rx_len, sl_i2c_irq_callback_t i2c_callback, void *context)

None

Ecode_t DMADRV_AllocateChannelById(unsigned int channelId, void *capabilities)

None

sl_status_t nvm3_registerCallback(nvm3_Handle_t *h, const nvm3_CallbackParams_t *callbackParams, nvm3_LowMemCallback_t lowMemCallback)

None

sl_status_t nvm3_deregisterCallback(nvm3_Handle_t *h)

None

sl_status_t nvm3_getMemInfo(nvm3_Handle_t *h, nvm3_MemInfo_t *memInfo)

None

*API functions prefixed with slx_ are considered experimental and are intended for advanced use cases.

Modified APIs#

Modified in 5.2.2#

None.

Modified in 5.2.1#

None.

Modified in 5.2.0#

Old API

Modified

_CONCAT_2(first, second)

_SL_CONCAT_2(first, second)

_CONCAT_3(first, second, third)

_SL_CONCAT_3(first, second, third)

_CONCAT_4(first, second, third, fourth)

_SL_CONCAT_4(first, second, third, fourth)

sl_iostream_t *sl_iostream_get_handle(char *name)

sl_iostream_t *sl_iostream_get_handle(const char *name)

sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, uint8_t slewrate)

sl_status_t sl_gpio_set_slew_rate(const sl_gpio_t *gpio, uint8_t slewrate)

sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, uint8_t *slewrate)

sl_status_t sl_gpio_get_slew_rate(const sl_gpio_t *gpio, uint8_t *slewrate)

UARTDRV_Callback_t(struct UARTDRV_HandleData *handle, Ecode_t transferStatus, uint8_t *data, UARTDRV_Count_t transferCount)

UARTDRV_Callback_t(struct UARTDRV_HandleData *handle, Ecode_t transferStatus, uint8_t *data, UARTDRV_Count_t transferCount, void *userParam)

UARTDRV_Transmit(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback)

UARTDRV_Transmit(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback, void *userParam)

UARTDRV_Receive(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback)

UARTDRV_Receive(UARTDRV_Handle_t handle, uint8_t *data, UARTDRV_Count_t count, UARTDRV_Callback_t callback, void *userParam)

sl_status_t sl_gpio_set_slew_rate(sl_gpio_port_t port, uint8_t slewrate)

sl_status_t sl_gpio_set_slew_rate(const sl_gpio_t *gpio, uint8_t slewrate)

sl_status_t sl_gpio_get_slew_rate(sl_gpio_port_t port, uint8_t *slewrate)

sl_status_t sl_gpio_get_slew_rate(const sl_gpio_t *gpio, uint8_t *slewrate)

Removed APIs#

Removed in 5.2.2#

None.

Removed in 5.2.1#

None.

Removed in 5.2.0#

Removed API Name

Was Deprecated?

void EMU_MemPwrDown(uint32_t blocks)

Yes

void EMU_UpdateOscConfig(void)

Yes

bool CORE_IrqIsBlocked(IRQn_Type irqN)

Yes

void CORE_GetNvicEnabledMask(CORE_nvicMask_t *mask)

Yes

bool CORE_GetNvicMaskDisableState(const CORE_nvicMask_t *mask)

Yes

void CORE_EnterNvicMask(CORE_nvicMask_t *nvicState, const CORE_nvicMask_t *disable)

Yes

void CORE_NvicDisableMask(const CORE_nvicMask_t *disable)

Yes

void CORE_NvicEnableMask(const CORE_nvicMask_t *enable)

Yes

void CORE_YieldNvicMask(const CORE_nvicMask_t *enable)

Yes

void CORE_NvicMaskSetIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)

Yes

void CORE_NvicMaskClearIRQ(IRQn_Type irqN, CORE_nvicMask_t *mask)

Yes

bool CORE_NvicIRQDisabled(IRQn_Type irqN)

Yes

void * CORE_GetNvicRamTableHandler(IRQn_Type irqN)

Yes

void CORE_SetNvicRamTableHandler(IRQn_Type irqN, void *handler)

Yes

void CORE_InitNvicVectorTable(uint32_t *sourceTable, uint32_t sourceSize, uint32_t *targetTable, uint32_t targetSize, void *defaultHandler, bool overwriteActive)

No

void sl_system_init(void)

Yes

void sl_system_kernel_start(void)

Yes

void sl_device_init_nvic(void)

Yes

void sl_ram_interrupt_vector_init(void)

Yes

Deprecated APIs#

None.

Bug Fixes#

Fixed in 5.2.2#

ID Issue Description GitHub / Salesforce Reference (if any) Affected Software Variants, Hardware, Modes, Host Interfaces
EMLIB
1486153 Fixed a bug where a device could fail to enter EM4 as expected after the EM4 entry sequence had been written. The WFI instruction has been added to the EMU_EnterEM4 function after the EM4 entry sequence finishes. None Series 2 and 3 Devices
Linker
1412916 Fixed an issue in the generated linkerfile that caused warnings when using the arm-none-eabi-objcopy tool. When the .noinit section was empty, the elf file produced by the linker contained a zero-sized .noinit section which caused the warnings. None Series 2 and 3 Devices
1506413 Fixed an issue where the start and end linker symbols for the ramfuncs section's loaded memory address did not match up to the actual addresses where it was appended in FLASH if the section was aligned. The LOADADDR directive is now used to more robustly calculate where the ramfuncs section will be loaded in the FLASH region. None Series 2 and 3 Devices
Services
1512518 Clock Manager: Fixed DPLL maximum frequency configuration on xG22 devices with 38MHz SYSCLK limitation. The DPLL maximum frequency is now correctly set to 38MHz instead of the incorrect 76.8MHz for these devices. None EFR32FG22 family, EFR32BG22C112F352GM32, EFR32BG22C112F352GM40, BGM220SC12WGA
1505125 Clock manager: SL_CLOCK_MANAGER_DEFAULT_HF_CLOCK_SOURCE_AUTO is now always HFRCODPLL for xG21 devices because wireless stacks expect SYSCLK to be on HFRCODPLL. This fixes the issue with the BLE stack not working correctly on custom boards that do not rely on Silicon Labs radio board configurations. None EFR32xG21 devices
1486589 Clock Manager: Fixed default Peripheral Clock (PCLK) divider for Series 2 devices. The default divider is now set to 2 instead of 1. When using a divider of 1, PCLK frequency exceeded the maximum limit when HCLK was greater than 50 MHz, causing incorrect peripheral behavior. None Series 2 Devices
1446522 CLI: Updated status_to_string() function to use the user-configured SL_CLI_EOL_STRING from sl_cli_config.h, instead of the hardcoded "\n". 00328848 Series 2 and 3 Devices
1449079 NVM3: Resolved an issue where, on bootup, the NVM3 handler would advance the next object address to the following page if the last stored object was fragmented. 00327649 Series 2 and 3 Devices
1501919 IOStream: Fixed IOstream issue where EUSART TX/RX and the peripheral were not properly re-enabled after waking from EM2 on instances lacking EM2 support. None Series 2 and 3 Devices

Fixed in 5.2.1#

ID Issue Description GitHub / Salesforce Reference (if any) Affected Software Variants, Hardware, Modes, Host Interfaces
EMLIB
1463186 em_eusart: Fixed EUSART_SpiInit() with the parameter init.eusartDisable to disable the EUSART correctly. None Series 2 and 3 Devices
Peripheral HAL
1468865 Peripheral HAL low-level drivers: Fixed naming issues for the initialization macros SL_HAL_XXXX_CONFIG_DEFAULT. All initialization macros are now SL_HAL_XXXX_INIT_DEFAULT. Fixed several initialization functions to have the following generic prototype: Initialization functions void sl_hal_<peripheral>_init(const sl_hal_<peripheral>_init_t *init). Some initialization functions were using sl_hal_<peripheral>_config_t{}. These naming fixes for initialization macros and initialization datatypes remove the confusion when looking at the Peripheral HAL low-level drivers API. None Series 2 and 3 Devices
1474641 hal_eusart: Updated sl_hal_eusart_reset() to avoid a possible bus fault if the EUSART bus clock is disabled just after sl_hal_eusart_reset(). None Series 2 and 3 Devices
Services
1449985 Memory Manager: Resolved an issue in heap usage calculation that caused inaccuracies in the reported usage. Also fixed a bug where the smallest free or allocated block could be incorrectly reported as SIZE_T_MAX. None Series 2 and 3 Devices
1455259 Clock Manager: Fixed the HFRCO default clock for some series 2 device parts that are limited to 38.4MHz. None EFR32FG22 family, EFR32BG22C112F352GM32, EFR32BG22C112F352GM40, BGM220SC12WGA

Fixed in 5.2.0#

ID Issue Description GitHub / Salesforce Reference (if any) Affected Software Variants, Hardware, Modes, Host Interfaces
Board Drivers
1320271 Microphone: Added an EM1 requirement when initializing the microphones to prevent chip from entering Low Energy modes. None Series 2 and 3 Devices
CMSIS Devices Files
1391130 Changed the license text in some CMSIS headers from MSLA to Zlib. (Affected headers are _dma_descriptor.h, _ldmaxbar_defines.h, _prs_signals.h).
Removed MSLA license text from startup_.c source file as Apache 2.0 license text is already there. 		None Series 2 Devices
1356015 Fixed a bug in the SystemHFRCODPLLClockGet function that caused incorrect frequency values being returned when the SYSTEM_NO_STATIC_MEMORY macro was defined. None Series 2 and 3 Devices
Common
1415010 sl_core: Fixed an issue in CORE_SystemReset where sl_core does not compile when building for a Cortex-M0+ processor due to a missing bitfield in the AIRCR register. None Cortex-M0+ processors
1383487 Toolchain: Fixed the CMSE option for CMake support with IAR compiler. This change consists in replacing specific CMSE toolchain options with a generic compiler option. None IAR CMake Projects
1349599 Linker: Changed permissions to READONLY for .rodata, .copy.table and .zero.table segments in the linker file to fix a warning (LOAD segment with RWX permissions). Removed the --no-warn-rwx-segments option from linker flags. None Series 2 and 3 Devices
1345860 Pin Tool: Added missing support for USART/EUSART COPI (TX) and CIPO (RX) SPI signals. This fixes a bug where USART signals are not selectable in the Pin Tool user interface (for CPC Secondary - UART (USART) component for instance). None Series 2 and 3 Devices
EMLIB
1363972 em_iadc: Added the positive vbat input None EFR32xG27 and EFR32xG29 Families
1408207 em_prs: Added the prsConsumerCORE_M33RXEV definition in the em_prs.h file None Series 2 Devices
FreeRTOS
1414796 FreeRTOS: Fixed an issue where the default configuration file would overwrite the user-provided configuration file. None Series 2 and 3 Devices
1374673 FreeRTOS: Updated to recommend using the interrupt_manager component instead of the deprecated device_init_nvic component. None Series 2 and 3 Devices
Services
1371534 Sleeptimer: Resolved an issue where timeout_ms could overflow by casting it to uint64_t. Additionally, moved the null check for the handle in sl_sleeptimer_stop_timer to occur before dereferencing. None EFR32xG27 and EFR32xG29 Families
1385086 HFXO Manager: The IRQ priority has been reduced to CORE_ATOMIC_BASE_PRIORITY_LEVEL to avoid impacting the execution of customer time-critical code that uses priority levels above CORE_ATOMIC_BASE_PRIORITY_LEVEL. None Series 2 Devices
1413417 Clock Manager: Resolved a compilation warning in sl_clock_manager_hal_s2.c that occurred when building the Clock Manager outside of the Simplicity Studio or SLC environment. None Series 2 Devices
1346413 Memory Manager: Fixed heap corruption in sl_memory_realloc() when reducing an allocated block. None Series 2 and 3 Devices
1354963 Memory Manager: Resolved an issue with the statistics feature where the heap high watermark could overflow. The fix ensures the heap high watermark remains accurate. None Series 2 and 3 Devices
1394833 Memory Manager: Resolved an issue in heap usage calculation that caused inaccuracies in the reported usage. Also fixed a bug where the smallest free or allocated block could be incorrectly reported as SIZE_T_MAX. None Series 2 and 3 Devices
1391237 Memory Manager: Fixed a bug in sl_memory_delete_pool() that allowed deletion of a memory pool even when one or more blocks had not been freed. A runtime check has been added to ensure all active blocks are freed before the pool can be deleted. None Series 2 and 3 Devices
1425220 Memory Manager: Resolved an issue with the memory manager redirect component during SLC generation on Si917 devices. None SiW917
1383887 sl_cos: Resolved issues reported by Coverity tool in sl_cos driver. None Series 2
1411549 IOStream: Resolved an issue in the IOStream UART driver with software flow control that could cause corruption of the reception buffer. None Series 2 and 3
1411549 IOStream: Fixed a rare issue in the UART driver that could lead to reception buffer corruption. None Series 2 and 3
1411549 IOStream: Updated the recommended IOStream streams so they are now visible and can be uninstalled through the user interface. None Series 2 and 3

Chip Enablement#

Added in 5.2.2#

Chip Family OPNs / Boards / OPN Combinations
SiXG301 Family
  • OPN: SiMG301, SiBG301
  • Boards: BRD2719A, BRD4407A, BRD4408A

Note that the SiXG301 devices are only supported with GCC (no IAR support). See the Known Issues and Limitations section for more details.
EFR32BG22L Family
  • OPN: EFR32BG22L122F352GM32
  • Boards: BRD4421A
EFR32FG23L Family
  • OPN: EFR32FG23L010F128GM40, EFR32FG23L020F128GM40
  • Boards: None
EFR32MG26 Family
  • OPN: EFR32MG26B611F2048IM48
  • Boards: None

Added in 5.2.1#

None.

Added in 5.2.0#

Chip Family OPNs / Boards / OPN Combinations
EFR32xG29 Family
  • OPN: EFR32MG29, EFR32BG29
  • Boards: BRD4412A, BRD4413A, BRD4420A
EFR32BG22L Family
  • OPN: EFR32BG22L122F352GM32
  • Boards: None
EFR32BG24L Family
  • OPN: EFR32BG24L010F768IM40, EFR32BG24L210F768IM40
  • Boards: None
MGM260P Family
  • OPN: MGM260PD32VNA, MGM260PD32VNN, MGM260PD22VNA, MGM260PB32VNA, MGM260PB32VNN, MGM260PB22VNA
  • Boards: BRD2713A
BGM260P Family
  • OPN: BGM260PB22VNA, BGM260PB32VNA
  • Boards: None
EFM32PG26 Family
  • Boards: BRD2505A
EFR32BG22 Family
  • Boards: BRD4402C, BRD4403C

Application Example Changes#

New Examples | Modified Examples | Removed Examples | Deprecated Examples

New Examples#

Added in 5.2.2#

Example Name Description Supported Software Variants (if applicable) Supported Modes Supported OPNs / Boards / OPN Combinations Supported Host Interfaces

blink_pwm_freertos

See README

 This sample application demonstrates LED blink using PWM in a FreeRTOS environment.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

iostream_eusart_kernel_freertos

See README

 This sample application demonstrates the use of EUSART communication over the virtual COM port (VCOM) in a FreeRTOS kernel task. The example will echo back any characters it receives over the serial connection. The VCOM serial port can be used over USB or by connecting to port 4902 if the kit is connected via internet.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

memlcd_kernel_freertos

See README

 This sample application demonstrates use of the Memory Liquid Crystal Display (LCD) module in a kernel task, using Silicon Labs Graphics Library (glib). Button 0 is used to clear the LCD. Button 1 is used to print 'Hello World!' on the LCD.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

sleeptimer_kernel_freertos

See README

 This sample application demonstrates the use of timers in an RTOS-based environment using FreeRTOS. The application uses the low-frequency RTC (Real Time Clock) peripheral to create periodic and one-shot timers. The on-board buttons control the timers' stop and start operations. Status is shown on the virtual COM serial port console.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

sleeptimer_wallclock_kernel_freertos

See README

 This sample application demonstrates the use of the sleeptimer's wall clock interface in a FreeRTOS environment. The application uses the low frequency RTC (Real Time Clock) peripheral to set and get the date and time, with operations accessible over a virtual COM serial port.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

tempdrv_kernel_freertos

See README

 This sample application demonstrates use of the temperature sensor driver in a FreeRTOS task.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

dmadrv_kernel_freertos

See README

 This sample application demonstrates how to use DMADRV for DMA transfers in a multitasking environment with FreeRTOS.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

Added in 5.2.1#

None.

Added in 5.2.0#

Example Name Description Supported Software Variants (if applicable) Supported Modes Supported OPNs / Boards / OPN Combinations Supported Host Interfaces

sht4x_i2cspm_baremetal.

See README

This example project demonstrates how to use the I2C Simple Polled Master driver using the SHT4x Relative Humidity and Temperature Sensor in a bare-metal configuration.

  • OPN: efm32pg26
  • Boards: brd2505a

sht4x_i2cspm_kernel_freertos.

See README.

 This example project demonstrates how to use the I2C Simple Polled Master driver using the SHT4X Relative Humidity and Temperature Sensor in a FreeRTOS kernel task.

  • OPN: efm32pg26
  • Boards: brd2505a

sht4x_i2cspm_kernel_micriumos.

See README

This example project demonstrates how to use the I2C Simple Polled Master driver using the SHT4X Relative Humidity and Temperature Sensor in a Micrium OS kernel task.

  • OPN: efm32pg26
  • Boards: brd2505a

common_token_manager_baremetal.

See README

 This example project demonstrates use of the CTM interface. Using the command line interface, the user can write, read and delete tokens.

  • OPN: Series 2 and 3 devices.
  • Boards: Series 2 and 3 boards.

Modified Examples#

Modified in 5.2.2#

  • NVM3: Updated the NVM3 Kernel FreeRTOS sample to support repack.

Removed Examples#

None.

Deprecated Examples#

None.

Known Issues and Limitations#

ID Issue or Limitation Description GitHub / Salesforce Reference (if any) Workaround (if any) Affected Software Variants, Hardware, Modes, Host Interfaces
1415459 SiXG301 is not supported on IAR.
The Simplicity SDK officially supported version of the IAR toolchain, 9.40.1, has a bug at link time that sometimes miscalculates the size of the initializers for copy-to-ram blocks. This miscalculation of initializers is often 4 bytes more than the destination RAM block's size, which throws the [Lp020] error. 		None Using a newer version of IAR may address this issue; however, it is not officially supported by the Simplicity SDK. In this case the #error directive in the Reset_Handler function (startup_simg301.c or startup_sibg301.c) will need to be removed to allow the code to compile. SiXG301 device family.
1462924 sl_main: When using Micrium OS, the start task's stack and Task Control Block (TCB) are not released upon task exit by default, resulting in a memory leak. None Enabling Micrium OS garbage collection resolves this, but may significantly increase RAM and flash usage. This can be achieved by adding the Micrium OS Task Exit Garbage Collection component to your project. Series 2 and 3 Devices
1358452 DMADRV_AllocateChannel function may allocate high priority channels when lower priority channels are available. The function starts channel allocation from index 0 instead of beginning with the lowest priority level (EMDRV_DMADRV_DMA_CH_PRIORITY). None None Series 2 and 3 Devices
1482665 Flash operations on Series-3 devices will take more time compared to Series-2 devices. For Series-3 devices using external flash, repack operations may take longer due to the increased latency of accessing external flash over the bus and security overhead. Bootup time may be impacted if an NVM3 repack operation is triggered. 00330526 None SiXG301 device family.