Clock API Architecture#

The SiWG917 Clock Manager application programming interface (API) defines how clock sources are generated, distributed, and configured across the core processor and peripheral subsystems on the SiWG917.

This section provides an overview of the architecture, core components, and software dependencies that support efficient clock management and synchronization on the SiWG917 platform.

High-Level Architecture#

The SiWG917 clock subsystem supports multiple clock sources and dynamic routing to balance performance and power. Clock signals drive the M4 processor, high-performance peripherals, and ultra-low-power (ULP) domains.

Understanding this structure helps you configure frequencies correctly when switching power modes or enabling wireless subsystems.

Clock Domain Organization#

The SiWG917 SoC architecture is organized into three primary clock domains. Each domain operates across different power states to balance performance and power consumption:

• MCU high-performance (HP) domain

  This domain runs the processor core, debug block, FPU, high-speed peripherals, and HP DMA. It operates in PS4 and PS3 power states and supports performance-oriented tasks such as wireless processing or compute-heavy workloads. Use this domain when your application requires high throughput or frequent interactions with HP peripherals.

• MCU ultra-low-power (ULP) domain

  This domain includes ULP peripherals and an AHB interconnect to the processor. It remains active in PS4, PS3, PS2, and PS1 power states, enabling low-power operation while maintaining essential functionality. Use this domain for sensor interfaces, background timers, or low-duty-cycle workflows that must remain active in sleep modes.

• MCU ultra-ultra-low-power (UULP) VBAT domain

  This always-on domain powers the most critical timing and control peripherals that must remain functional across all power states, including PS4, PS3, PS2, PS1, and PS0. The UULP VBAT domain operates from a battery-backed supply (VBAT) and is clocked by low-frequency sources to minimize power consumption during deep sleep modes.

  • Low-frequency (LF) clock operation: The UULP VBAT domain is clocked exclusively by low-frequency clock sources operating at 32 kHz (such as RC_32KHZ_CLK or XTAL_32KHZ_CLK). These sources are optimized for power consumption while maintaining accurate timekeeping functionality. The reduced operating frequency substantially lowers dynamic power consumption compared to high-frequency clocks operating, enabling continuous operation of battery-backed peripherals, including the watchdog timer, sleep timer, and system real-time clock (SYSRTC), during deep sleep modes and system power cycling events.

  Additional Resources: For information about configuring the system real-time clock, see the System Real-Time Clock (SYSRTC) Developer Guide.

M4 Core (Processor) Clock Generation#

The M4 core clock subsystem supports multiple selectable sources, allowing you to tailor performance and power usage dynamically:

1. High-frequency internal oscillator (RC). On-chip oscillator for fast startup and basic timing operations.

2. External crystal oscillator (XTAL). Provides accurate and stable clocking for precision timing.

3. Phase-locked loop (PLL). Generates high-frequency signals derived from a reference clock for higher performance modes.

Each clock source passes through programmable dividers before reaching the M4 core.
This flexible design allows real-time frequency adjustments to meet application needs, while balancing throughput and energy consumption.

Low-Level Design#

The SiWG917 clock system provides configurable clock routing for high-performance (HP) and ultra-low-power (ULP) peripherals. Each subsystem can select from multiple clock sources, as summarized in the following table.

Note: Peripheral clock sources and routing options vary by subsystem and application mode. See the SiWx917 family Reference Manual – Clock Management Unit for a complete signal map.

Core Components#

The Clock Manager architecture includes modular components that handle initialization, configuration, and runtime management of all clock domains.

• Clock manager module – Provides APIs for clock source selection, divider configuration, PLL control, and runtime clock adjustments.

• emlib – Silicon Labs’ embedded library that enables low-level access to device hardware registers.

• Device initialization layer – Configures default system clocks and applies startup settings automatically.

• Hardware register interface – Allows direct manipulation of SiWG917 clock control registers for advanced custom configurations.

Tip: Use Clock Manager APIs for standard configurations. Direct register access should be reserved for expert-level debugging or timing-critical applications.

Dependencies#

The SiWG917 clock system integrates with multiple hardware and software layers to ensure reliable timing operation.

• Operating system (OS) – Supports bare-metal and RTOS-based implementations.

• Middleware – Includes emlib and device_init modules from the Gecko Software Development Kit (GSDK).

• Drivers – Provide low-level control for oscillators, PLLs, and clock gating mechanisms.

• Hardware interfaces – Implements the SiWG917 hardware blocks for clock generation and distribution. See the SiWx917 family Reference Manual – Clock Management Unit.