Clock API Usage Scenarios#

This section describes common use cases for the Clock Manager application programming interface (API) on the Silicon Labs SiWG917 system-on-chip (SoC). Each scenario explains when to use a specific function, provides a concise code example, and highlights design considerations to ensure correct and efficient clock configuration.

Use Case 1: Switching M4 Core Clock Frequency#

Many SiWG917-based applications require dynamic adjustment of the M4 core frequency to balance performance and power consumption.

Use the sl_si91x_clock_manager_m4_set_core_clk() function to configure both the clock source and the target frequency.

Example: Switching the M4 Core Clock to the SoC PLL#

#include "sl_si91x_clock_manager.h"

#define DESIRED_FREQ 100000000 // 100 MHz

sl_status_t status;

// Set the M4 core clock source to SoC PLL and target frequency to 100 MHz
status = sl_si91x_clock_manager_m4_set_core_clk(M4_SOC_CLK_SRC_PLL, DESIRED_FREQ);

if (status == SL_STATUS_OK) {
  // Core clock successfully switched
} else {
  // Handle error condition
}

Note: Always confirm that the selected clock source and frequency are valid for your hardware configuration. Unsupported combinations can cause clock instability or violate device operating limits.

Use Case 2: Adjusting PLL Frequency for Peripheral Timing#

Some peripherals require precise clock frequencies to operate correctly. In these cases, you can modify the SoC phase-locked loop (PLL) output.

The sl_si91x_clock_manager_set_pll_freq() API allows you to define the PLL frequency and reference clock dynamically.

Example: Configuring the SoC PLL#

#include "sl_si91x_clock_manager.h"

#define PLL_FREQ    120000000 // 120 MHz
#define REF_CLK     40000000  // 40 MHz reference

sl_status_t status;

// Configure the SoC PLL to 120 MHz with a 40 MHz reference clock
status = sl_si91x_clock_manager_set_pll_freq(SOC_PLL, PLL_FREQ, REF_CLK);

if (status == SL_STATUS_OK) {
  // PLL frequency configured successfully
} else {
  // Handle PLL configuration error
}

Note:
Replace SOC_PLL with the correct PLL type enumeration for your target configuration.
Verify that both the target frequency and reference clock values are supported for the SiWG917 family to prevent timing errors or hardware faults.

Use Case 3: Introducing Timing Delays#

Some applications require short, controlled timing gaps between operations. The sl_si91x_delay_ms() function introduces a blocking delay for a specified duration (in milliseconds).

Use this function during initialization or short pauses, not for real-time or low-power operations.

Example: Inserting a 500 ms Delay#

#include "sl_si91x_clock_manager.h"

#define DELAY_MS 500 // 500 milliseconds

// Create a blocking delay of 500 ms
sl_si91x_delay_ms(DELAY_MS);

// Code execution resumes after delay

Caution:
Because this is a blocking delay, it halts all CPU activity for the specified duration.
Avoid using it in real-time, low-power, or interrupt-driven contexts.
For non-blocking behavior, consider using timers or event callbacks.