Serial Synchronous Interface (SSI) Appendix#
This appendix provides reference material for the Serial Synchronous Interface (SSI) peripheral. It includes a glossary of terms, a list of acronyms, extended usage examples, and frequently asked questions (FAQs). Use this section as a quick lookup guide when developing with SSI.
Appendix Overview#
The appendix is organized into the following sections:
Glossary: Defines important SSI-related terms.
Acronyms: Expands abbreviations commonly used in SSI development.
Extended Examples: Provides links to example projects in the WiSeConnect software development kit (SDK).
FAQs: Answers common questions about SSI usage, performance, and troubleshooting.
Glossary#
The glossary defines key terms related to SSI and its supported protocols.
Term | Description |
|---|---|
CMSIS | Cortex Microcontroller Software Interface Standard – ARM's standardized interface for Cortex-M microcontrollers. |
CPHA | Clock Phase – Determines when data is sampled relative to the clock edge. |
CPOL | Clock Polarity – Determines the idle state of the serial clock. |
DMA | Direct Memory Access – Transfers data without central processing unit (CPU) intervention. |
Dual SPI | Dual Serial Peripheral Interface – Uses two data lines for increased throughput. |
FIFO | First In, First Out – A buffer structure used in the SSI peripheral. |
HAL | Hardware Abstraction Layer – A software layer that provides a uniform interface to hardware peripherals. |
Microwire | A half-duplex serial protocol developed by National Semiconductor. |
PLL | Phase-Locked Loop – A control system that generates a stable, high-frequency clock from a lower-frequency reference. |
Primary | The device that initiates and controls serial transfers. |
PS1 | Power State 1 – Ultra-low power or standby state. The CPU and most peripherals are halted. Fast wake-up is possible. Used for deep energy savings. |
PS2 | Power State 2 – Low performance (up to 20–32 MHz CPU, 0.75 V supply). Many features and peripherals enter low-power mode. Maintains limited processing capability while conserving power. |
PS3 | Power State 3 – Medium performance (up to 90 MHz CPU, 1.05 V supply). Some features and peripherals may be disabled or limited. Consumes less power than PS4 but remains responsive. |
PS4 | Power State 4 – Maximum performance (up to 180 MHz CPU, 1.15 V supply). All features and peripherals are available. Used for full-speed operations and during startup after reset. |
Quad SPI | Quad Serial Peripheral Interface – Uses four data lines for maximum throughput. |
RTOS | Real-Time Operating System – An operating system designed for real-time applications with deterministic timing. |
SDK | Software Development Kit – A collection of software tools and libraries for application development. |
Secondary | The device that responds to transfers initiated by the Primary. |
SPI | Serial Peripheral Interface – A synchronous serial communication protocol developed by Motorola. |
SSI | Serial Synchronous Interface – A configurable peripheral that supports multiple protocols. |
SSP | Synchronous Serial Protocol – A communication protocol developed by Texas Instruments. |
ULP | Ultra-Low Power – A power domain designed for minimal energy consumption. |
Acronyms#
Acronym | Description |
|---|---|
APB | Advanced Peripheral Bus |
CPHA | Clock Phase |
CPOL | Clock Polarity |
CS | Chip Select |
DMA | Direct Memory Access |
FIFO | First In, First Out |
GPIO | General Purpose Input/Output |
MISO | Master In Slave Out |
MOSI | Master Out Slave In |
PMU | Power Management Unit |
PS1–PS4 | Power Save Modes |
RX | Receive |
SCK | Serial Clock |
SLC | Simplicity Studio Component |
SPI | Serial Peripheral Interface |
SSI | Serial Synchronous Interface |
SSP | Synchronous Serial Protocol |
TX | Transmit |
UC | Universal Configurator |
ULP | Ultra-Low Power |
Extended Examples#
This section provides links to example projects that demonstrate SSI features and integration within the WiSeConnect SDK. Use these examples to accelerate development and validate configurations.
Basic SSI Examples#
SSI Master: examples/si91x_soc/peripheral/sl_si91x_ssi_master/
SSI Slave: examples/si91x_soc/peripheral/sl_si91x_ssi_slave/
ULP SSI Master Example: examples/si91x_soc/peripheral/sl_si91x_ulp_ssi_master/
Sensor Integration Examples#
ICM40627 Inertial Measurement Unit (IMU) with SPI and DMA: examples/si91x_soc/peripheral/sl_si91x_icm40627/ -- Demonstrates configuring SSI for high-speed sensor data acquisition using Direct Memory Access (DMA) and burst reads.
Memory LCD (Baremetal, SPI): examples/si91x_soc/peripheral/memlcd_baremetal/ -- Demonstrates driving a memory LCD with SSI and frame buffer updates.
FAQ#
This section answers frequently asked questions about SSI functionality, modes, and troubleshooting.
Q: What is the maximum Serial Peripheral Interface (SPI) clock frequency supported?#
A: The SSI peripheral supports up to 40 MHz for standard SPI mode and up to 10 MHz for Dual/Quad SPI modes.
Q: Can I use both Direct Memory Access (DMA) and interrupts simultaneously?#
A: Yes. When DMA is enabled, the driver uses DMA for data transfer and interrupts for completion notification and error handling.
Q: How do I switch between different SPI modes (Clock Polarity and Clock Phase)?#
A: Configure the frame format in the Universal Configurator (UC) or
set the appropriate parameters in the sl_si91x_ssi_set_configuration()
function.
Q: What happens to SSI configuration during sleep modes?#
A: For Ultra-Low-Power (ULP) SSI, configuration is retained during Power State 2 (PS2) and Power State 1 (PS1). For regular SSI, you must reinitialize the peripheral after waking from deep sleep.
Q: Can I communicate with multiple slave devices?#
A: Yes. The SSI Primary supports up to four chip select (CS) lines for addressing multiple slave devices.
Q: How do I troubleshoot timing issues in Dual or Quad SPI?#
A: Use a logic analyzer to verify clock phase, data setup and hold times, and ensure adequate wait cycles between command/address and data phases.
Q: What is the difference between blocking and non-blocking transfers?#
A: Blocking transfers wait until completion before returning. Non-blocking transfers (using DMA) return immediately and use callbacks to signal completion.
Q: How do I optimize power consumption with SSI?#
A: Use the ULP SSI instance with ULP General Purpose Input/Output (GPIO), enable Power State 2 (PS2), and leverage DMA for autonomous operation during sleep.
Q: Can I use SSI with external flash memory?#
A: Yes. The SSI peripheral works well for flash memory communication, particularly with Dual or Quad SPI modes for higher throughput.
Q: What should I do if I encounter persistent communication errors?#
A: Check hardware connections, verify clock settings, ensure proper impedance matching, and implement error recovery mechanisms as described in the debugging section.
Additional Resources#
Use these resources for further reference and support:
SSI API Documentation: WiSeConnect SSI API
WiSeConnect SDK: WiSeConnect GitHub Repository
Community Support: Silicon Labs Community
Technical Support: Silicon Labs Support